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GPIO_demo_timing_summary_routed.rpt 225KB

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  1. Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  2. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  3. | Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
  4. | Date : Fri Apr 09 23:16:38 2021
  5. | Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
  6. | Command : report_timing_summary -warn_on_violation -max_paths 10 -file GPIO_demo_timing_summary_routed.rpt -rpx GPIO_demo_timing_summary_routed.rpx
  7. | Design : GPIO_demo
  8. | Device : 7a35t-cpg236
  9. | Speed File : -1 PRODUCTION 1.16 2016-11-09
  10. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  11. Timing Summary Report
  12. ------------------------------------------------------------------------------------------------
  13. | Timer Settings
  14. | --------------
  15. ------------------------------------------------------------------------------------------------
  16. Enable Multi Corner Analysis : Yes
  17. Enable Pessimism Removal : Yes
  18. Pessimism Removal Resolution : Nearest Common Node
  19. Enable Input Delay Default Clock : No
  20. Enable Preset / Clear Arcs : No
  21. Disable Flight Delays : No
  22. Ignore I/O Paths : No
  23. Timing Early Launch at Borrowing Latches : false
  24. Corner Analyze Analyze
  25. Name Max Paths Min Paths
  26. ------ --------- ---------
  27. Slow Yes Yes
  28. Fast Yes Yes
  29. check_timing report
  30. Table of Contents
  31. -----------------
  32. 1. checking no_clock
  33. 2. checking constant_clock
  34. 3. checking pulse_width_clock
  35. 4. checking unconstrained_internal_endpoints
  36. 5. checking no_input_delay
  37. 6. checking no_output_delay
  38. 7. checking multiple_clock
  39. 8. checking generated_clocks
  40. 9. checking loops
  41. 10. checking partial_input_delay
  42. 11. checking partial_output_delay
  43. 12. checking latch_loops
  44. 1. checking no_clock
  45. --------------------
  46. There are 0 register/latch pins with no clock.
  47. 2. checking constant_clock
  48. --------------------------
  49. There are 0 register/latch pins with constant_clock.
  50. 3. checking pulse_width_clock
  51. -----------------------------
  52. There are 0 register/latch pins which need pulse_width check
  53. 4. checking unconstrained_internal_endpoints
  54. --------------------------------------------
  55. There are 0 pins that are not constrained for maximum delay.
  56. There are 0 pins that are not constrained for maximum delay due to constant clock.
  57. 5. checking no_input_delay
  58. --------------------------
  59. There are 7 input ports with no input delay specified. (HIGH)
  60. There are 0 input ports with no input delay but user has a false path constraint.
  61. 6. checking no_output_delay
  62. ---------------------------
  63. There are 29 ports with no output delay specified. (HIGH)
  64. There are 0 ports with no output delay but user has a false path constraint
  65. There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
  66. 7. checking multiple_clock
  67. --------------------------
  68. There are 0 register/latch pins with multiple clocks.
  69. 8. checking generated_clocks
  70. ----------------------------
  71. There are 0 generated clocks that are not connected to a clock source.
  72. 9. checking loops
  73. -----------------
  74. There are 0 combinational loops in the design.
  75. 10. checking partial_input_delay
  76. --------------------------------
  77. There are 0 input ports with partial input delay specified.
  78. 11. checking partial_output_delay
  79. ---------------------------------
  80. There are 0 ports with partial output delay specified.
  81. 12. checking latch_loops
  82. ------------------------
  83. There are 0 combinational latch loops in the design through latch input
  84. ------------------------------------------------------------------------------------------------
  85. | Design Timing Summary
  86. | ---------------------
  87. ------------------------------------------------------------------------------------------------
  88. WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
  89. ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
  90. 3.744 0.000 0 1137 0.064 0.000 0 1137 3.000 0.000 0 585
  91. All user specified timing constraints are met.
  92. ------------------------------------------------------------------------------------------------
  93. | Clock Summary
  94. | -------------
  95. ------------------------------------------------------------------------------------------------
  96. Clock Waveform(ns) Period(ns) Frequency(MHz)
  97. ----- ------------ ---------- --------------
  98. sys_clk_pin {0.000 5.000} 10.000 100.000
  99. clk_out1_clk_wiz_0 {0.000 4.630} 9.259 108.000
  100. clkfbout_clk_wiz_0 {0.000 5.000} 10.000 100.000
  101. ------------------------------------------------------------------------------------------------
  102. | Intra Clock Table
  103. | -----------------
  104. ------------------------------------------------------------------------------------------------
  105. Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
  106. ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
  107. sys_clk_pin 4.802 0.000 0 534 0.183 0.000 0 534 3.000 0.000 0 244
  108. clk_out1_clk_wiz_0 3.744 0.000 0 603 0.064 0.000 0 603 4.130 0.000 0 338
  109. clkfbout_clk_wiz_0 7.845 0.000 0 3
  110. ------------------------------------------------------------------------------------------------
  111. | Inter Clock Table
  112. | -----------------
  113. ------------------------------------------------------------------------------------------------
  114. From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
  115. ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
  116. ------------------------------------------------------------------------------------------------
  117. | Other Path Groups Table
  118. | -----------------------
  119. ------------------------------------------------------------------------------------------------
  120. Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
  121. ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
  122. ------------------------------------------------------------------------------------------------
  123. | Timing Details
  124. | --------------
  125. ------------------------------------------------------------------------------------------------
  126. ---------------------------------------------------------------------------------------------------
  127. From Clock: sys_clk_pin
  128. To Clock: sys_clk_pin
  129. Setup : 0 Failing Endpoints, Worst Slack 4.802ns, Total Violation 0.000ns
  130. Hold : 0 Failing Endpoints, Worst Slack 0.183ns, Total Violation 0.000ns
  131. PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns
  132. ---------------------------------------------------------------------------------------------------
  133. Max Delay Paths
  134. --------------------------------------------------------------------------------------
  135. Slack (MET) : 4.802ns (required time - arrival time)
  136. Source: tmrCntr_reg[7]/C
  137. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  138. Destination: tmrCntr_reg[0]/R
  139. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  140. Path Group: sys_clk_pin
  141. Path Type: Setup (Max at Slow Process Corner)
  142. Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  143. Data Path Delay: 4.711ns (logic 0.952ns (20.210%) route 3.759ns (79.790%))
  144. Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
  145. Clock Path Skew: -0.023ns (DCD - SCD + CPR)
  146. Destination Clock Delay (DCD): 4.850ns = ( 14.850 - 10.000 )
  147. Source Clock Delay (SCD): 5.147ns
  148. Clock Pessimism Removal (CPR): 0.274ns
  149. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  150. Total System Jitter (TSJ): 0.071ns
  151. Total Input Jitter (TIJ): 0.000ns
  152. Discrete Jitter (DJ): 0.000ns
  153. Phase Error (PE): 0.000ns
  154. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  155. ------------------------------------------------------------------- -------------------
  156. (clock sys_clk_pin rise edge)
  157. 0.000 0.000 r
  158. W5 0.000 0.000 r CLK (IN)
  159. net (fo=0) 0.000 0.000 CLK
  160. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  161. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  162. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  163. net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
  164. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  165. ------------------------------------------------------------------- -------------------
  166. SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
  167. net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
  168. SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
  169. net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
  170. SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
  171. net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
  172. SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
  173. net (fo=6, routed) 0.736 8.867 eqOp2_in
  174. SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
  175. net (fo=27, routed) 0.867 9.858 tmrCntr0
  176. SLICE_X62Y18 FDRE r tmrCntr_reg[0]/R
  177. ------------------------------------------------------------------- -------------------
  178. (clock sys_clk_pin rise edge)
  179. 10.000 10.000 r
  180. W5 0.000 10.000 r CLK (IN)
  181. net (fo=0) 0.000 10.000 CLK
  182. W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
  183. net (fo=1, routed) 1.862 13.250 CLK_IBUF
  184. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
  185. net (fo=243, routed) 1.509 14.850 CLK_IBUF_BUFG
  186. SLICE_X62Y18 FDRE r tmrCntr_reg[0]/C
  187. clock pessimism 0.274 15.124
  188. clock uncertainty -0.035 15.089
  189. SLICE_X62Y18 FDRE (Setup_fdre_C_R) -0.429 14.660 tmrCntr_reg[0]
  190. -------------------------------------------------------------------
  191. required time 14.660
  192. arrival time -9.858
  193. -------------------------------------------------------------------
  194. slack 4.802
  195. Slack (MET) : 4.802ns (required time - arrival time)
  196. Source: tmrCntr_reg[7]/C
  197. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  198. Destination: tmrCntr_reg[1]/R
  199. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  200. Path Group: sys_clk_pin
  201. Path Type: Setup (Max at Slow Process Corner)
  202. Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  203. Data Path Delay: 4.711ns (logic 0.952ns (20.210%) route 3.759ns (79.790%))
  204. Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
  205. Clock Path Skew: -0.023ns (DCD - SCD + CPR)
  206. Destination Clock Delay (DCD): 4.850ns = ( 14.850 - 10.000 )
  207. Source Clock Delay (SCD): 5.147ns
  208. Clock Pessimism Removal (CPR): 0.274ns
  209. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  210. Total System Jitter (TSJ): 0.071ns
  211. Total Input Jitter (TIJ): 0.000ns
  212. Discrete Jitter (DJ): 0.000ns
  213. Phase Error (PE): 0.000ns
  214. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  215. ------------------------------------------------------------------- -------------------
  216. (clock sys_clk_pin rise edge)
  217. 0.000 0.000 r
  218. W5 0.000 0.000 r CLK (IN)
  219. net (fo=0) 0.000 0.000 CLK
  220. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  221. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  222. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  223. net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
  224. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  225. ------------------------------------------------------------------- -------------------
  226. SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
  227. net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
  228. SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
  229. net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
  230. SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
  231. net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
  232. SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
  233. net (fo=6, routed) 0.736 8.867 eqOp2_in
  234. SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
  235. net (fo=27, routed) 0.867 9.858 tmrCntr0
  236. SLICE_X62Y18 FDRE r tmrCntr_reg[1]/R
  237. ------------------------------------------------------------------- -------------------
  238. (clock sys_clk_pin rise edge)
  239. 10.000 10.000 r
  240. W5 0.000 10.000 r CLK (IN)
  241. net (fo=0) 0.000 10.000 CLK
  242. W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
  243. net (fo=1, routed) 1.862 13.250 CLK_IBUF
  244. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
  245. net (fo=243, routed) 1.509 14.850 CLK_IBUF_BUFG
  246. SLICE_X62Y18 FDRE r tmrCntr_reg[1]/C
  247. clock pessimism 0.274 15.124
  248. clock uncertainty -0.035 15.089
  249. SLICE_X62Y18 FDRE (Setup_fdre_C_R) -0.429 14.660 tmrCntr_reg[1]
  250. -------------------------------------------------------------------
  251. required time 14.660
  252. arrival time -9.858
  253. -------------------------------------------------------------------
  254. slack 4.802
  255. Slack (MET) : 4.802ns (required time - arrival time)
  256. Source: tmrCntr_reg[7]/C
  257. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  258. Destination: tmrCntr_reg[2]/R
  259. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  260. Path Group: sys_clk_pin
  261. Path Type: Setup (Max at Slow Process Corner)
  262. Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  263. Data Path Delay: 4.711ns (logic 0.952ns (20.210%) route 3.759ns (79.790%))
  264. Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
  265. Clock Path Skew: -0.023ns (DCD - SCD + CPR)
  266. Destination Clock Delay (DCD): 4.850ns = ( 14.850 - 10.000 )
  267. Source Clock Delay (SCD): 5.147ns
  268. Clock Pessimism Removal (CPR): 0.274ns
  269. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  270. Total System Jitter (TSJ): 0.071ns
  271. Total Input Jitter (TIJ): 0.000ns
  272. Discrete Jitter (DJ): 0.000ns
  273. Phase Error (PE): 0.000ns
  274. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  275. ------------------------------------------------------------------- -------------------
  276. (clock sys_clk_pin rise edge)
  277. 0.000 0.000 r
  278. W5 0.000 0.000 r CLK (IN)
  279. net (fo=0) 0.000 0.000 CLK
  280. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  281. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  282. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  283. net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
  284. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  285. ------------------------------------------------------------------- -------------------
  286. SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
  287. net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
  288. SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
  289. net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
  290. SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
  291. net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
  292. SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
  293. net (fo=6, routed) 0.736 8.867 eqOp2_in
  294. SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
  295. net (fo=27, routed) 0.867 9.858 tmrCntr0
  296. SLICE_X62Y18 FDRE r tmrCntr_reg[2]/R
  297. ------------------------------------------------------------------- -------------------
  298. (clock sys_clk_pin rise edge)
  299. 10.000 10.000 r
  300. W5 0.000 10.000 r CLK (IN)
  301. net (fo=0) 0.000 10.000 CLK
  302. W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
  303. net (fo=1, routed) 1.862 13.250 CLK_IBUF
  304. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
  305. net (fo=243, routed) 1.509 14.850 CLK_IBUF_BUFG
  306. SLICE_X62Y18 FDRE r tmrCntr_reg[2]/C
  307. clock pessimism 0.274 15.124
  308. clock uncertainty -0.035 15.089
  309. SLICE_X62Y18 FDRE (Setup_fdre_C_R) -0.429 14.660 tmrCntr_reg[2]
  310. -------------------------------------------------------------------
  311. required time 14.660
  312. arrival time -9.858
  313. -------------------------------------------------------------------
  314. slack 4.802
  315. Slack (MET) : 4.802ns (required time - arrival time)
  316. Source: tmrCntr_reg[7]/C
  317. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  318. Destination: tmrCntr_reg[3]/R
  319. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  320. Path Group: sys_clk_pin
  321. Path Type: Setup (Max at Slow Process Corner)
  322. Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  323. Data Path Delay: 4.711ns (logic 0.952ns (20.210%) route 3.759ns (79.790%))
  324. Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
  325. Clock Path Skew: -0.023ns (DCD - SCD + CPR)
  326. Destination Clock Delay (DCD): 4.850ns = ( 14.850 - 10.000 )
  327. Source Clock Delay (SCD): 5.147ns
  328. Clock Pessimism Removal (CPR): 0.274ns
  329. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  330. Total System Jitter (TSJ): 0.071ns
  331. Total Input Jitter (TIJ): 0.000ns
  332. Discrete Jitter (DJ): 0.000ns
  333. Phase Error (PE): 0.000ns
  334. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  335. ------------------------------------------------------------------- -------------------
  336. (clock sys_clk_pin rise edge)
  337. 0.000 0.000 r
  338. W5 0.000 0.000 r CLK (IN)
  339. net (fo=0) 0.000 0.000 CLK
  340. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  341. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  342. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  343. net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
  344. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  345. ------------------------------------------------------------------- -------------------
  346. SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
  347. net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
  348. SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
  349. net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
  350. SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
  351. net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
  352. SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
  353. net (fo=6, routed) 0.736 8.867 eqOp2_in
  354. SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
  355. net (fo=27, routed) 0.867 9.858 tmrCntr0
  356. SLICE_X62Y18 FDRE r tmrCntr_reg[3]/R
  357. ------------------------------------------------------------------- -------------------
  358. (clock sys_clk_pin rise edge)
  359. 10.000 10.000 r
  360. W5 0.000 10.000 r CLK (IN)
  361. net (fo=0) 0.000 10.000 CLK
  362. W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
  363. net (fo=1, routed) 1.862 13.250 CLK_IBUF
  364. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
  365. net (fo=243, routed) 1.509 14.850 CLK_IBUF_BUFG
  366. SLICE_X62Y18 FDRE r tmrCntr_reg[3]/C
  367. clock pessimism 0.274 15.124
  368. clock uncertainty -0.035 15.089
  369. SLICE_X62Y18 FDRE (Setup_fdre_C_R) -0.429 14.660 tmrCntr_reg[3]
  370. -------------------------------------------------------------------
  371. required time 14.660
  372. arrival time -9.858
  373. -------------------------------------------------------------------
  374. slack 4.802
  375. Slack (MET) : 4.965ns (required time - arrival time)
  376. Source: tmrCntr_reg[7]/C
  377. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  378. Destination: tmrCntr_reg[4]/R
  379. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  380. Path Group: sys_clk_pin
  381. Path Type: Setup (Max at Slow Process Corner)
  382. Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  383. Data Path Delay: 4.571ns (logic 0.952ns (20.828%) route 3.619ns (79.172%))
  384. Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
  385. Clock Path Skew: 0.000ns (DCD - SCD + CPR)
  386. Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 )
  387. Source Clock Delay (SCD): 5.147ns
  388. Clock Pessimism Removal (CPR): 0.298ns
  389. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  390. Total System Jitter (TSJ): 0.071ns
  391. Total Input Jitter (TIJ): 0.000ns
  392. Discrete Jitter (DJ): 0.000ns
  393. Phase Error (PE): 0.000ns
  394. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  395. ------------------------------------------------------------------- -------------------
  396. (clock sys_clk_pin rise edge)
  397. 0.000 0.000 r
  398. W5 0.000 0.000 r CLK (IN)
  399. net (fo=0) 0.000 0.000 CLK
  400. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  401. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  402. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  403. net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
  404. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  405. ------------------------------------------------------------------- -------------------
  406. SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
  407. net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
  408. SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
  409. net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
  410. SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
  411. net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
  412. SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
  413. net (fo=6, routed) 0.736 8.867 eqOp2_in
  414. SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
  415. net (fo=27, routed) 0.727 9.718 tmrCntr0
  416. SLICE_X62Y19 FDRE r tmrCntr_reg[4]/R
  417. ------------------------------------------------------------------- -------------------
  418. (clock sys_clk_pin rise edge)
  419. 10.000 10.000 r
  420. W5 0.000 10.000 r CLK (IN)
  421. net (fo=0) 0.000 10.000 CLK
  422. W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
  423. net (fo=1, routed) 1.862 13.250 CLK_IBUF
  424. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
  425. net (fo=243, routed) 1.508 14.849 CLK_IBUF_BUFG
  426. SLICE_X62Y19 FDRE r tmrCntr_reg[4]/C
  427. clock pessimism 0.298 15.147
  428. clock uncertainty -0.035 15.112
  429. SLICE_X62Y19 FDRE (Setup_fdre_C_R) -0.429 14.683 tmrCntr_reg[4]
  430. -------------------------------------------------------------------
  431. required time 14.683
  432. arrival time -9.718
  433. -------------------------------------------------------------------
  434. slack 4.965
  435. Slack (MET) : 4.965ns (required time - arrival time)
  436. Source: tmrCntr_reg[7]/C
  437. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  438. Destination: tmrCntr_reg[5]/R
  439. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  440. Path Group: sys_clk_pin
  441. Path Type: Setup (Max at Slow Process Corner)
  442. Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  443. Data Path Delay: 4.571ns (logic 0.952ns (20.828%) route 3.619ns (79.172%))
  444. Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
  445. Clock Path Skew: 0.000ns (DCD - SCD + CPR)
  446. Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 )
  447. Source Clock Delay (SCD): 5.147ns
  448. Clock Pessimism Removal (CPR): 0.298ns
  449. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  450. Total System Jitter (TSJ): 0.071ns
  451. Total Input Jitter (TIJ): 0.000ns
  452. Discrete Jitter (DJ): 0.000ns
  453. Phase Error (PE): 0.000ns
  454. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  455. ------------------------------------------------------------------- -------------------
  456. (clock sys_clk_pin rise edge)
  457. 0.000 0.000 r
  458. W5 0.000 0.000 r CLK (IN)
  459. net (fo=0) 0.000 0.000 CLK
  460. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  461. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  462. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  463. net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
  464. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  465. ------------------------------------------------------------------- -------------------
  466. SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
  467. net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
  468. SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
  469. net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
  470. SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
  471. net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
  472. SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
  473. net (fo=6, routed) 0.736 8.867 eqOp2_in
  474. SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
  475. net (fo=27, routed) 0.727 9.718 tmrCntr0
  476. SLICE_X62Y19 FDRE r tmrCntr_reg[5]/R
  477. ------------------------------------------------------------------- -------------------
  478. (clock sys_clk_pin rise edge)
  479. 10.000 10.000 r
  480. W5 0.000 10.000 r CLK (IN)
  481. net (fo=0) 0.000 10.000 CLK
  482. W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
  483. net (fo=1, routed) 1.862 13.250 CLK_IBUF
  484. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
  485. net (fo=243, routed) 1.508 14.849 CLK_IBUF_BUFG
  486. SLICE_X62Y19 FDRE r tmrCntr_reg[5]/C
  487. clock pessimism 0.298 15.147
  488. clock uncertainty -0.035 15.112
  489. SLICE_X62Y19 FDRE (Setup_fdre_C_R) -0.429 14.683 tmrCntr_reg[5]
  490. -------------------------------------------------------------------
  491. required time 14.683
  492. arrival time -9.718
  493. -------------------------------------------------------------------
  494. slack 4.965
  495. Slack (MET) : 4.965ns (required time - arrival time)
  496. Source: tmrCntr_reg[7]/C
  497. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  498. Destination: tmrCntr_reg[6]/R
  499. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  500. Path Group: sys_clk_pin
  501. Path Type: Setup (Max at Slow Process Corner)
  502. Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  503. Data Path Delay: 4.571ns (logic 0.952ns (20.828%) route 3.619ns (79.172%))
  504. Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
  505. Clock Path Skew: 0.000ns (DCD - SCD + CPR)
  506. Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 )
  507. Source Clock Delay (SCD): 5.147ns
  508. Clock Pessimism Removal (CPR): 0.298ns
  509. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  510. Total System Jitter (TSJ): 0.071ns
  511. Total Input Jitter (TIJ): 0.000ns
  512. Discrete Jitter (DJ): 0.000ns
  513. Phase Error (PE): 0.000ns
  514. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  515. ------------------------------------------------------------------- -------------------
  516. (clock sys_clk_pin rise edge)
  517. 0.000 0.000 r
  518. W5 0.000 0.000 r CLK (IN)
  519. net (fo=0) 0.000 0.000 CLK
  520. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  521. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  522. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  523. net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
  524. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  525. ------------------------------------------------------------------- -------------------
  526. SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
  527. net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
  528. SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
  529. net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
  530. SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
  531. net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
  532. SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
  533. net (fo=6, routed) 0.736 8.867 eqOp2_in
  534. SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
  535. net (fo=27, routed) 0.727 9.718 tmrCntr0
  536. SLICE_X62Y19 FDRE r tmrCntr_reg[6]/R
  537. ------------------------------------------------------------------- -------------------
  538. (clock sys_clk_pin rise edge)
  539. 10.000 10.000 r
  540. W5 0.000 10.000 r CLK (IN)
  541. net (fo=0) 0.000 10.000 CLK
  542. W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
  543. net (fo=1, routed) 1.862 13.250 CLK_IBUF
  544. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
  545. net (fo=243, routed) 1.508 14.849 CLK_IBUF_BUFG
  546. SLICE_X62Y19 FDRE r tmrCntr_reg[6]/C
  547. clock pessimism 0.298 15.147
  548. clock uncertainty -0.035 15.112
  549. SLICE_X62Y19 FDRE (Setup_fdre_C_R) -0.429 14.683 tmrCntr_reg[6]
  550. -------------------------------------------------------------------
  551. required time 14.683
  552. arrival time -9.718
  553. -------------------------------------------------------------------
  554. slack 4.965
  555. Slack (MET) : 4.965ns (required time - arrival time)
  556. Source: tmrCntr_reg[7]/C
  557. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  558. Destination: tmrCntr_reg[7]/R
  559. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  560. Path Group: sys_clk_pin
  561. Path Type: Setup (Max at Slow Process Corner)
  562. Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  563. Data Path Delay: 4.571ns (logic 0.952ns (20.828%) route 3.619ns (79.172%))
  564. Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
  565. Clock Path Skew: 0.000ns (DCD - SCD + CPR)
  566. Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 )
  567. Source Clock Delay (SCD): 5.147ns
  568. Clock Pessimism Removal (CPR): 0.298ns
  569. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  570. Total System Jitter (TSJ): 0.071ns
  571. Total Input Jitter (TIJ): 0.000ns
  572. Discrete Jitter (DJ): 0.000ns
  573. Phase Error (PE): 0.000ns
  574. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  575. ------------------------------------------------------------------- -------------------
  576. (clock sys_clk_pin rise edge)
  577. 0.000 0.000 r
  578. W5 0.000 0.000 r CLK (IN)
  579. net (fo=0) 0.000 0.000 CLK
  580. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  581. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  582. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  583. net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
  584. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  585. ------------------------------------------------------------------- -------------------
  586. SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
  587. net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
  588. SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
  589. net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
  590. SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
  591. net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
  592. SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
  593. net (fo=6, routed) 0.736 8.867 eqOp2_in
  594. SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
  595. net (fo=27, routed) 0.727 9.718 tmrCntr0
  596. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/R
  597. ------------------------------------------------------------------- -------------------
  598. (clock sys_clk_pin rise edge)
  599. 10.000 10.000 r
  600. W5 0.000 10.000 r CLK (IN)
  601. net (fo=0) 0.000 10.000 CLK
  602. W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
  603. net (fo=1, routed) 1.862 13.250 CLK_IBUF
  604. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
  605. net (fo=243, routed) 1.508 14.849 CLK_IBUF_BUFG
  606. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  607. clock pessimism 0.298 15.147
  608. clock uncertainty -0.035 15.112
  609. SLICE_X62Y19 FDRE (Setup_fdre_C_R) -0.429 14.683 tmrCntr_reg[7]
  610. -------------------------------------------------------------------
  611. required time 14.683
  612. arrival time -9.718
  613. -------------------------------------------------------------------
  614. slack 4.965
  615. Slack (MET) : 4.994ns (required time - arrival time)
  616. Source: tmrCntr_reg[7]/C
  617. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  618. Destination: tmrCntr_reg[24]/R
  619. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  620. Path Group: sys_clk_pin
  621. Path Type: Setup (Max at Slow Process Corner)
  622. Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  623. Data Path Delay: 4.511ns (logic 0.952ns (21.102%) route 3.559ns (78.898%))
  624. Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
  625. Clock Path Skew: -0.030ns (DCD - SCD + CPR)
  626. Destination Clock Delay (DCD): 4.843ns = ( 14.843 - 10.000 )
  627. Source Clock Delay (SCD): 5.147ns
  628. Clock Pessimism Removal (CPR): 0.274ns
  629. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  630. Total System Jitter (TSJ): 0.071ns
  631. Total Input Jitter (TIJ): 0.000ns
  632. Discrete Jitter (DJ): 0.000ns
  633. Phase Error (PE): 0.000ns
  634. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  635. ------------------------------------------------------------------- -------------------
  636. (clock sys_clk_pin rise edge)
  637. 0.000 0.000 r
  638. W5 0.000 0.000 r CLK (IN)
  639. net (fo=0) 0.000 0.000 CLK
  640. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  641. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  642. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  643. net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
  644. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  645. ------------------------------------------------------------------- -------------------
  646. SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
  647. net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
  648. SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
  649. net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
  650. SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
  651. net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
  652. SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
  653. net (fo=6, routed) 0.736 8.867 eqOp2_in
  654. SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
  655. net (fo=27, routed) 0.668 9.659 tmrCntr0
  656. SLICE_X62Y24 FDRE r tmrCntr_reg[24]/R
  657. ------------------------------------------------------------------- -------------------
  658. (clock sys_clk_pin rise edge)
  659. 10.000 10.000 r
  660. W5 0.000 10.000 r CLK (IN)
  661. net (fo=0) 0.000 10.000 CLK
  662. W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
  663. net (fo=1, routed) 1.862 13.250 CLK_IBUF
  664. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
  665. net (fo=243, routed) 1.502 14.843 CLK_IBUF_BUFG
  666. SLICE_X62Y24 FDRE r tmrCntr_reg[24]/C
  667. clock pessimism 0.274 15.117
  668. clock uncertainty -0.035 15.082
  669. SLICE_X62Y24 FDRE (Setup_fdre_C_R) -0.429 14.653 tmrCntr_reg[24]
  670. -------------------------------------------------------------------
  671. required time 14.653
  672. arrival time -9.659
  673. -------------------------------------------------------------------
  674. slack 4.994
  675. Slack (MET) : 4.994ns (required time - arrival time)
  676. Source: tmrCntr_reg[7]/C
  677. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  678. Destination: tmrCntr_reg[25]/R
  679. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  680. Path Group: sys_clk_pin
  681. Path Type: Setup (Max at Slow Process Corner)
  682. Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  683. Data Path Delay: 4.511ns (logic 0.952ns (21.102%) route 3.559ns (78.898%))
  684. Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
  685. Clock Path Skew: -0.030ns (DCD - SCD + CPR)
  686. Destination Clock Delay (DCD): 4.843ns = ( 14.843 - 10.000 )
  687. Source Clock Delay (SCD): 5.147ns
  688. Clock Pessimism Removal (CPR): 0.274ns
  689. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  690. Total System Jitter (TSJ): 0.071ns
  691. Total Input Jitter (TIJ): 0.000ns
  692. Discrete Jitter (DJ): 0.000ns
  693. Phase Error (PE): 0.000ns
  694. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  695. ------------------------------------------------------------------- -------------------
  696. (clock sys_clk_pin rise edge)
  697. 0.000 0.000 r
  698. W5 0.000 0.000 r CLK (IN)
  699. net (fo=0) 0.000 0.000 CLK
  700. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  701. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  702. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  703. net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
  704. SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
  705. ------------------------------------------------------------------- -------------------
  706. SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
  707. net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
  708. SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
  709. net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
  710. SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
  711. net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
  712. SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
  713. net (fo=6, routed) 0.736 8.867 eqOp2_in
  714. SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
  715. net (fo=27, routed) 0.668 9.659 tmrCntr0
  716. SLICE_X62Y24 FDRE r tmrCntr_reg[25]/R
  717. ------------------------------------------------------------------- -------------------
  718. (clock sys_clk_pin rise edge)
  719. 10.000 10.000 r
  720. W5 0.000 10.000 r CLK (IN)
  721. net (fo=0) 0.000 10.000 CLK
  722. W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
  723. net (fo=1, routed) 1.862 13.250 CLK_IBUF
  724. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
  725. net (fo=243, routed) 1.502 14.843 CLK_IBUF_BUFG
  726. SLICE_X62Y24 FDRE r tmrCntr_reg[25]/C
  727. clock pessimism 0.274 15.117
  728. clock uncertainty -0.035 15.082
  729. SLICE_X62Y24 FDRE (Setup_fdre_C_R) -0.429 14.653 tmrCntr_reg[25]
  730. -------------------------------------------------------------------
  731. required time 14.653
  732. arrival time -9.659
  733. -------------------------------------------------------------------
  734. slack 4.994
  735. Min Delay Paths
  736. --------------------------------------------------------------------------------------
  737. Slack (MET) : 0.183ns (arrival time - required time)
  738. Source: Inst_UART_TX_CTRL/bitIndex_reg[2]/C
  739. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  740. Destination: Inst_UART_TX_CTRL/txBit_reg/D
  741. (rising edge-triggered cell FDSE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  742. Path Group: sys_clk_pin
  743. Path Type: Hold (Min at Fast Process Corner)
  744. Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  745. Data Path Delay: 0.319ns (logic 0.186ns (58.233%) route 0.133ns (41.767%))
  746. Logic Levels: 1 (LUT6=1)
  747. Clock Path Skew: 0.016ns (DCD - SCD - CPR)
  748. Destination Clock Delay (DCD): 1.962ns
  749. Source Clock Delay (SCD): 1.448ns
  750. Clock Pessimism Removal (CPR): 0.498ns
  751. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  752. ------------------------------------------------------------------- -------------------
  753. (clock sys_clk_pin rise edge)
  754. 0.000 0.000 r
  755. W5 0.000 0.000 r CLK (IN)
  756. net (fo=0) 0.000 0.000 CLK
  757. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  758. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  759. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  760. net (fo=243, routed) 0.565 1.448 Inst_UART_TX_CTRL/CLK
  761. SLICE_X9Y8 FDRE r Inst_UART_TX_CTRL/bitIndex_reg[2]/C
  762. ------------------------------------------------------------------- -------------------
  763. SLICE_X9Y8 FDRE (Prop_fdre_C_Q) 0.141 1.589 r Inst_UART_TX_CTRL/bitIndex_reg[2]/Q
  764. net (fo=3, routed) 0.133 1.723 Inst_UART_TX_CTRL/bitIndex_reg[2]
  765. SLICE_X8Y9 LUT6 (Prop_lut6_I4_O) 0.045 1.768 r Inst_UART_TX_CTRL/txBit_i_2/O
  766. net (fo=1, routed) 0.000 1.768 Inst_UART_TX_CTRL/txBit_i_2_n_0
  767. SLICE_X8Y9 FDSE r Inst_UART_TX_CTRL/txBit_reg/D
  768. ------------------------------------------------------------------- -------------------
  769. (clock sys_clk_pin rise edge)
  770. 0.000 0.000 r
  771. W5 0.000 0.000 r CLK (IN)
  772. net (fo=0) 0.000 0.000 CLK
  773. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  774. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  775. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  776. net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
  777. SLICE_X8Y9 FDSE r Inst_UART_TX_CTRL/txBit_reg/C
  778. clock pessimism -0.498 1.464
  779. SLICE_X8Y9 FDSE (Hold_fdse_C_D) 0.120 1.584 Inst_UART_TX_CTRL/txBit_reg
  780. -------------------------------------------------------------------
  781. required time -1.584
  782. arrival time 1.768
  783. -------------------------------------------------------------------
  784. slack 0.183
  785. Slack (MET) : 0.197ns (arrival time - required time)
  786. Source: uartData_reg[3]/C
  787. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  788. Destination: Inst_UART_TX_CTRL/txData_reg[4]/D
  789. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  790. Path Group: sys_clk_pin
  791. Path Type: Hold (Min at Fast Process Corner)
  792. Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  793. Data Path Delay: 0.276ns (logic 0.164ns (59.419%) route 0.112ns (40.581%))
  794. Logic Levels: 0
  795. Clock Path Skew: 0.016ns (DCD - SCD - CPR)
  796. Destination Clock Delay (DCD): 1.962ns
  797. Source Clock Delay (SCD): 1.448ns
  798. Clock Pessimism Removal (CPR): 0.498ns
  799. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  800. ------------------------------------------------------------------- -------------------
  801. (clock sys_clk_pin rise edge)
  802. 0.000 0.000 r
  803. W5 0.000 0.000 r CLK (IN)
  804. net (fo=0) 0.000 0.000 CLK
  805. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  806. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  807. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  808. net (fo=243, routed) 0.565 1.448 CLK_IBUF_BUFG
  809. SLICE_X8Y7 FDRE r uartData_reg[3]/C
  810. ------------------------------------------------------------------- -------------------
  811. SLICE_X8Y7 FDRE (Prop_fdre_C_Q) 0.164 1.612 r uartData_reg[3]/Q
  812. net (fo=1, routed) 0.112 1.724 Inst_UART_TX_CTRL/DATA[3]
  813. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[4]/D
  814. ------------------------------------------------------------------- -------------------
  815. (clock sys_clk_pin rise edge)
  816. 0.000 0.000 r
  817. W5 0.000 0.000 r CLK (IN)
  818. net (fo=0) 0.000 0.000 CLK
  819. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  820. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  821. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  822. net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
  823. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[4]/C
  824. clock pessimism -0.498 1.464
  825. SLICE_X8Y8 FDRE (Hold_fdre_C_D) 0.063 1.527 Inst_UART_TX_CTRL/txData_reg[4]
  826. -------------------------------------------------------------------
  827. required time -1.527
  828. arrival time 1.724
  829. -------------------------------------------------------------------
  830. slack 0.197
  831. Slack (MET) : 0.207ns (arrival time - required time)
  832. Source: Inst_btn_debounce/sig_out_reg_reg[1]/C
  833. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  834. Destination: btnReg_reg[1]/D
  835. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  836. Path Group: sys_clk_pin
  837. Path Type: Hold (Min at Fast Process Corner)
  838. Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  839. Data Path Delay: 0.273ns (logic 0.141ns (51.608%) route 0.132ns (48.392%))
  840. Logic Levels: 0
  841. Clock Path Skew: 0.014ns (DCD - SCD - CPR)
  842. Destination Clock Delay (DCD): 1.955ns
  843. Source Clock Delay (SCD): 1.443ns
  844. Clock Pessimism Removal (CPR): 0.498ns
  845. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  846. ------------------------------------------------------------------- -------------------
  847. (clock sys_clk_pin rise edge)
  848. 0.000 0.000 r
  849. W5 0.000 0.000 r CLK (IN)
  850. net (fo=0) 0.000 0.000 CLK
  851. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  852. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  853. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  854. net (fo=243, routed) 0.560 1.443 Inst_btn_debounce/CLK_I
  855. SLICE_X13Y17 FDRE r Inst_btn_debounce/sig_out_reg_reg[1]/C
  856. ------------------------------------------------------------------- -------------------
  857. SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 1.584 r Inst_btn_debounce/sig_out_reg_reg[1]/Q
  858. net (fo=5, routed) 0.132 1.716 btnDeBnc[1]
  859. SLICE_X14Y17 FDRE r btnReg_reg[1]/D
  860. ------------------------------------------------------------------- -------------------
  861. (clock sys_clk_pin rise edge)
  862. 0.000 0.000 r
  863. W5 0.000 0.000 r CLK (IN)
  864. net (fo=0) 0.000 0.000 CLK
  865. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  866. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  867. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  868. net (fo=243, routed) 0.828 1.955 CLK_IBUF_BUFG
  869. SLICE_X14Y17 FDRE r btnReg_reg[1]/C
  870. clock pessimism -0.498 1.457
  871. SLICE_X14Y17 FDRE (Hold_fdre_C_D) 0.052 1.509 btnReg_reg[1]
  872. -------------------------------------------------------------------
  873. required time -1.509
  874. arrival time 1.716
  875. -------------------------------------------------------------------
  876. slack 0.207
  877. Slack (MET) : 0.221ns (arrival time - required time)
  878. Source: Inst_btn_debounce/sig_out_reg_reg[3]/C
  879. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  880. Destination: Inst_btn_debounce/sig_out_reg_reg[3]/D
  881. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  882. Path Group: sys_clk_pin
  883. Path Type: Hold (Min at Fast Process Corner)
  884. Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  885. Data Path Delay: 0.312ns (logic 0.186ns (59.538%) route 0.126ns (40.462%))
  886. Logic Levels: 1 (LUT5=1)
  887. Clock Path Skew: 0.000ns (DCD - SCD - CPR)
  888. Destination Clock Delay (DCD): 1.957ns
  889. Source Clock Delay (SCD): 1.445ns
  890. Clock Pessimism Removal (CPR): 0.512ns
  891. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  892. ------------------------------------------------------------------- -------------------
  893. (clock sys_clk_pin rise edge)
  894. 0.000 0.000 r
  895. W5 0.000 0.000 r CLK (IN)
  896. net (fo=0) 0.000 0.000 CLK
  897. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  898. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  899. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  900. net (fo=243, routed) 0.562 1.445 Inst_btn_debounce/CLK_I
  901. SLICE_X11Y15 FDRE r Inst_btn_debounce/sig_out_reg_reg[3]/C
  902. ------------------------------------------------------------------- -------------------
  903. SLICE_X11Y15 FDRE (Prop_fdre_C_Q) 0.141 1.586 r Inst_btn_debounce/sig_out_reg_reg[3]/Q
  904. net (fo=5, routed) 0.126 1.713 Inst_btn_debounce/SIGNAL_O[3]
  905. SLICE_X11Y15 LUT5 (Prop_lut5_I4_O) 0.045 1.758 r Inst_btn_debounce/sig_out_reg[3]_i_1/O
  906. net (fo=1, routed) 0.000 1.758 Inst_btn_debounce/sig_out_reg[3]_i_1_n_0
  907. SLICE_X11Y15 FDRE r Inst_btn_debounce/sig_out_reg_reg[3]/D
  908. ------------------------------------------------------------------- -------------------
  909. (clock sys_clk_pin rise edge)
  910. 0.000 0.000 r
  911. W5 0.000 0.000 r CLK (IN)
  912. net (fo=0) 0.000 0.000 CLK
  913. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  914. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  915. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  916. net (fo=243, routed) 0.830 1.957 Inst_btn_debounce/CLK_I
  917. SLICE_X11Y15 FDRE r Inst_btn_debounce/sig_out_reg_reg[3]/C
  918. clock pessimism -0.512 1.445
  919. SLICE_X11Y15 FDRE (Hold_fdre_C_D) 0.091 1.536 Inst_btn_debounce/sig_out_reg_reg[3]
  920. -------------------------------------------------------------------
  921. required time -1.536
  922. arrival time 1.758
  923. -------------------------------------------------------------------
  924. slack 0.221
  925. Slack (MET) : 0.223ns (arrival time - required time)
  926. Source: uartData_reg[5]/C
  927. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  928. Destination: Inst_UART_TX_CTRL/txData_reg[6]/D
  929. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  930. Path Group: sys_clk_pin
  931. Path Type: Hold (Min at Fast Process Corner)
  932. Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  933. Data Path Delay: 0.318ns (logic 0.141ns (44.389%) route 0.177ns (55.611%))
  934. Logic Levels: 0
  935. Clock Path Skew: 0.035ns (DCD - SCD - CPR)
  936. Destination Clock Delay (DCD): 1.962ns
  937. Source Clock Delay (SCD): 1.449ns
  938. Clock Pessimism Removal (CPR): 0.478ns
  939. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  940. ------------------------------------------------------------------- -------------------
  941. (clock sys_clk_pin rise edge)
  942. 0.000 0.000 r
  943. W5 0.000 0.000 r CLK (IN)
  944. net (fo=0) 0.000 0.000 CLK
  945. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  946. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  947. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  948. net (fo=243, routed) 0.566 1.449 CLK_IBUF_BUFG
  949. SLICE_X11Y6 FDRE r uartData_reg[5]/C
  950. ------------------------------------------------------------------- -------------------
  951. SLICE_X11Y6 FDRE (Prop_fdre_C_Q) 0.141 1.590 r uartData_reg[5]/Q
  952. net (fo=1, routed) 0.177 1.767 Inst_UART_TX_CTRL/DATA[5]
  953. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[6]/D
  954. ------------------------------------------------------------------- -------------------
  955. (clock sys_clk_pin rise edge)
  956. 0.000 0.000 r
  957. W5 0.000 0.000 r CLK (IN)
  958. net (fo=0) 0.000 0.000 CLK
  959. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  960. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  961. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  962. net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
  963. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[6]/C
  964. clock pessimism -0.478 1.484
  965. SLICE_X8Y8 FDRE (Hold_fdre_C_D) 0.060 1.544 Inst_UART_TX_CTRL/txData_reg[6]
  966. -------------------------------------------------------------------
  967. required time -1.544
  968. arrival time 1.767
  969. -------------------------------------------------------------------
  970. slack 0.223
  971. Slack (MET) : 0.235ns (arrival time - required time)
  972. Source: Inst_btn_debounce/sig_out_reg_reg[4]/C
  973. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  974. Destination: uartState_reg[2]/D
  975. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  976. Path Group: sys_clk_pin
  977. Path Type: Hold (Min at Fast Process Corner)
  978. Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  979. Data Path Delay: 0.343ns (logic 0.209ns (60.852%) route 0.134ns (39.148%))
  980. Logic Levels: 1 (LUT6=1)
  981. Clock Path Skew: 0.016ns (DCD - SCD - CPR)
  982. Destination Clock Delay (DCD): 1.961ns
  983. Source Clock Delay (SCD): 1.447ns
  984. Clock Pessimism Removal (CPR): 0.498ns
  985. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  986. ------------------------------------------------------------------- -------------------
  987. (clock sys_clk_pin rise edge)
  988. 0.000 0.000 r
  989. W5 0.000 0.000 r CLK (IN)
  990. net (fo=0) 0.000 0.000 CLK
  991. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  992. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  993. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  994. net (fo=243, routed) 0.564 1.447 Inst_btn_debounce/CLK_I
  995. SLICE_X14Y11 FDRE r Inst_btn_debounce/sig_out_reg_reg[4]/C
  996. ------------------------------------------------------------------- -------------------
  997. SLICE_X14Y11 FDRE (Prop_fdre_C_Q) 0.164 1.611 f Inst_btn_debounce/sig_out_reg_reg[4]/Q
  998. net (fo=5, routed) 0.134 1.746 btnDeBnc[4]
  999. SLICE_X13Y11 LUT6 (Prop_lut6_I5_O) 0.045 1.791 r uartState[2]_i_1/O
  1000. net (fo=1, routed) 0.000 1.791 uartState[2]_i_1_n_0
  1001. SLICE_X13Y11 FDRE r uartState_reg[2]/D
  1002. ------------------------------------------------------------------- -------------------
  1003. (clock sys_clk_pin rise edge)
  1004. 0.000 0.000 r
  1005. W5 0.000 0.000 r CLK (IN)
  1006. net (fo=0) 0.000 0.000 CLK
  1007. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  1008. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  1009. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  1010. net (fo=243, routed) 0.834 1.961 CLK_IBUF_BUFG
  1011. SLICE_X13Y11 FDRE r uartState_reg[2]/C
  1012. clock pessimism -0.498 1.463
  1013. SLICE_X13Y11 FDRE (Hold_fdre_C_D) 0.092 1.555 uartState_reg[2]
  1014. -------------------------------------------------------------------
  1015. required time -1.555
  1016. arrival time 1.791
  1017. -------------------------------------------------------------------
  1018. slack 0.235
  1019. Slack (MET) : 0.244ns (arrival time - required time)
  1020. Source: uartData_reg[6]/C
  1021. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  1022. Destination: Inst_UART_TX_CTRL/txData_reg[7]/D
  1023. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  1024. Path Group: sys_clk_pin
  1025. Path Type: Hold (Min at Fast Process Corner)
  1026. Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  1027. Data Path Delay: 0.313ns (logic 0.141ns (45.028%) route 0.172ns (54.972%))
  1028. Logic Levels: 0
  1029. Clock Path Skew: 0.016ns (DCD - SCD - CPR)
  1030. Destination Clock Delay (DCD): 1.962ns
  1031. Source Clock Delay (SCD): 1.448ns
  1032. Clock Pessimism Removal (CPR): 0.498ns
  1033. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1034. ------------------------------------------------------------------- -------------------
  1035. (clock sys_clk_pin rise edge)
  1036. 0.000 0.000 r
  1037. W5 0.000 0.000 r CLK (IN)
  1038. net (fo=0) 0.000 0.000 CLK
  1039. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  1040. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  1041. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  1042. net (fo=243, routed) 0.565 1.448 CLK_IBUF_BUFG
  1043. SLICE_X9Y7 FDRE r uartData_reg[6]/C
  1044. ------------------------------------------------------------------- -------------------
  1045. SLICE_X9Y7 FDRE (Prop_fdre_C_Q) 0.141 1.589 r uartData_reg[6]/Q
  1046. net (fo=1, routed) 0.172 1.761 Inst_UART_TX_CTRL/DATA[6]
  1047. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[7]/D
  1048. ------------------------------------------------------------------- -------------------
  1049. (clock sys_clk_pin rise edge)
  1050. 0.000 0.000 r
  1051. W5 0.000 0.000 r CLK (IN)
  1052. net (fo=0) 0.000 0.000 CLK
  1053. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  1054. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  1055. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  1056. net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
  1057. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[7]/C
  1058. clock pessimism -0.498 1.464
  1059. SLICE_X8Y8 FDRE (Hold_fdre_C_D) 0.053 1.517 Inst_UART_TX_CTRL/txData_reg[7]
  1060. -------------------------------------------------------------------
  1061. required time -1.517
  1062. arrival time 1.761
  1063. -------------------------------------------------------------------
  1064. slack 0.244
  1065. Slack (MET) : 0.249ns (arrival time - required time)
  1066. Source: uartSend_reg/C
  1067. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  1068. Destination: Inst_UART_TX_CTRL/txData_reg[1]/CE
  1069. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  1070. Path Group: sys_clk_pin
  1071. Path Type: Hold (Min at Fast Process Corner)
  1072. Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  1073. Data Path Delay: 0.269ns (logic 0.141ns (52.505%) route 0.128ns (47.495%))
  1074. Logic Levels: 0
  1075. Clock Path Skew: 0.036ns (DCD - SCD - CPR)
  1076. Destination Clock Delay (DCD): 1.962ns
  1077. Source Clock Delay (SCD): 1.448ns
  1078. Clock Pessimism Removal (CPR): 0.478ns
  1079. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1080. ------------------------------------------------------------------- -------------------
  1081. (clock sys_clk_pin rise edge)
  1082. 0.000 0.000 r
  1083. W5 0.000 0.000 r CLK (IN)
  1084. net (fo=0) 0.000 0.000 CLK
  1085. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  1086. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  1087. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  1088. net (fo=243, routed) 0.565 1.448 CLK_IBUF_BUFG
  1089. SLICE_X11Y8 FDRE r uartSend_reg/C
  1090. ------------------------------------------------------------------- -------------------
  1091. SLICE_X11Y8 FDRE (Prop_fdre_C_Q) 0.141 1.589 r uartSend_reg/Q
  1092. net (fo=8, routed) 0.128 1.717 Inst_UART_TX_CTRL/SEND
  1093. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[1]/CE
  1094. ------------------------------------------------------------------- -------------------
  1095. (clock sys_clk_pin rise edge)
  1096. 0.000 0.000 r
  1097. W5 0.000 0.000 r CLK (IN)
  1098. net (fo=0) 0.000 0.000 CLK
  1099. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  1100. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  1101. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  1102. net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
  1103. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[1]/C
  1104. clock pessimism -0.478 1.484
  1105. SLICE_X8Y8 FDRE (Hold_fdre_C_CE) -0.016 1.468 Inst_UART_TX_CTRL/txData_reg[1]
  1106. -------------------------------------------------------------------
  1107. required time -1.468
  1108. arrival time 1.717
  1109. -------------------------------------------------------------------
  1110. slack 0.249
  1111. Slack (MET) : 0.249ns (arrival time - required time)
  1112. Source: uartSend_reg/C
  1113. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  1114. Destination: Inst_UART_TX_CTRL/txData_reg[3]/CE
  1115. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  1116. Path Group: sys_clk_pin
  1117. Path Type: Hold (Min at Fast Process Corner)
  1118. Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  1119. Data Path Delay: 0.269ns (logic 0.141ns (52.505%) route 0.128ns (47.495%))
  1120. Logic Levels: 0
  1121. Clock Path Skew: 0.036ns (DCD - SCD - CPR)
  1122. Destination Clock Delay (DCD): 1.962ns
  1123. Source Clock Delay (SCD): 1.448ns
  1124. Clock Pessimism Removal (CPR): 0.478ns
  1125. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1126. ------------------------------------------------------------------- -------------------
  1127. (clock sys_clk_pin rise edge)
  1128. 0.000 0.000 r
  1129. W5 0.000 0.000 r CLK (IN)
  1130. net (fo=0) 0.000 0.000 CLK
  1131. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  1132. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  1133. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  1134. net (fo=243, routed) 0.565 1.448 CLK_IBUF_BUFG
  1135. SLICE_X11Y8 FDRE r uartSend_reg/C
  1136. ------------------------------------------------------------------- -------------------
  1137. SLICE_X11Y8 FDRE (Prop_fdre_C_Q) 0.141 1.589 r uartSend_reg/Q
  1138. net (fo=8, routed) 0.128 1.717 Inst_UART_TX_CTRL/SEND
  1139. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[3]/CE
  1140. ------------------------------------------------------------------- -------------------
  1141. (clock sys_clk_pin rise edge)
  1142. 0.000 0.000 r
  1143. W5 0.000 0.000 r CLK (IN)
  1144. net (fo=0) 0.000 0.000 CLK
  1145. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  1146. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  1147. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  1148. net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
  1149. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[3]/C
  1150. clock pessimism -0.478 1.484
  1151. SLICE_X8Y8 FDRE (Hold_fdre_C_CE) -0.016 1.468 Inst_UART_TX_CTRL/txData_reg[3]
  1152. -------------------------------------------------------------------
  1153. required time -1.468
  1154. arrival time 1.717
  1155. -------------------------------------------------------------------
  1156. slack 0.249
  1157. Slack (MET) : 0.249ns (arrival time - required time)
  1158. Source: uartSend_reg/C
  1159. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  1160. Destination: Inst_UART_TX_CTRL/txData_reg[4]/CE
  1161. (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
  1162. Path Group: sys_clk_pin
  1163. Path Type: Hold (Min at Fast Process Corner)
  1164. Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  1165. Data Path Delay: 0.269ns (logic 0.141ns (52.505%) route 0.128ns (47.495%))
  1166. Logic Levels: 0
  1167. Clock Path Skew: 0.036ns (DCD - SCD - CPR)
  1168. Destination Clock Delay (DCD): 1.962ns
  1169. Source Clock Delay (SCD): 1.448ns
  1170. Clock Pessimism Removal (CPR): 0.478ns
  1171. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1172. ------------------------------------------------------------------- -------------------
  1173. (clock sys_clk_pin rise edge)
  1174. 0.000 0.000 r
  1175. W5 0.000 0.000 r CLK (IN)
  1176. net (fo=0) 0.000 0.000 CLK
  1177. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  1178. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  1179. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  1180. net (fo=243, routed) 0.565 1.448 CLK_IBUF_BUFG
  1181. SLICE_X11Y8 FDRE r uartSend_reg/C
  1182. ------------------------------------------------------------------- -------------------
  1183. SLICE_X11Y8 FDRE (Prop_fdre_C_Q) 0.141 1.589 r uartSend_reg/Q
  1184. net (fo=8, routed) 0.128 1.717 Inst_UART_TX_CTRL/SEND
  1185. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[4]/CE
  1186. ------------------------------------------------------------------- -------------------
  1187. (clock sys_clk_pin rise edge)
  1188. 0.000 0.000 r
  1189. W5 0.000 0.000 r CLK (IN)
  1190. net (fo=0) 0.000 0.000 CLK
  1191. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  1192. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  1193. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  1194. net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
  1195. SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[4]/C
  1196. clock pessimism -0.478 1.484
  1197. SLICE_X8Y8 FDRE (Hold_fdre_C_CE) -0.016 1.468 Inst_UART_TX_CTRL/txData_reg[4]
  1198. -------------------------------------------------------------------
  1199. required time -1.468
  1200. arrival time 1.717
  1201. -------------------------------------------------------------------
  1202. slack 0.249
  1203. Pulse Width Checks
  1204. --------------------------------------------------------------------------------------
  1205. Clock Name: sys_clk_pin
  1206. Waveform(ns): { 0.000 5.000 }
  1207. Period(ns): 10.000
  1208. Sources: { CLK }
  1209. Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
  1210. Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y1 CLK_IBUF_BUFG_inst/I
  1211. Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
  1212. Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y8 Inst_UART_TX_CTRL/bitIndex_reg[0]/C
  1213. Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y10 Inst_UART_TX_CTRL/bitIndex_reg[10]/C
  1214. Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y10 Inst_UART_TX_CTRL/bitIndex_reg[11]/C
  1215. Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[12]/C
  1216. Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[13]/C
  1217. Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[14]/C
  1218. Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[15]/C
  1219. Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y12 Inst_UART_TX_CTRL/bitIndex_reg[16]/C
  1220. Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
  1221. Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
  1222. Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
  1223. Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[12]/C
  1224. Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[13]/C
  1225. Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[14]/C
  1226. Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[15]/C
  1227. Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y12 Inst_UART_TX_CTRL/bitIndex_reg[16]/C
  1228. Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y14 Inst_btn_debounce/sig_cntrs_ary_reg[2][0]/C
  1229. Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y14 Inst_btn_debounce/sig_cntrs_ary_reg[2][1]/C
  1230. Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y14 Inst_btn_debounce/sig_cntrs_ary_reg[2][2]/C
  1231. High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
  1232. High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
  1233. High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y8 Inst_UART_TX_CTRL/bitIndex_reg[0]/C
  1234. High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y8 Inst_UART_TX_CTRL/txData_reg[1]/C
  1235. High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y8 Inst_UART_TX_CTRL/txData_reg[3]/C
  1236. High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y8 Inst_UART_TX_CTRL/txData_reg[4]/C
  1237. High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y8 Inst_UART_TX_CTRL/txData_reg[5]/C
  1238. High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y8 Inst_UART_TX_CTRL/txData_reg[6]/C
  1239. High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y16 Inst_btn_debounce/sig_cntrs_ary_reg[2][10]/C
  1240. High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y16 Inst_btn_debounce/sig_cntrs_ary_reg[2][11]/C
  1241. ---------------------------------------------------------------------------------------------------
  1242. From Clock: clk_out1_clk_wiz_0
  1243. To Clock: clk_out1_clk_wiz_0
  1244. Setup : 0 Failing Endpoints, Worst Slack 3.744ns, Total Violation 0.000ns
  1245. Hold : 0 Failing Endpoints, Worst Slack 0.064ns, Total Violation 0.000ns
  1246. PW : 0 Failing Endpoints, Worst Slack 4.130ns, Total Violation 0.000ns
  1247. ---------------------------------------------------------------------------------------------------
  1248. Max Delay Paths
  1249. --------------------------------------------------------------------------------------
  1250. Slack (MET) : 3.744ns (required time - arrival time)
  1251. Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1252. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1253. Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]/D
  1254. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1255. Path Group: clk_out1_clk_wiz_0
  1256. Path Type: Setup (Max at Slow Process Corner)
  1257. Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
  1258. Data Path Delay: 5.474ns (logic 2.609ns (47.666%) route 2.865ns (52.334%))
  1259. Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
  1260. Clock Path Skew: 0.000ns (DCD - SCD + CPR)
  1261. Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
  1262. Source Clock Delay (SCD): 5.156ns
  1263. Clock Pessimism Removal (CPR): 0.298ns
  1264. Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  1265. Total System Jitter (TSJ): 0.071ns
  1266. Discrete Jitter (DJ): 0.126ns
  1267. Phase Error (PE): 0.000ns
  1268. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1269. ------------------------------------------------------------------- -------------------
  1270. (clock clk_out1_clk_wiz_0 rise edge)
  1271. 0.000 0.000 r
  1272. W5 0.000 0.000 r CLK (IN)
  1273. net (fo=0) 0.000 0.000 CLK
  1274. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  1275. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  1276. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  1277. net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1278. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1279. -3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1280. net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1281. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1282. net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
  1283. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1284. ------------------------------------------------------------------- -------------------
  1285. SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
  1286. net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
  1287. SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
  1288. net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
  1289. SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
  1290. 0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
  1291. net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
  1292. SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
  1293. 0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
  1294. net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
  1295. SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
  1296. 0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
  1297. net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
  1298. SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
  1299. net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
  1300. SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
  1301. 0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
  1302. net (fo=12, routed) 1.047 10.298 Inst_vga_ctrl/Inst_MouseCtl/gtOp
  1303. SLICE_X5Y43 LUT5 (Prop_lut5_I3_O) 0.332 10.630 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[2]_i_1/O
  1304. net (fo=1, routed) 0.000 10.630 Inst_vga_ctrl/Inst_MouseCtl/x_pos[2]_i_1_n_0
  1305. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]/D
  1306. ------------------------------------------------------------------- -------------------
  1307. (clock clk_out1_clk_wiz_0 rise edge)
  1308. 9.259 9.259 r
  1309. W5 0.000 9.259 r CLK (IN)
  1310. net (fo=0) 0.000 9.259 CLK
  1311. W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
  1312. net (fo=1, routed) 1.862 12.509 CLK_IBUF
  1313. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
  1314. net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1315. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1316. -3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1317. net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1318. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1319. net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
  1320. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]/C
  1321. clock pessimism 0.298 14.416
  1322. clock uncertainty -0.072 14.343
  1323. SLICE_X5Y43 FDRE (Setup_fdre_C_D) 0.031 14.374 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]
  1324. -------------------------------------------------------------------
  1325. required time 14.374
  1326. arrival time -10.630
  1327. -------------------------------------------------------------------
  1328. slack 3.744
  1329. Slack (MET) : 3.938ns (required time - arrival time)
  1330. Source: Inst_vga_ctrl/MOUSE_X_POS_REG_reg[5]/C
  1331. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1332. Destination: Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg/D
  1333. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1334. Path Group: clk_out1_clk_wiz_0
  1335. Path Type: Setup (Max at Slow Process Corner)
  1336. Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
  1337. Data Path Delay: 5.252ns (logic 2.569ns (48.913%) route 2.683ns (51.087%))
  1338. Logic Levels: 5 (CARRY4=3 LUT4=1 LUT5=1)
  1339. Clock Path Skew: -0.026ns (DCD - SCD + CPR)
  1340. Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
  1341. Source Clock Delay (SCD): 5.158ns
  1342. Clock Pessimism Removal (CPR): 0.274ns
  1343. Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  1344. Total System Jitter (TSJ): 0.071ns
  1345. Discrete Jitter (DJ): 0.126ns
  1346. Phase Error (PE): 0.000ns
  1347. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1348. ------------------------------------------------------------------- -------------------
  1349. (clock clk_out1_clk_wiz_0 rise edge)
  1350. 0.000 0.000 r
  1351. W5 0.000 0.000 r CLK (IN)
  1352. net (fo=0) 0.000 0.000 CLK
  1353. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  1354. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  1355. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  1356. net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1357. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1358. -3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1359. net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1360. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1361. net (fo=336, routed) 1.637 5.158 Inst_vga_ctrl/pxl_clk
  1362. SLICE_X1Y42 FDRE r Inst_vga_ctrl/MOUSE_X_POS_REG_reg[5]/C
  1363. ------------------------------------------------------------------- -------------------
  1364. SLICE_X1Y42 FDRE (Prop_fdre_C_Q) 0.456 5.614 r Inst_vga_ctrl/MOUSE_X_POS_REG_reg[5]/Q
  1365. net (fo=2, routed) 0.875 6.489 Inst_vga_ctrl/Inst_MouseDisplay/xpos[5]
  1366. SLICE_X4Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
  1367. 0.656 7.145 r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_35/CO[3]
  1368. net (fo=1, routed) 0.000 7.145 Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_35_n_0
  1369. SLICE_X4Y45 CARRY4 (Prop_carry4_CI_O[1])
  1370. 0.334 7.479 r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_34/O[1]
  1371. net (fo=2, routed) 0.872 8.351 Inst_vga_ctrl/Inst_MouseDisplay/plusOp26[10]
  1372. SLICE_X7Y45 LUT4 (Prop_lut4_I1_O) 0.303 8.654 r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_9/O
  1373. net (fo=1, routed) 0.000 8.654 Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_9_n_0
  1374. SLICE_X7Y45 CARRY4 (Prop_carry4_S[1]_CO[1])
  1375. 0.491 9.145 r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_2/CO[1]
  1376. net (fo=1, routed) 0.936 10.081 Inst_vga_ctrl/Inst_MouseDisplay/geqOp
  1377. SLICE_X3Y39 LUT5 (Prop_lut5_I0_O) 0.329 10.410 r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_1/O
  1378. net (fo=1, routed) 0.000 10.410 Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_1_n_0
  1379. SLICE_X3Y39 FDRE r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg/D
  1380. ------------------------------------------------------------------- -------------------
  1381. (clock clk_out1_clk_wiz_0 rise edge)
  1382. 9.259 9.259 r
  1383. W5 0.000 9.259 r CLK (IN)
  1384. net (fo=0) 0.000 9.259 CLK
  1385. W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
  1386. net (fo=1, routed) 1.862 12.509 CLK_IBUF
  1387. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
  1388. net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1389. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1390. -3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1391. net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1392. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1393. net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseDisplay/pixel_clk
  1394. SLICE_X3Y39 FDRE r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg/C
  1395. clock pessimism 0.274 14.392
  1396. clock uncertainty -0.072 14.319
  1397. SLICE_X3Y39 FDRE (Setup_fdre_C_D) 0.029 14.348 Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg
  1398. -------------------------------------------------------------------
  1399. required time 14.348
  1400. arrival time -10.410
  1401. -------------------------------------------------------------------
  1402. slack 3.938
  1403. Slack (MET) : 4.066ns (required time - arrival time)
  1404. Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1405. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1406. Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/D
  1407. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1408. Path Group: clk_out1_clk_wiz_0
  1409. Path Type: Setup (Max at Slow Process Corner)
  1410. Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
  1411. Data Path Delay: 5.150ns (logic 2.609ns (50.660%) route 2.541ns (49.340%))
  1412. Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
  1413. Clock Path Skew: 0.000ns (DCD - SCD + CPR)
  1414. Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
  1415. Source Clock Delay (SCD): 5.156ns
  1416. Clock Pessimism Removal (CPR): 0.298ns
  1417. Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  1418. Total System Jitter (TSJ): 0.071ns
  1419. Discrete Jitter (DJ): 0.126ns
  1420. Phase Error (PE): 0.000ns
  1421. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1422. ------------------------------------------------------------------- -------------------
  1423. (clock clk_out1_clk_wiz_0 rise edge)
  1424. 0.000 0.000 r
  1425. W5 0.000 0.000 r CLK (IN)
  1426. net (fo=0) 0.000 0.000 CLK
  1427. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  1428. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  1429. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  1430. net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1431. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1432. -3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1433. net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1434. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1435. net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
  1436. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1437. ------------------------------------------------------------------- -------------------
  1438. SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
  1439. net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
  1440. SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
  1441. net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
  1442. SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
  1443. 0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
  1444. net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
  1445. SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
  1446. 0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
  1447. net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
  1448. SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
  1449. 0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
  1450. net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
  1451. SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
  1452. net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
  1453. SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
  1454. 0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
  1455. net (fo=12, routed) 0.723 9.974 Inst_vga_ctrl/Inst_MouseCtl/gtOp
  1456. SLICE_X5Y43 LUT5 (Prop_lut5_I3_O) 0.332 10.306 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]_i_1/O
  1457. net (fo=1, routed) 0.000 10.306 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]_i_1_n_0
  1458. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/D
  1459. ------------------------------------------------------------------- -------------------
  1460. (clock clk_out1_clk_wiz_0 rise edge)
  1461. 9.259 9.259 r
  1462. W5 0.000 9.259 r CLK (IN)
  1463. net (fo=0) 0.000 9.259 CLK
  1464. W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
  1465. net (fo=1, routed) 1.862 12.509 CLK_IBUF
  1466. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
  1467. net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1468. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1469. -3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1470. net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1471. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1472. net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
  1473. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1474. clock pessimism 0.298 14.416
  1475. clock uncertainty -0.072 14.343
  1476. SLICE_X5Y43 FDRE (Setup_fdre_C_D) 0.029 14.372 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]
  1477. -------------------------------------------------------------------
  1478. required time 14.372
  1479. arrival time -10.306
  1480. -------------------------------------------------------------------
  1481. slack 4.066
  1482. Slack (MET) : 4.148ns (required time - arrival time)
  1483. Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1484. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1485. Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]/D
  1486. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1487. Path Group: clk_out1_clk_wiz_0
  1488. Path Type: Setup (Max at Slow Process Corner)
  1489. Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
  1490. Data Path Delay: 5.070ns (logic 2.609ns (51.464%) route 2.461ns (48.536%))
  1491. Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
  1492. Clock Path Skew: 0.000ns (DCD - SCD + CPR)
  1493. Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
  1494. Source Clock Delay (SCD): 5.156ns
  1495. Clock Pessimism Removal (CPR): 0.298ns
  1496. Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  1497. Total System Jitter (TSJ): 0.071ns
  1498. Discrete Jitter (DJ): 0.126ns
  1499. Phase Error (PE): 0.000ns
  1500. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1501. ------------------------------------------------------------------- -------------------
  1502. (clock clk_out1_clk_wiz_0 rise edge)
  1503. 0.000 0.000 r
  1504. W5 0.000 0.000 r CLK (IN)
  1505. net (fo=0) 0.000 0.000 CLK
  1506. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  1507. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  1508. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  1509. net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1510. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1511. -3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1512. net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1513. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1514. net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
  1515. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1516. ------------------------------------------------------------------- -------------------
  1517. SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
  1518. net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
  1519. SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
  1520. net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
  1521. SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
  1522. 0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
  1523. net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
  1524. SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
  1525. 0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
  1526. net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
  1527. SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
  1528. 0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
  1529. net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
  1530. SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
  1531. net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
  1532. SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
  1533. 0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
  1534. net (fo=12, routed) 0.643 9.894 Inst_vga_ctrl/Inst_MouseCtl/gtOp
  1535. SLICE_X5Y43 LUT5 (Prop_lut5_I3_O) 0.332 10.226 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_1/O
  1536. net (fo=1, routed) 0.000 10.226 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_1_n_0
  1537. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]/D
  1538. ------------------------------------------------------------------- -------------------
  1539. (clock clk_out1_clk_wiz_0 rise edge)
  1540. 9.259 9.259 r
  1541. W5 0.000 9.259 r CLK (IN)
  1542. net (fo=0) 0.000 9.259 CLK
  1543. W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
  1544. net (fo=1, routed) 1.862 12.509 CLK_IBUF
  1545. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
  1546. net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1547. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1548. -3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1549. net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1550. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1551. net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
  1552. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]/C
  1553. clock pessimism 0.298 14.416
  1554. clock uncertainty -0.072 14.343
  1555. SLICE_X5Y43 FDRE (Setup_fdre_C_D) 0.031 14.374 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]
  1556. -------------------------------------------------------------------
  1557. required time 14.374
  1558. arrival time -10.226
  1559. -------------------------------------------------------------------
  1560. slack 4.148
  1561. Slack (MET) : 4.150ns (required time - arrival time)
  1562. Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1563. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1564. Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]/D
  1565. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1566. Path Group: clk_out1_clk_wiz_0
  1567. Path Type: Setup (Max at Slow Process Corner)
  1568. Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
  1569. Data Path Delay: 5.069ns (logic 2.609ns (51.474%) route 2.460ns (48.526%))
  1570. Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
  1571. Clock Path Skew: 0.000ns (DCD - SCD + CPR)
  1572. Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
  1573. Source Clock Delay (SCD): 5.156ns
  1574. Clock Pessimism Removal (CPR): 0.298ns
  1575. Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  1576. Total System Jitter (TSJ): 0.071ns
  1577. Discrete Jitter (DJ): 0.126ns
  1578. Phase Error (PE): 0.000ns
  1579. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1580. ------------------------------------------------------------------- -------------------
  1581. (clock clk_out1_clk_wiz_0 rise edge)
  1582. 0.000 0.000 r
  1583. W5 0.000 0.000 r CLK (IN)
  1584. net (fo=0) 0.000 0.000 CLK
  1585. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  1586. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  1587. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  1588. net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1589. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1590. -3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1591. net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1592. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1593. net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
  1594. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1595. ------------------------------------------------------------------- -------------------
  1596. SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
  1597. net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
  1598. SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
  1599. net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
  1600. SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
  1601. 0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
  1602. net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
  1603. SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
  1604. 0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
  1605. net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
  1606. SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
  1607. 0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
  1608. net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
  1609. SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
  1610. net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
  1611. SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
  1612. 0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
  1613. net (fo=12, routed) 0.642 9.893 Inst_vga_ctrl/Inst_MouseCtl/gtOp
  1614. SLICE_X5Y43 LUT5 (Prop_lut5_I3_O) 0.332 10.225 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[4]_i_1/O
  1615. net (fo=1, routed) 0.000 10.225 Inst_vga_ctrl/Inst_MouseCtl/x_pos[4]_i_1_n_0
  1616. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]/D
  1617. ------------------------------------------------------------------- -------------------
  1618. (clock clk_out1_clk_wiz_0 rise edge)
  1619. 9.259 9.259 r
  1620. W5 0.000 9.259 r CLK (IN)
  1621. net (fo=0) 0.000 9.259 CLK
  1622. W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
  1623. net (fo=1, routed) 1.862 12.509 CLK_IBUF
  1624. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
  1625. net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1626. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1627. -3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1628. net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1629. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1630. net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
  1631. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]/C
  1632. clock pessimism 0.298 14.416
  1633. clock uncertainty -0.072 14.343
  1634. SLICE_X5Y43 FDRE (Setup_fdre_C_D) 0.032 14.375 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]
  1635. -------------------------------------------------------------------
  1636. required time 14.375
  1637. arrival time -10.225
  1638. -------------------------------------------------------------------
  1639. slack 4.150
  1640. Slack (MET) : 4.278ns (required time - arrival time)
  1641. Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1642. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1643. Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]/D
  1644. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1645. Path Group: clk_out1_clk_wiz_0
  1646. Path Type: Setup (Max at Slow Process Corner)
  1647. Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
  1648. Data Path Delay: 4.902ns (logic 2.609ns (53.218%) route 2.293ns (46.782%))
  1649. Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
  1650. Clock Path Skew: -0.036ns (DCD - SCD + CPR)
  1651. Destination Clock Delay (DCD): 4.860ns = ( 14.120 - 9.259 )
  1652. Source Clock Delay (SCD): 5.156ns
  1653. Clock Pessimism Removal (CPR): 0.260ns
  1654. Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  1655. Total System Jitter (TSJ): 0.071ns
  1656. Discrete Jitter (DJ): 0.126ns
  1657. Phase Error (PE): 0.000ns
  1658. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1659. ------------------------------------------------------------------- -------------------
  1660. (clock clk_out1_clk_wiz_0 rise edge)
  1661. 0.000 0.000 r
  1662. W5 0.000 0.000 r CLK (IN)
  1663. net (fo=0) 0.000 0.000 CLK
  1664. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  1665. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  1666. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  1667. net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1668. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1669. -3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1670. net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1671. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1672. net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
  1673. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1674. ------------------------------------------------------------------- -------------------
  1675. SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
  1676. net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
  1677. SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
  1678. net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
  1679. SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
  1680. 0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
  1681. net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
  1682. SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
  1683. 0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
  1684. net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
  1685. SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
  1686. 0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
  1687. net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
  1688. SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
  1689. net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
  1690. SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
  1691. 0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
  1692. net (fo=12, routed) 0.476 9.727 Inst_vga_ctrl/Inst_MouseCtl/gtOp
  1693. SLICE_X1Y44 LUT5 (Prop_lut5_I3_O) 0.332 10.059 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[0]_i_1/O
  1694. net (fo=1, routed) 0.000 10.059 Inst_vga_ctrl/Inst_MouseCtl/x_pos[0]_i_1_n_0
  1695. SLICE_X1Y44 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]/D
  1696. ------------------------------------------------------------------- -------------------
  1697. (clock clk_out1_clk_wiz_0 rise edge)
  1698. 9.259 9.259 r
  1699. W5 0.000 9.259 r CLK (IN)
  1700. net (fo=0) 0.000 9.259 CLK
  1701. W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
  1702. net (fo=1, routed) 1.862 12.509 CLK_IBUF
  1703. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
  1704. net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1705. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1706. -3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1707. net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1708. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1709. net (fo=336, routed) 1.519 14.120 Inst_vga_ctrl/Inst_MouseCtl/clk
  1710. SLICE_X1Y44 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]/C
  1711. clock pessimism 0.260 14.380
  1712. clock uncertainty -0.072 14.307
  1713. SLICE_X1Y44 FDRE (Setup_fdre_C_D) 0.029 14.336 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]
  1714. -------------------------------------------------------------------
  1715. required time 14.336
  1716. arrival time -10.059
  1717. -------------------------------------------------------------------
  1718. slack 4.278
  1719. Slack (MET) : 4.294ns (required time - arrival time)
  1720. Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1721. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1722. Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]/D
  1723. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1724. Path Group: clk_out1_clk_wiz_0
  1725. Path Type: Setup (Max at Slow Process Corner)
  1726. Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
  1727. Data Path Delay: 4.888ns (logic 2.609ns (53.372%) route 2.279ns (46.628%))
  1728. Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
  1729. Clock Path Skew: -0.036ns (DCD - SCD + CPR)
  1730. Destination Clock Delay (DCD): 4.860ns = ( 14.120 - 9.259 )
  1731. Source Clock Delay (SCD): 5.156ns
  1732. Clock Pessimism Removal (CPR): 0.260ns
  1733. Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  1734. Total System Jitter (TSJ): 0.071ns
  1735. Discrete Jitter (DJ): 0.126ns
  1736. Phase Error (PE): 0.000ns
  1737. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1738. ------------------------------------------------------------------- -------------------
  1739. (clock clk_out1_clk_wiz_0 rise edge)
  1740. 0.000 0.000 r
  1741. W5 0.000 0.000 r CLK (IN)
  1742. net (fo=0) 0.000 0.000 CLK
  1743. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  1744. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  1745. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  1746. net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1747. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1748. -3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1749. net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1750. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1751. net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
  1752. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1753. ------------------------------------------------------------------- -------------------
  1754. SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
  1755. net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
  1756. SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
  1757. net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
  1758. SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
  1759. 0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
  1760. net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
  1761. SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
  1762. 0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
  1763. net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
  1764. SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
  1765. 0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
  1766. net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
  1767. SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
  1768. net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
  1769. SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
  1770. 0.492 9.251 f Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
  1771. net (fo=12, routed) 0.462 9.713 Inst_vga_ctrl/Inst_MouseCtl/gtOp
  1772. SLICE_X3Y46 LUT5 (Prop_lut5_I4_O) 0.332 10.045 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[9]_i_1/O
  1773. net (fo=1, routed) 0.000 10.045 Inst_vga_ctrl/Inst_MouseCtl/x_pos[9]_i_1_n_0
  1774. SLICE_X3Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]/D
  1775. ------------------------------------------------------------------- -------------------
  1776. (clock clk_out1_clk_wiz_0 rise edge)
  1777. 9.259 9.259 r
  1778. W5 0.000 9.259 r CLK (IN)
  1779. net (fo=0) 0.000 9.259 CLK
  1780. W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
  1781. net (fo=1, routed) 1.862 12.509 CLK_IBUF
  1782. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
  1783. net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1784. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1785. -3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1786. net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1787. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1788. net (fo=336, routed) 1.519 14.120 Inst_vga_ctrl/Inst_MouseCtl/clk
  1789. SLICE_X3Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]/C
  1790. clock pessimism 0.260 14.380
  1791. clock uncertainty -0.072 14.307
  1792. SLICE_X3Y46 FDRE (Setup_fdre_C_D) 0.031 14.338 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]
  1793. -------------------------------------------------------------------
  1794. required time 14.338
  1795. arrival time -10.045
  1796. -------------------------------------------------------------------
  1797. slack 4.294
  1798. Slack (MET) : 4.296ns (required time - arrival time)
  1799. Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1800. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1801. Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]/D
  1802. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1803. Path Group: clk_out1_clk_wiz_0
  1804. Path Type: Setup (Max at Slow Process Corner)
  1805. Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
  1806. Data Path Delay: 4.884ns (logic 2.609ns (53.416%) route 2.275ns (46.584%))
  1807. Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
  1808. Clock Path Skew: -0.036ns (DCD - SCD + CPR)
  1809. Destination Clock Delay (DCD): 4.860ns = ( 14.120 - 9.259 )
  1810. Source Clock Delay (SCD): 5.156ns
  1811. Clock Pessimism Removal (CPR): 0.260ns
  1812. Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  1813. Total System Jitter (TSJ): 0.071ns
  1814. Discrete Jitter (DJ): 0.126ns
  1815. Phase Error (PE): 0.000ns
  1816. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1817. ------------------------------------------------------------------- -------------------
  1818. (clock clk_out1_clk_wiz_0 rise edge)
  1819. 0.000 0.000 r
  1820. W5 0.000 0.000 r CLK (IN)
  1821. net (fo=0) 0.000 0.000 CLK
  1822. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  1823. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  1824. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  1825. net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1826. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1827. -3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1828. net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1829. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1830. net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
  1831. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1832. ------------------------------------------------------------------- -------------------
  1833. SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
  1834. net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
  1835. SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
  1836. net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
  1837. SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
  1838. 0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
  1839. net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
  1840. SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
  1841. 0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
  1842. net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
  1843. SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
  1844. 0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
  1845. net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
  1846. SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
  1847. net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
  1848. SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
  1849. 0.492 9.251 f Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
  1850. net (fo=12, routed) 0.458 9.709 Inst_vga_ctrl/Inst_MouseCtl/gtOp
  1851. SLICE_X3Y46 LUT5 (Prop_lut5_I4_O) 0.332 10.041 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[8]_i_1/O
  1852. net (fo=1, routed) 0.000 10.041 Inst_vga_ctrl/Inst_MouseCtl/x_pos[8]_i_1_n_0
  1853. SLICE_X3Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]/D
  1854. ------------------------------------------------------------------- -------------------
  1855. (clock clk_out1_clk_wiz_0 rise edge)
  1856. 9.259 9.259 r
  1857. W5 0.000 9.259 r CLK (IN)
  1858. net (fo=0) 0.000 9.259 CLK
  1859. W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
  1860. net (fo=1, routed) 1.862 12.509 CLK_IBUF
  1861. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
  1862. net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1863. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1864. -3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1865. net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1866. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1867. net (fo=336, routed) 1.519 14.120 Inst_vga_ctrl/Inst_MouseCtl/clk
  1868. SLICE_X3Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]/C
  1869. clock pessimism 0.260 14.380
  1870. clock uncertainty -0.072 14.307
  1871. SLICE_X3Y46 FDRE (Setup_fdre_C_D) 0.029 14.336 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]
  1872. -------------------------------------------------------------------
  1873. required time 14.336
  1874. arrival time -10.041
  1875. -------------------------------------------------------------------
  1876. slack 4.296
  1877. Slack (MET) : 4.393ns (required time - arrival time)
  1878. Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1879. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1880. Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/D
  1881. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1882. Path Group: clk_out1_clk_wiz_0
  1883. Path Type: Setup (Max at Slow Process Corner)
  1884. Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
  1885. Data Path Delay: 4.798ns (logic 2.609ns (54.374%) route 2.189ns (45.626%))
  1886. Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
  1887. Clock Path Skew: -0.025ns (DCD - SCD + CPR)
  1888. Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
  1889. Source Clock Delay (SCD): 5.156ns
  1890. Clock Pessimism Removal (CPR): 0.273ns
  1891. Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  1892. Total System Jitter (TSJ): 0.071ns
  1893. Discrete Jitter (DJ): 0.126ns
  1894. Phase Error (PE): 0.000ns
  1895. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1896. ------------------------------------------------------------------- -------------------
  1897. (clock clk_out1_clk_wiz_0 rise edge)
  1898. 0.000 0.000 r
  1899. W5 0.000 0.000 r CLK (IN)
  1900. net (fo=0) 0.000 0.000 CLK
  1901. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  1902. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  1903. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  1904. net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1905. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1906. -3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1907. net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1908. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1909. net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
  1910. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1911. ------------------------------------------------------------------- -------------------
  1912. SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
  1913. net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
  1914. SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
  1915. net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
  1916. SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
  1917. 0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
  1918. net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
  1919. SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
  1920. 0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
  1921. net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
  1922. SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
  1923. 0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
  1924. net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
  1925. SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
  1926. net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
  1927. SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
  1928. 0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
  1929. net (fo=12, routed) 0.371 9.623 Inst_vga_ctrl/Inst_MouseCtl/gtOp
  1930. SLICE_X4Y46 LUT5 (Prop_lut5_I3_O) 0.332 9.955 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[10]_i_1/O
  1931. net (fo=1, routed) 0.000 9.955 Inst_vga_ctrl/Inst_MouseCtl/x_pos[10]_i_1_n_0
  1932. SLICE_X4Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/D
  1933. ------------------------------------------------------------------- -------------------
  1934. (clock clk_out1_clk_wiz_0 rise edge)
  1935. 9.259 9.259 r
  1936. W5 0.000 9.259 r CLK (IN)
  1937. net (fo=0) 0.000 9.259 CLK
  1938. W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
  1939. net (fo=1, routed) 1.862 12.509 CLK_IBUF
  1940. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
  1941. net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1942. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1943. -3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1944. net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1945. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1946. net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
  1947. SLICE_X4Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/C
  1948. clock pessimism 0.273 14.391
  1949. clock uncertainty -0.072 14.318
  1950. SLICE_X4Y46 FDRE (Setup_fdre_C_D) 0.029 14.347 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]
  1951. -------------------------------------------------------------------
  1952. required time 14.347
  1953. arrival time -9.955
  1954. -------------------------------------------------------------------
  1955. slack 4.393
  1956. Slack (MET) : 4.396ns (required time - arrival time)
  1957. Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1958. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1959. Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]/D
  1960. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  1961. Path Group: clk_out1_clk_wiz_0
  1962. Path Type: Setup (Max at Slow Process Corner)
  1963. Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
  1964. Data Path Delay: 4.798ns (logic 2.609ns (54.374%) route 2.189ns (45.626%))
  1965. Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
  1966. Clock Path Skew: -0.025ns (DCD - SCD + CPR)
  1967. Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
  1968. Source Clock Delay (SCD): 5.156ns
  1969. Clock Pessimism Removal (CPR): 0.273ns
  1970. Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  1971. Total System Jitter (TSJ): 0.071ns
  1972. Discrete Jitter (DJ): 0.126ns
  1973. Phase Error (PE): 0.000ns
  1974. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  1975. ------------------------------------------------------------------- -------------------
  1976. (clock clk_out1_clk_wiz_0 rise edge)
  1977. 0.000 0.000 r
  1978. W5 0.000 0.000 r CLK (IN)
  1979. net (fo=0) 0.000 0.000 CLK
  1980. W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
  1981. net (fo=1, routed) 1.967 3.425 CLK_IBUF
  1982. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
  1983. net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  1984. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  1985. -3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  1986. net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  1987. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  1988. net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
  1989. SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
  1990. ------------------------------------------------------------------- -------------------
  1991. SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
  1992. net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
  1993. SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
  1994. net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
  1995. SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
  1996. 0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
  1997. net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
  1998. SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
  1999. 0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
  2000. net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
  2001. SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
  2002. 0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
  2003. net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
  2004. SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
  2005. net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
  2006. SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
  2007. 0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
  2008. net (fo=12, routed) 0.371 9.623 Inst_vga_ctrl/Inst_MouseCtl/gtOp
  2009. SLICE_X4Y46 LUT5 (Prop_lut5_I3_O) 0.332 9.955 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[7]_i_1/O
  2010. net (fo=1, routed) 0.000 9.955 Inst_vga_ctrl/Inst_MouseCtl/x_pos[7]_i_1_n_0
  2011. SLICE_X4Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]/D
  2012. ------------------------------------------------------------------- -------------------
  2013. (clock clk_out1_clk_wiz_0 rise edge)
  2014. 9.259 9.259 r
  2015. W5 0.000 9.259 r CLK (IN)
  2016. net (fo=0) 0.000 9.259 CLK
  2017. W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
  2018. net (fo=1, routed) 1.862 12.509 CLK_IBUF
  2019. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
  2020. net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2021. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2022. -3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2023. net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2024. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2025. net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
  2026. SLICE_X4Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]/C
  2027. clock pessimism 0.273 14.391
  2028. clock uncertainty -0.072 14.318
  2029. SLICE_X4Y46 FDRE (Setup_fdre_C_D) 0.032 14.350 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]
  2030. -------------------------------------------------------------------
  2031. required time 14.350
  2032. arrival time -9.955
  2033. -------------------------------------------------------------------
  2034. slack 4.396
  2035. Min Delay Paths
  2036. --------------------------------------------------------------------------------------
  2037. Slack (MET) : 0.064ns (arrival time - required time)
  2038. Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
  2039. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2040. Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]/D
  2041. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2042. Path Group: clk_out1_clk_wiz_0
  2043. Path Type: Hold (Min at Fast Process Corner)
  2044. Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  2045. Data Path Delay: 0.354ns (logic 0.148ns (41.815%) route 0.206ns (58.185%))
  2046. Logic Levels: 0
  2047. Clock Path Skew: 0.273ns (DCD - SCD - CPR)
  2048. Destination Clock Delay (DCD): 1.992ns
  2049. Source Clock Delay (SCD): 1.475ns
  2050. Clock Pessimism Removal (CPR): 0.244ns
  2051. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  2052. ------------------------------------------------------------------- -------------------
  2053. (clock clk_out1_clk_wiz_0 rise edge)
  2054. 0.000 0.000 r
  2055. W5 0.000 0.000 r CLK (IN)
  2056. net (fo=0) 0.000 0.000 CLK
  2057. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  2058. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  2059. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  2060. net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2061. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2062. -1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2063. net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2064. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2065. net (fo=336, routed) 0.592 1.475 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2066. SLICE_X6Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
  2067. ------------------------------------------------------------------- -------------------
  2068. SLICE_X6Y50 FDRE (Prop_fdre_C_Q) 0.148 1.623 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/Q
  2069. net (fo=3, routed) 0.206 1.829 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/CONV_INTEGER[6]
  2070. SLICE_X7Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]/D
  2071. ------------------------------------------------------------------- -------------------
  2072. (clock clk_out1_clk_wiz_0 rise edge)
  2073. 0.000 0.000 r
  2074. W5 0.000 0.000 r CLK (IN)
  2075. net (fo=0) 0.000 0.000 CLK
  2076. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  2077. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  2078. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  2079. net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2080. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2081. -1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2082. net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2083. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2084. net (fo=336, routed) 0.865 1.992 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2085. SLICE_X7Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]/C
  2086. clock pessimism -0.244 1.748
  2087. SLICE_X7Y49 FDRE (Hold_fdre_C_D) 0.017 1.765 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]
  2088. -------------------------------------------------------------------
  2089. required time -1.765
  2090. arrival time 1.829
  2091. -------------------------------------------------------------------
  2092. slack 0.064
  2093. Slack (MET) : 0.068ns (arrival time - required time)
  2094. Source: Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[0]/C
  2095. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2096. Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]/D
  2097. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2098. Path Group: clk_out1_clk_wiz_0
  2099. Path Type: Hold (Min at Fast Process Corner)
  2100. Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  2101. Data Path Delay: 0.488ns (logic 0.209ns (42.827%) route 0.279ns (57.173%))
  2102. Logic Levels: 1 (LUT3=1)
  2103. Clock Path Skew: 0.300ns (DCD - SCD - CPR)
  2104. Destination Clock Delay (DCD): 1.992ns
  2105. Source Clock Delay (SCD): 1.448ns
  2106. Clock Pessimism Removal (CPR): 0.244ns
  2107. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  2108. ------------------------------------------------------------------- -------------------
  2109. (clock clk_out1_clk_wiz_0 rise edge)
  2110. 0.000 0.000 r
  2111. W5 0.000 0.000 r CLK (IN)
  2112. net (fo=0) 0.000 0.000 CLK
  2113. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  2114. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  2115. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  2116. net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2117. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2118. -1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2119. net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2120. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2121. net (fo=336, routed) 0.565 1.448 Inst_vga_ctrl/Inst_MouseCtl/clk
  2122. SLICE_X8Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[0]/C
  2123. ------------------------------------------------------------------- -------------------
  2124. SLICE_X8Y50 FDRE (Prop_fdre_C_Q) 0.164 1.612 r Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[0]/Q
  2125. net (fo=2, routed) 0.279 1.891 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_data[0]
  2126. SLICE_X6Y49 LUT3 (Prop_lut3_I1_O) 0.045 1.936 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[1]_i_1/O
  2127. net (fo=1, routed) 0.000 1.936 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[1]_i_1_n_0
  2128. SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]/D
  2129. ------------------------------------------------------------------- -------------------
  2130. (clock clk_out1_clk_wiz_0 rise edge)
  2131. 0.000 0.000 r
  2132. W5 0.000 0.000 r CLK (IN)
  2133. net (fo=0) 0.000 0.000 CLK
  2134. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  2135. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  2136. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  2137. net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2138. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2139. -1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2140. net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2141. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2142. net (fo=336, routed) 0.865 1.992 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2143. SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]/C
  2144. clock pessimism -0.244 1.748
  2145. SLICE_X6Y49 FDRE (Hold_fdre_C_D) 0.120 1.868 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]
  2146. -------------------------------------------------------------------
  2147. required time -1.868
  2148. arrival time 1.936
  2149. -------------------------------------------------------------------
  2150. slack 0.068
  2151. Slack (MET) : 0.090ns (arrival time - required time)
  2152. Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg[2]/C
  2153. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2154. Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv/D
  2155. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2156. Path Group: clk_out1_clk_wiz_0
  2157. Path Type: Hold (Min at Fast Process Corner)
  2158. Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  2159. Data Path Delay: 0.448ns (logic 0.209ns (46.656%) route 0.239ns (53.344%))
  2160. Logic Levels: 1 (LUT6=1)
  2161. Clock Path Skew: 0.267ns (DCD - SCD - CPR)
  2162. Destination Clock Delay (DCD): 1.990ns
  2163. Source Clock Delay (SCD): 1.479ns
  2164. Clock Pessimism Removal (CPR): 0.244ns
  2165. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  2166. ------------------------------------------------------------------- -------------------
  2167. (clock clk_out1_clk_wiz_0 rise edge)
  2168. 0.000 0.000 r
  2169. W5 0.000 0.000 r CLK (IN)
  2170. net (fo=0) 0.000 0.000 CLK
  2171. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  2172. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  2173. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  2174. net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2175. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2176. -1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2177. net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2178. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2179. net (fo=336, routed) 0.596 1.479 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2180. SLICE_X2Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg[2]/C
  2181. ------------------------------------------------------------------- -------------------
  2182. SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 1.643 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg[2]/Q
  2183. net (fo=28, routed) 0.239 1.882 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg_n_0_[2]
  2184. SLICE_X5Y50 LUT6 (Prop_lut6_I1_O) 0.045 1.927 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_inv_i_2/O
  2185. net (fo=1, routed) 0.000 1.927 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_inv_i_1_n_0
  2186. SLICE_X5Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv/D
  2187. ------------------------------------------------------------------- -------------------
  2188. (clock clk_out1_clk_wiz_0 rise edge)
  2189. 0.000 0.000 r
  2190. W5 0.000 0.000 r CLK (IN)
  2191. net (fo=0) 0.000 0.000 CLK
  2192. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  2193. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  2194. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  2195. net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2196. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2197. -1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2198. net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2199. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2200. net (fo=336, routed) 0.863 1.990 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2201. SLICE_X5Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv/C
  2202. clock pessimism -0.244 1.746
  2203. SLICE_X5Y50 FDRE (Hold_fdre_C_D) 0.091 1.837 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv
  2204. -------------------------------------------------------------------
  2205. required time -1.837
  2206. arrival time 1.927
  2207. -------------------------------------------------------------------
  2208. slack 0.090
  2209. Slack (MET) : 0.091ns (arrival time - required time)
  2210. Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
  2211. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2212. Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg/D
  2213. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2214. Path Group: clk_out1_clk_wiz_0
  2215. Path Type: Hold (Min at Fast Process Corner)
  2216. Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  2217. Data Path Delay: 0.485ns (logic 0.246ns (50.728%) route 0.239ns (49.272%))
  2218. Logic Levels: 1 (LUT5=1)
  2219. Clock Path Skew: 0.273ns (DCD - SCD - CPR)
  2220. Destination Clock Delay (DCD): 1.992ns
  2221. Source Clock Delay (SCD): 1.475ns
  2222. Clock Pessimism Removal (CPR): 0.244ns
  2223. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  2224. ------------------------------------------------------------------- -------------------
  2225. (clock clk_out1_clk_wiz_0 rise edge)
  2226. 0.000 0.000 r
  2227. W5 0.000 0.000 r CLK (IN)
  2228. net (fo=0) 0.000 0.000 CLK
  2229. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  2230. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  2231. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  2232. net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2233. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2234. -1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2235. net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2236. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2237. net (fo=336, routed) 0.592 1.475 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2238. SLICE_X6Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
  2239. ------------------------------------------------------------------- -------------------
  2240. SLICE_X6Y50 FDRE (Prop_fdre_C_Q) 0.148 1.623 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/Q
  2241. net (fo=3, routed) 0.239 1.862 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/CONV_INTEGER[6]
  2242. SLICE_X6Y48 LUT5 (Prop_lut5_I3_O) 0.098 1.960 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_i_1/O
  2243. net (fo=1, routed) 0.000 1.960 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_i_1_n_0
  2244. SLICE_X6Y48 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg/D
  2245. ------------------------------------------------------------------- -------------------
  2246. (clock clk_out1_clk_wiz_0 rise edge)
  2247. 0.000 0.000 r
  2248. W5 0.000 0.000 r CLK (IN)
  2249. net (fo=0) 0.000 0.000 CLK
  2250. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  2251. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  2252. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  2253. net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2254. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2255. -1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2256. net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2257. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2258. net (fo=336, routed) 0.865 1.992 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2259. SLICE_X6Y48 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg/C
  2260. clock pessimism -0.244 1.748
  2261. SLICE_X6Y48 FDRE (Hold_fdre_C_D) 0.121 1.869 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg
  2262. -------------------------------------------------------------------
  2263. required time -1.869
  2264. arrival time 1.960
  2265. -------------------------------------------------------------------
  2266. slack 0.091
  2267. Slack (MET) : 0.102ns (arrival time - required time)
  2268. Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_parity_reg/C
  2269. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2270. Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]/D
  2271. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2272. Path Group: clk_out1_clk_wiz_0
  2273. Path Type: Hold (Min at Fast Process Corner)
  2274. Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  2275. Data Path Delay: 0.506ns (logic 0.185ns (36.583%) route 0.321ns (63.417%))
  2276. Logic Levels: 1 (LUT3=1)
  2277. Clock Path Skew: 0.273ns (DCD - SCD - CPR)
  2278. Destination Clock Delay (DCD): 1.992ns
  2279. Source Clock Delay (SCD): 1.475ns
  2280. Clock Pessimism Removal (CPR): 0.244ns
  2281. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  2282. ------------------------------------------------------------------- -------------------
  2283. (clock clk_out1_clk_wiz_0 rise edge)
  2284. 0.000 0.000 r
  2285. W5 0.000 0.000 r CLK (IN)
  2286. net (fo=0) 0.000 0.000 CLK
  2287. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  2288. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  2289. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  2290. net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2291. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2292. -1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2293. net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2294. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2295. net (fo=336, routed) 0.592 1.475 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2296. SLICE_X7Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_parity_reg/C
  2297. ------------------------------------------------------------------- -------------------
  2298. SLICE_X7Y50 FDRE (Prop_fdre_C_Q) 0.141 1.616 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_parity_reg/Q
  2299. net (fo=1, routed) 0.321 1.937 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/p_1_in[9]
  2300. SLICE_X6Y49 LUT3 (Prop_lut3_I0_O) 0.044 1.981 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_2/O
  2301. net (fo=1, routed) 0.000 1.981 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_2_n_0
  2302. SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]/D
  2303. ------------------------------------------------------------------- -------------------
  2304. (clock clk_out1_clk_wiz_0 rise edge)
  2305. 0.000 0.000 r
  2306. W5 0.000 0.000 r CLK (IN)
  2307. net (fo=0) 0.000 0.000 CLK
  2308. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  2309. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  2310. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  2311. net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2312. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2313. -1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2314. net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2315. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2316. net (fo=336, routed) 0.865 1.992 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2317. SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]/C
  2318. clock pessimism -0.244 1.748
  2319. SLICE_X6Y49 FDRE (Hold_fdre_C_D) 0.131 1.879 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]
  2320. -------------------------------------------------------------------
  2321. required time -1.879
  2322. arrival time 1.981
  2323. -------------------------------------------------------------------
  2324. slack 0.102
  2325. Slack (MET) : 0.104ns (arrival time - required time)
  2326. Source: Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[7]/C
  2327. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2328. Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/D
  2329. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2330. Path Group: clk_out1_clk_wiz_0
  2331. Path Type: Hold (Min at Fast Process Corner)
  2332. Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  2333. Data Path Delay: 0.534ns (logic 0.250ns (46.773%) route 0.284ns (53.227%))
  2334. Logic Levels: 1 (LUT3=1)
  2335. Clock Path Skew: 0.300ns (DCD - SCD - CPR)
  2336. Destination Clock Delay (DCD): 1.992ns
  2337. Source Clock Delay (SCD): 1.448ns
  2338. Clock Pessimism Removal (CPR): 0.244ns
  2339. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  2340. ------------------------------------------------------------------- -------------------
  2341. (clock clk_out1_clk_wiz_0 rise edge)
  2342. 0.000 0.000 r
  2343. W5 0.000 0.000 r CLK (IN)
  2344. net (fo=0) 0.000 0.000 CLK
  2345. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  2346. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  2347. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  2348. net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2349. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2350. -1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2351. net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2352. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2353. net (fo=336, routed) 0.565 1.448 Inst_vga_ctrl/Inst_MouseCtl/clk
  2354. SLICE_X8Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[7]/C
  2355. ------------------------------------------------------------------- -------------------
  2356. SLICE_X8Y50 FDRE (Prop_fdre_C_Q) 0.148 1.596 r Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[7]/Q
  2357. net (fo=2, routed) 0.284 1.881 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_data[7]
  2358. SLICE_X6Y49 LUT3 (Prop_lut3_I0_O) 0.102 1.983 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[8]_i_1/O
  2359. net (fo=1, routed) 0.000 1.983 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[8]_i_1_n_0
  2360. SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/D
  2361. ------------------------------------------------------------------- -------------------
  2362. (clock clk_out1_clk_wiz_0 rise edge)
  2363. 0.000 0.000 r
  2364. W5 0.000 0.000 r CLK (IN)
  2365. net (fo=0) 0.000 0.000 CLK
  2366. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  2367. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  2368. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  2369. net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2370. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2371. -1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2372. net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2373. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2374. net (fo=336, routed) 0.865 1.992 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2375. SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/C
  2376. clock pessimism -0.244 1.748
  2377. SLICE_X6Y49 FDRE (Hold_fdre_C_D) 0.131 1.879 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]
  2378. -------------------------------------------------------------------
  2379. required time -1.879
  2380. arrival time 1.983
  2381. -------------------------------------------------------------------
  2382. slack 0.104
  2383. Slack (MET) : 0.114ns (arrival time - required time)
  2384. Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
  2385. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2386. Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]/D
  2387. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2388. Path Group: clk_out1_clk_wiz_0
  2389. Path Type: Hold (Min at Fast Process Corner)
  2390. Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  2391. Data Path Delay: 0.488ns (logic 0.355ns (72.708%) route 0.133ns (27.292%))
  2392. Logic Levels: 2 (CARRY4=2)
  2393. Clock Path Skew: 0.269ns (DCD - SCD - CPR)
  2394. Destination Clock Delay (DCD): 1.990ns
  2395. Source Clock Delay (SCD): 1.477ns
  2396. Clock Pessimism Removal (CPR): 0.244ns
  2397. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  2398. ------------------------------------------------------------------- -------------------
  2399. (clock clk_out1_clk_wiz_0 rise edge)
  2400. 0.000 0.000 r
  2401. W5 0.000 0.000 r CLK (IN)
  2402. net (fo=0) 0.000 0.000 CLK
  2403. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  2404. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  2405. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  2406. net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2407. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2408. -1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2409. net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2410. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2411. net (fo=336, routed) 0.594 1.477 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2412. SLICE_X4Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
  2413. ------------------------------------------------------------------- -------------------
  2414. SLICE_X4Y49 FDRE (Prop_fdre_C_Q) 0.141 1.618 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/Q
  2415. net (fo=2, routed) 0.133 1.751 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]
  2416. SLICE_X4Y49 CARRY4 (Prop_carry4_S[2]_CO[3])
  2417. 0.160 1.911 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3/CO[3]
  2418. net (fo=1, routed) 0.001 1.911 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3_n_0
  2419. SLICE_X4Y50 CARRY4 (Prop_carry4_CI_O[0])
  2420. 0.054 1.965 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1/O[0]
  2421. net (fo=1, routed) 0.000 1.965 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1_n_7
  2422. SLICE_X4Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]/D
  2423. ------------------------------------------------------------------- -------------------
  2424. (clock clk_out1_clk_wiz_0 rise edge)
  2425. 0.000 0.000 r
  2426. W5 0.000 0.000 r CLK (IN)
  2427. net (fo=0) 0.000 0.000 CLK
  2428. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  2429. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  2430. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  2431. net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2432. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2433. -1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2434. net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2435. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2436. net (fo=336, routed) 0.863 1.990 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2437. SLICE_X4Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]/C
  2438. clock pessimism -0.244 1.746
  2439. SLICE_X4Y50 FDRE (Hold_fdre_C_D) 0.105 1.851 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]
  2440. -------------------------------------------------------------------
  2441. required time -1.851
  2442. arrival time 1.965
  2443. -------------------------------------------------------------------
  2444. slack 0.114
  2445. Slack (MET) : 0.122ns (arrival time - required time)
  2446. Source: Inst_vga_ctrl/h_sync_reg_reg/C
  2447. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2448. Destination: Inst_vga_ctrl/h_sync_reg_dly_reg/D
  2449. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2450. Path Group: clk_out1_clk_wiz_0
  2451. Path Type: Hold (Min at Fast Process Corner)
  2452. Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  2453. Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
  2454. Logic Levels: 0
  2455. Clock Path Skew: 0.000ns (DCD - SCD - CPR)
  2456. Destination Clock Delay (DCD): 1.990ns
  2457. Source Clock Delay (SCD): 1.475ns
  2458. Clock Pessimism Removal (CPR): 0.515ns
  2459. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  2460. ------------------------------------------------------------------- -------------------
  2461. (clock clk_out1_clk_wiz_0 rise edge)
  2462. 0.000 0.000 r
  2463. W5 0.000 0.000 r CLK (IN)
  2464. net (fo=0) 0.000 0.000 CLK
  2465. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  2466. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  2467. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  2468. net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2469. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2470. -1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2471. net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2472. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2473. net (fo=336, routed) 0.592 1.475 Inst_vga_ctrl/pxl_clk
  2474. SLICE_X7Y40 FDRE r Inst_vga_ctrl/h_sync_reg_reg/C
  2475. ------------------------------------------------------------------- -------------------
  2476. SLICE_X7Y40 FDRE (Prop_fdre_C_Q) 0.141 1.616 r Inst_vga_ctrl/h_sync_reg_reg/Q
  2477. net (fo=1, routed) 0.056 1.672 Inst_vga_ctrl/h_sync_reg
  2478. SLICE_X7Y40 FDRE r Inst_vga_ctrl/h_sync_reg_dly_reg/D
  2479. ------------------------------------------------------------------- -------------------
  2480. (clock clk_out1_clk_wiz_0 rise edge)
  2481. 0.000 0.000 r
  2482. W5 0.000 0.000 r CLK (IN)
  2483. net (fo=0) 0.000 0.000 CLK
  2484. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  2485. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  2486. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  2487. net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2488. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2489. -1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2490. net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2491. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2492. net (fo=336, routed) 0.863 1.990 Inst_vga_ctrl/pxl_clk
  2493. SLICE_X7Y40 FDRE r Inst_vga_ctrl/h_sync_reg_dly_reg/C
  2494. clock pessimism -0.515 1.475
  2495. SLICE_X7Y40 FDRE (Hold_fdre_C_D) 0.075 1.550 Inst_vga_ctrl/h_sync_reg_dly_reg
  2496. -------------------------------------------------------------------
  2497. required time -1.550
  2498. arrival time 1.672
  2499. -------------------------------------------------------------------
  2500. slack 0.122
  2501. Slack (MET) : 0.125ns (arrival time - required time)
  2502. Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
  2503. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2504. Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]/D
  2505. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2506. Path Group: clk_out1_clk_wiz_0
  2507. Path Type: Hold (Min at Fast Process Corner)
  2508. Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  2509. Data Path Delay: 0.499ns (logic 0.366ns (73.309%) route 0.133ns (26.691%))
  2510. Logic Levels: 2 (CARRY4=2)
  2511. Clock Path Skew: 0.269ns (DCD - SCD - CPR)
  2512. Destination Clock Delay (DCD): 1.990ns
  2513. Source Clock Delay (SCD): 1.477ns
  2514. Clock Pessimism Removal (CPR): 0.244ns
  2515. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  2516. ------------------------------------------------------------------- -------------------
  2517. (clock clk_out1_clk_wiz_0 rise edge)
  2518. 0.000 0.000 r
  2519. W5 0.000 0.000 r CLK (IN)
  2520. net (fo=0) 0.000 0.000 CLK
  2521. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  2522. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  2523. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  2524. net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2525. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2526. -1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2527. net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2528. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2529. net (fo=336, routed) 0.594 1.477 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2530. SLICE_X4Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
  2531. ------------------------------------------------------------------- -------------------
  2532. SLICE_X4Y49 FDRE (Prop_fdre_C_Q) 0.141 1.618 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/Q
  2533. net (fo=2, routed) 0.133 1.751 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]
  2534. SLICE_X4Y49 CARRY4 (Prop_carry4_S[2]_CO[3])
  2535. 0.160 1.911 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3/CO[3]
  2536. net (fo=1, routed) 0.001 1.911 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3_n_0
  2537. SLICE_X4Y50 CARRY4 (Prop_carry4_CI_O[2])
  2538. 0.065 1.976 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1/O[2]
  2539. net (fo=1, routed) 0.000 1.976 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1_n_5
  2540. SLICE_X4Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]/D
  2541. ------------------------------------------------------------------- -------------------
  2542. (clock clk_out1_clk_wiz_0 rise edge)
  2543. 0.000 0.000 r
  2544. W5 0.000 0.000 r CLK (IN)
  2545. net (fo=0) 0.000 0.000 CLK
  2546. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  2547. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  2548. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  2549. net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2550. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2551. -1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2552. net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2553. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2554. net (fo=336, routed) 0.863 1.990 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2555. SLICE_X4Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]/C
  2556. clock pessimism -0.244 1.746
  2557. SLICE_X4Y50 FDRE (Hold_fdre_C_D) 0.105 1.851 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]
  2558. -------------------------------------------------------------------
  2559. required time -1.851
  2560. arrival time 1.976
  2561. -------------------------------------------------------------------
  2562. slack 0.125
  2563. Slack (MET) : 0.144ns (arrival time - required time)
  2564. Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/C
  2565. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2566. Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/D
  2567. (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
  2568. Path Group: clk_out1_clk_wiz_0
  2569. Path Type: Hold (Min at Fast Process Corner)
  2570. Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  2571. Data Path Delay: 0.544ns (logic 0.249ns (45.767%) route 0.295ns (54.233%))
  2572. Logic Levels: 1 (LUT3=1)
  2573. Clock Path Skew: 0.269ns (DCD - SCD - CPR)
  2574. Destination Clock Delay (DCD): 1.990ns
  2575. Source Clock Delay (SCD): 1.477ns
  2576. Clock Pessimism Removal (CPR): 0.244ns
  2577. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
  2578. ------------------------------------------------------------------- -------------------
  2579. (clock clk_out1_clk_wiz_0 rise edge)
  2580. 0.000 0.000 r
  2581. W5 0.000 0.000 r CLK (IN)
  2582. net (fo=0) 0.000 0.000 CLK
  2583. W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
  2584. net (fo=1, routed) 0.631 0.858 CLK_IBUF
  2585. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
  2586. net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2587. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2588. -1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2589. net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2590. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2591. net (fo=336, routed) 0.594 1.477 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2592. SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/C
  2593. ------------------------------------------------------------------- -------------------
  2594. SLICE_X6Y49 FDRE (Prop_fdre_C_Q) 0.148 1.625 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/Q
  2595. net (fo=3, routed) 0.295 1.920 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/CONV_INTEGER[7]
  2596. SLICE_X6Y50 LUT3 (Prop_lut3_I2_O) 0.101 2.021 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[7]_i_1/O
  2597. net (fo=1, routed) 0.000 2.021 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[7]_i_1_n_0
  2598. SLICE_X6Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/D
  2599. ------------------------------------------------------------------- -------------------
  2600. (clock clk_out1_clk_wiz_0 rise edge)
  2601. 0.000 0.000 r
  2602. W5 0.000 0.000 r CLK (IN)
  2603. net (fo=0) 0.000 0.000 CLK
  2604. W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
  2605. net (fo=1, routed) 0.685 1.099 CLK_IBUF
  2606. BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
  2607. net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
  2608. MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
  2609. -1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2610. net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
  2611. BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
  2612. net (fo=336, routed) 0.863 1.990 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
  2613. SLICE_X6Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
  2614. clock pessimism -0.244 1.746
  2615. SLICE_X6Y50 FDRE (Hold_fdre_C_D) 0.131 1.877 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]
  2616. -------------------------------------------------------------------
  2617. required time -1.877
  2618. arrival time 2.021
  2619. -------------------------------------------------------------------
  2620. slack 0.144
  2621. Pulse Width Checks
  2622. --------------------------------------------------------------------------------------
  2623. Clock Name: clk_out1_clk_wiz_0
  2624. Waveform(ns): { 0.000 4.630 }
  2625. Period(ns): 9.259
  2626. Sources: { Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0 }
  2627. Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
  2628. Min Period n/a BUFG/I n/a 2.155 9.259 7.104 BUFGCTRL_X0Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/I
  2629. Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 9.259 8.010 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2630. Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X12Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[10]/C
  2631. Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X14Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[1]/C
  2632. Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X14Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[2]/C
  2633. Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X13Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[3]/C
  2634. Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X13Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[4]/C
  2635. Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X13Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[5]/C
  2636. Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X12Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[6]/C
  2637. Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X13Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[7]/C
  2638. Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 9.259 204.101 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
  2639. Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X1Y31 Inst_vga_ctrl/cntDyn_reg[0]/C
  2640. Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X1Y31 Inst_vga_ctrl/cntDyn_reg[1]/C
  2641. Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X1Y31 Inst_vga_ctrl/cntDyn_reg[2]/C
  2642. Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X1Y31 Inst_vga_ctrl/cntDyn_reg[3]/C
  2643. Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X4Y46 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/C
  2644. Low Pulse Width Fast FDRE/C n/a 0.500 4.630 4.130 SLICE_X5Y42 Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[1]/C
  2645. Low Pulse Width Fast FDRE/C n/a 0.500 4.630 4.130 SLICE_X5Y42 Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[2]/C
  2646. Low Pulse Width Fast FDRE/C n/a 0.500 4.630 4.130 SLICE_X5Y42 Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[5]/C
  2647. Low Pulse Width Fast FDRE/C n/a 0.500 4.630 4.130 SLICE_X5Y42 Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[7]/C
  2648. Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X6Y45 Inst_vga_ctrl/MOUSE_X_POS_REG_reg[10]/C
  2649. High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X7Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_done_reg/C
  2650. High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y45 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[13]/C
  2651. High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X9Y44 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[14]/C
  2652. High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y45 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[15]/C
  2653. High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y45 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[16]/C
  2654. High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y45 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[17]/C
  2655. High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X9Y44 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[18]/C
  2656. High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y45 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[19]/C
  2657. High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y42 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[1]/C
  2658. High Pulse Width Fast FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y42 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[1]/C
  2659. ---------------------------------------------------------------------------------------------------
  2660. From Clock: clkfbout_clk_wiz_0
  2661. To Clock: clkfbout_clk_wiz_0
  2662. Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
  2663. Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
  2664. PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns
  2665. ---------------------------------------------------------------------------------------------------
  2666. Pulse Width Checks
  2667. --------------------------------------------------------------------------------------
  2668. Clock Name: clkfbout_clk_wiz_0
  2669. Waveform(ns): { 0.000 5.000 }
  2670. Period(ns): 10.000
  2671. Sources: { Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT }
  2672. Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
  2673. Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y2 Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf/I
  2674. Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT
  2675. Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBIN
  2676. Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBIN
  2677. Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT