506 lines
21 KiB
HTML
506 lines
21 KiB
HTML
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
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<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
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<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>1756540</TD>
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</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Fri Apr 09 23:19:55 2021</TD>
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<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
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</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2016.4 (64-bit)</TD>
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<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>0138f6f78b4b4ef3a03837b84ae3d333</TD>
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</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>1</TD>
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<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>89e526329a235cb691995f8457477284</TD>
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</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>89e526329a235cb691995f8457477284</TD>
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<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
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</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a35t</TD>
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<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
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</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>cpg236</TD>
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<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
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</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
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</TR> </TABLE><BR>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
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<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz</TD>
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<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2592 MHz</TD>
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</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
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<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
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</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
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<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
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</TR> </TABLE><BR>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
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<TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>runbitgen=1</TD>
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<TD>runimplementation=1</TD>
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<TD>runsynthesis=1</TD>
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</TR> </TABLE>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>guimode=1</TD>
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</TR> </TABLE>
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</TR><TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>constraintsetcount=1</TD>
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<TD>core_container=false</TD>
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<TD>currentimplrun=impl_1</TD>
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<TD>currentsynthesisrun=synth_1</TD>
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</TR><TR ALIGN='LEFT'> <TD>default_library=xil_defaultlib</TD>
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<TD>designmode=RTL</TD>
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<TD>export_simulation_activehdl=0</TD>
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<TD>export_simulation_ies=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>export_simulation_modelsim=0</TD>
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<TD>export_simulation_questa=0</TD>
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<TD>export_simulation_riviera=0</TD>
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<TD>export_simulation_vcs=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>export_simulation_xsim=0</TD>
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<TD>implstrategy=Vivado Implementation Defaults</TD>
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<TD>launch_simulation_activehdl=0</TD>
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<TD>launch_simulation_ies=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>launch_simulation_modelsim=0</TD>
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<TD>launch_simulation_questa=0</TD>
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<TD>launch_simulation_riviera=0</TD>
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<TD>launch_simulation_vcs=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>launch_simulation_xsim=0</TD>
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<TD>simulator_language=Mixed</TD>
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<TD>srcsetcount=9</TD>
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<TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
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</TR><TR ALIGN='LEFT'> <TD>target_language=VHDL</TD>
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<TD>target_simulator=XSim</TD>
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<TD>totalimplruns=1</TD>
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<TD>totalsynthesisruns=1</TD>
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</TR> </TABLE>
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</TR> </TABLE><BR>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
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<TR><TD>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>bufg=3</TD>
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<TD>carry4=132</TD>
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<TD>fdre=579</TD>
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<TD>fdse=2</TD>
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</TR><TR ALIGN='LEFT'> <TD>gnd=8</TD>
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<TD>ibuf=24</TD>
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<TD>lut1=368</TD>
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<TD>lut2=207</TD>
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</TR><TR ALIGN='LEFT'> <TD>lut3=91</TD>
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<TD>lut4=138</TD>
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<TD>lut5=73</TD>
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<TD>lut6=157</TD>
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</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv=1</TD>
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<TD>muxf7=3</TD>
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<TD>obuf=43</TD>
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<TD>obuft=2</TD>
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</TR><TR ALIGN='LEFT'> <TD>vcc=8</TD>
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</TR> </TABLE>
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</TD></TR>
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<TR><TD>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>bufg=3</TD>
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<TD>carry4=132</TD>
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<TD>fdre=579</TD>
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<TD>fdse=2</TD>
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</TR><TR ALIGN='LEFT'> <TD>gnd=8</TD>
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<TD>ibuf=22</TD>
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<TD>iobuf=2</TD>
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<TD>lut1=368</TD>
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</TR><TR ALIGN='LEFT'> <TD>lut2=207</TD>
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<TD>lut3=91</TD>
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<TD>lut4=138</TD>
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<TD>lut5=73</TD>
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</TR><TR ALIGN='LEFT'> <TD>lut6=157</TD>
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<TD>mmcme2_adv=1</TD>
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<TD>muxf7=3</TD>
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<TD>obuf=43</TD>
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</TR><TR ALIGN='LEFT'> <TD>vcc=8</TD>
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</TR> </TABLE>
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</TD></TR>
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</TABLE><BR>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
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<TR><TD>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v5_1/1</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>clkin1_period=10.0</TD>
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<TD>clkin2_period=10.0</TD>
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<TD>clock_mgr_type=NA</TD>
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<TD>component_name=clk_wiz_0</TD>
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</TR><TR ALIGN='LEFT'> <TD>core_container=NA</TD>
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<TD>enable_axi=0</TD>
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<TD>feedback_source=FDBK_AUTO</TD>
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<TD>feedback_type=SINGLE</TD>
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</TR><TR ALIGN='LEFT'> <TD>iptotal=1</TD>
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<TD>manual_override=false</TD>
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<TD>num_out_clk=1</TD>
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<TD>primitive=MMCM</TD>
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</TR><TR ALIGN='LEFT'> <TD>use_dyn_phase_shift=false</TD>
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<TD>use_dyn_reconfig=false</TD>
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<TD>use_inclk_stopped=false</TD>
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<TD>use_inclk_switchover=false</TD>
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</TR><TR ALIGN='LEFT'> <TD>use_locked=false</TD>
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<TD>use_max_i_jitter=false</TD>
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<TD>use_min_o_jitter=false</TD>
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<TD>use_phase_alignment=true</TD>
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</TR><TR ALIGN='LEFT'> <TD>use_power_down=false</TD>
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<TD>use_reset=false</TD>
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</TR> </TABLE>
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</TD></TR>
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</TABLE><BR>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
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<TR><TD>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
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<TD>-checks=default::[not_specified]</TD>
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<TD>-fail_on=default::[not_specified]</TD>
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<TD>-force=default::[not_specified]</TD>
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</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
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<TD>-messages=default::[not_specified]</TD>
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<TD>-name=default::[not_specified]</TD>
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<TD>-return_string=default::[not_specified]</TD>
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</TR><TR ALIGN='LEFT'> <TD>-ruledecks=default::[not_specified]</TD>
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<TD>-upgrade_cw=default::[not_specified]</TD>
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</TR> </TABLE>
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</TD></TR>
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</TABLE><BR>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
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<TR><TD>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>bufgctrl_available=32</TD>
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<TD>bufgctrl_fixed=0</TD>
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<TD>bufgctrl_used=3</TD>
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<TD>bufgctrl_util_percentage=9.38</TD>
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</TR><TR ALIGN='LEFT'> <TD>bufhce_available=72</TD>
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<TD>bufhce_fixed=0</TD>
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<TD>bufhce_used=0</TD>
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<TD>bufhce_util_percentage=0.00</TD>
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</TR><TR ALIGN='LEFT'> <TD>bufio_available=20</TD>
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<TD>bufio_fixed=0</TD>
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<TD>bufio_used=0</TD>
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<TD>bufio_util_percentage=0.00</TD>
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</TR><TR ALIGN='LEFT'> <TD>bufmrce_available=10</TD>
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<TD>bufmrce_fixed=0</TD>
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<TD>bufmrce_used=0</TD>
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<TD>bufmrce_util_percentage=0.00</TD>
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</TR><TR ALIGN='LEFT'> <TD>bufr_available=20</TD>
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<TD>bufr_fixed=0</TD>
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<TD>bufr_used=0</TD>
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<TD>bufr_util_percentage=0.00</TD>
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</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv_available=5</TD>
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<TD>mmcme2_adv_fixed=0</TD>
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<TD>mmcme2_adv_used=1</TD>
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<TD>mmcme2_adv_util_percentage=20.00</TD>
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</TR><TR ALIGN='LEFT'> <TD>plle2_adv_available=5</TD>
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<TD>plle2_adv_fixed=0</TD>
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<TD>plle2_adv_used=0</TD>
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<TD>plle2_adv_util_percentage=0.00</TD>
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</TR> </TABLE>
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</TD></TR>
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<TR><TD>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>dsps_available=90</TD>
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<TD>dsps_fixed=0</TD>
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<TD>dsps_used=0</TD>
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<TD>dsps_util_percentage=0.00</TD>
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</TR> </TABLE>
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</TD></TR>
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<TR><TD>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>blvds_25=0</TD>
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<TD>diff_hstl_i=0</TD>
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<TD>diff_hstl_i_18=0</TD>
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<TD>diff_hstl_ii=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>diff_hstl_ii_18=0</TD>
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<TD>diff_hsul_12=0</TD>
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<TD>diff_mobile_ddr=0</TD>
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<TD>diff_sstl135=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>diff_sstl135_r=0</TD>
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<TD>diff_sstl15=0</TD>
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<TD>diff_sstl15_r=0</TD>
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<TD>diff_sstl18_i=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>diff_sstl18_ii=0</TD>
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<TD>hstl_i=0</TD>
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<TD>hstl_i_18=0</TD>
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<TD>hstl_ii=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>hstl_ii_18=0</TD>
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<TD>hsul_12=0</TD>
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<TD>lvcmos12=0</TD>
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<TD>lvcmos15=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>lvcmos18=0</TD>
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<TD>lvcmos25=0</TD>
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<TD>lvcmos33=1</TD>
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<TD>lvds_25=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>lvttl=0</TD>
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<TD>mini_lvds_25=0</TD>
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<TD>mobile_ddr=0</TD>
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<TD>pci33_3=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>ppds_25=0</TD>
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<TD>rsds_25=0</TD>
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<TD>sstl135=0</TD>
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<TD>sstl135_r=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>sstl15=0</TD>
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<TD>sstl15_r=0</TD>
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<TD>sstl18_i=0</TD>
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<TD>sstl18_ii=0</TD>
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</TR><TR ALIGN='LEFT'> <TD>tmds_33=0</TD>
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</TR> </TABLE>
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</TD></TR>
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<TR><TD>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>block_ram_tile_available=50</TD>
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<TD>block_ram_tile_fixed=0</TD>
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<TD>block_ram_tile_used=0</TD>
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<TD>block_ram_tile_util_percentage=0.00</TD>
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</TR><TR ALIGN='LEFT'> <TD>ramb18_available=100</TD>
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<TD>ramb18_fixed=0</TD>
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<TD>ramb18_used=0</TD>
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<TD>ramb18_util_percentage=0.00</TD>
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</TR><TR ALIGN='LEFT'> <TD>ramb36_fifo_available=50</TD>
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<TD>ramb36_fifo_fixed=0</TD>
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<TD>ramb36_fifo_used=0</TD>
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<TD>ramb36_fifo_util_percentage=0.00</TD>
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</TR> </TABLE>
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</TD></TR>
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<TR><TD>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>bufg_functional_category=Clock</TD>
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<TD>bufg_used=3</TD>
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<TD>carry4_functional_category=CarryLogic</TD>
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<TD>carry4_used=132</TD>
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</TR><TR ALIGN='LEFT'> <TD>fdre_functional_category=Flop & Latch</TD>
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<TD>fdre_used=576</TD>
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<TD>fdse_functional_category=Flop & Latch</TD>
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<TD>fdse_used=2</TD>
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</TR><TR ALIGN='LEFT'> <TD>ibuf_functional_category=IO</TD>
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<TD>ibuf_used=24</TD>
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<TD>lut1_functional_category=LUT</TD>
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<TD>lut1_used=30</TD>
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</TR><TR ALIGN='LEFT'> <TD>lut2_functional_category=LUT</TD>
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<TD>lut2_used=207</TD>
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<TD>lut3_functional_category=LUT</TD>
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<TD>lut3_used=93</TD>
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</TR><TR ALIGN='LEFT'> <TD>lut4_functional_category=LUT</TD>
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<TD>lut4_used=136</TD>
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<TD>lut5_functional_category=LUT</TD>
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<TD>lut5_used=72</TD>
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</TR><TR ALIGN='LEFT'> <TD>lut6_functional_category=LUT</TD>
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<TD>lut6_used=157</TD>
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<TD>mmcme2_adv_functional_category=Clock</TD>
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<TD>mmcme2_adv_used=1</TD>
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</TR><TR ALIGN='LEFT'> <TD>muxf7_functional_category=MuxFx</TD>
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<TD>muxf7_used=3</TD>
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<TD>obuf_functional_category=IO</TD>
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<TD>obuf_used=43</TD>
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</TR><TR ALIGN='LEFT'> <TD>obuft_functional_category=IO</TD>
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<TD>obuft_used=2</TD>
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</TR> </TABLE>
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</TD></TR>
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<TR><TD>
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<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
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<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
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<TR ALIGN='LEFT'> <TD>f7_muxes_available=16300</TD>
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|
<TD>f7_muxes_fixed=0</TD>
|
|
<TD>f7_muxes_used=3</TD>
|
|
<TD>f7_muxes_util_percentage=0.02</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>f8_muxes_available=8150</TD>
|
|
<TD>f8_muxes_fixed=0</TD>
|
|
<TD>f8_muxes_used=0</TD>
|
|
<TD>f8_muxes_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=20800</TD>
|
|
<TD>lut_as_logic_fixed=0</TD>
|
|
<TD>lut_as_logic_used=564</TD>
|
|
<TD>lut_as_logic_util_percentage=2.71</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=9600</TD>
|
|
<TD>lut_as_memory_fixed=0</TD>
|
|
<TD>lut_as_memory_used=0</TD>
|
|
<TD>lut_as_memory_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>register_as_flip_flop_available=41600</TD>
|
|
<TD>register_as_flip_flop_fixed=0</TD>
|
|
<TD>register_as_flip_flop_used=578</TD>
|
|
<TD>register_as_flip_flop_util_percentage=1.39</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>register_as_latch_available=41600</TD>
|
|
<TD>register_as_latch_fixed=0</TD>
|
|
<TD>register_as_latch_used=0</TD>
|
|
<TD>register_as_latch_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>slice_luts_available=20800</TD>
|
|
<TD>slice_luts_fixed=0</TD>
|
|
<TD>slice_luts_used=564</TD>
|
|
<TD>slice_luts_util_percentage=2.71</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>slice_registers_available=41600</TD>
|
|
<TD>slice_registers_fixed=0</TD>
|
|
<TD>slice_registers_used=578</TD>
|
|
<TD>slice_registers_util_percentage=1.39</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>fully_used_lut_ff_pairs_fixed=1.39</TD>
|
|
<TD>fully_used_lut_ff_pairs_used=54</TD>
|
|
<TD>lut_as_distributed_ram_fixed=0</TD>
|
|
<TD>lut_as_distributed_ram_used=0</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=20800</TD>
|
|
<TD>lut_as_logic_fixed=0</TD>
|
|
<TD>lut_as_logic_used=564</TD>
|
|
<TD>lut_as_logic_util_percentage=2.71</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=9600</TD>
|
|
<TD>lut_as_memory_fixed=0</TD>
|
|
<TD>lut_as_memory_used=0</TD>
|
|
<TD>lut_as_memory_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>lut_as_shift_register_fixed=0</TD>
|
|
<TD>lut_as_shift_register_used=0</TD>
|
|
<TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=0</TD>
|
|
<TD>lut_ff_pairs_with_one_unused_flip_flop_used=111</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=111</TD>
|
|
<TD>lut_ff_pairs_with_one_unused_lut_output_used=110</TD>
|
|
<TD>lut_flip_flop_pairs_available=20800</TD>
|
|
<TD>lut_flip_flop_pairs_fixed=0</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>lut_flip_flop_pairs_used=171</TD>
|
|
<TD>lut_flip_flop_pairs_util_percentage=0.82</TD>
|
|
<TD>slice_available=8150</TD>
|
|
<TD>slice_fixed=0</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>slice_used=282</TD>
|
|
<TD>slice_util_percentage=3.46</TD>
|
|
<TD>slicel_fixed=0</TD>
|
|
<TD>slicel_used=182</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>slicem_fixed=0</TD>
|
|
<TD>slicem_used=100</TD>
|
|
<TD>unique_control_sets_used=36</TD>
|
|
<TD>using_o5_and_o6_fixed=36</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>using_o5_and_o6_used=131</TD>
|
|
<TD>using_o5_output_only_fixed=131</TD>
|
|
<TD>using_o5_output_only_used=0</TD>
|
|
<TD>using_o6_output_only_fixed=0</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>using_o6_output_only_used=433</TD>
|
|
</TR> </TABLE>
|
|
</TD></TR>
|
|
<TR><TD>
|
|
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
|
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
|
|
<TR ALIGN='LEFT'> <TD>bscane2_available=4</TD>
|
|
<TD>bscane2_fixed=0</TD>
|
|
<TD>bscane2_used=0</TD>
|
|
<TD>bscane2_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>capturee2_available=1</TD>
|
|
<TD>capturee2_fixed=0</TD>
|
|
<TD>capturee2_used=0</TD>
|
|
<TD>capturee2_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>dna_port_available=1</TD>
|
|
<TD>dna_port_fixed=0</TD>
|
|
<TD>dna_port_used=0</TD>
|
|
<TD>dna_port_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>efuse_usr_available=1</TD>
|
|
<TD>efuse_usr_fixed=0</TD>
|
|
<TD>efuse_usr_used=0</TD>
|
|
<TD>efuse_usr_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>frame_ecce2_available=1</TD>
|
|
<TD>frame_ecce2_fixed=0</TD>
|
|
<TD>frame_ecce2_used=0</TD>
|
|
<TD>frame_ecce2_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>icape2_available=2</TD>
|
|
<TD>icape2_fixed=0</TD>
|
|
<TD>icape2_used=0</TD>
|
|
<TD>icape2_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>pcie_2_1_available=1</TD>
|
|
<TD>pcie_2_1_fixed=0</TD>
|
|
<TD>pcie_2_1_used=0</TD>
|
|
<TD>pcie_2_1_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>startupe2_available=1</TD>
|
|
<TD>startupe2_fixed=0</TD>
|
|
<TD>startupe2_used=0</TD>
|
|
<TD>startupe2_util_percentage=0.00</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>xadc_available=1</TD>
|
|
<TD>xadc_fixed=0</TD>
|
|
<TD>xadc_used=0</TD>
|
|
<TD>xadc_util_percentage=0.00</TD>
|
|
</TR> </TABLE>
|
|
</TD></TR>
|
|
</TABLE><BR>
|
|
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
|
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
|
|
<TR><TD>
|
|
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
|
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
|
<TR ALIGN='LEFT'> <TD>actual_expansions=695075</TD>
|
|
<TD>bogomips=0</TD>
|
|
<TD>bram18=0</TD>
|
|
<TD>bram36=0</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>bufg=0</TD>
|
|
<TD>bufr=0</TD>
|
|
<TD>congestion_level=0</TD>
|
|
<TD>ctrls=36</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>dsp=0</TD>
|
|
<TD>effort=2</TD>
|
|
<TD>estimated_expansions=723384</TD>
|
|
<TD>ff=578</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>global_clocks=3</TD>
|
|
<TD>high_fanout_nets=0</TD>
|
|
<TD>iob=67</TD>
|
|
<TD>lut=609</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>movable_instances=1499</TD>
|
|
<TD>nets=1904</TD>
|
|
<TD>pins=8775</TD>
|
|
<TD>pll=0</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>router_runtime=0.000000</TD>
|
|
<TD>router_timing_driven=1</TD>
|
|
<TD>threads=2</TD>
|
|
<TD>timing_constraints_exist=1</TD>
|
|
</TR> </TABLE>
|
|
</TD></TR>
|
|
</TABLE><BR>
|
|
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
|
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
|
|
<TR><TD>
|
|
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
|
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
|
|
<TR ALIGN='LEFT'> <TD>-assert=default::[not_specified]</TD>
|
|
<TD>-bufg=default::12</TD>
|
|
<TD>-cascade_dsp=default::auto</TD>
|
|
<TD>-constrset=default::[not_specified]</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>-control_set_opt_threshold=default::auto</TD>
|
|
<TD>-directive=RuntimeOptimized</TD>
|
|
<TD>-fanout_limit=default::10000</TD>
|
|
<TD>-flatten_hierarchy=none</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>-fsm_extraction=off</TD>
|
|
<TD>-gated_clock_conversion=default::off</TD>
|
|
<TD>-generic=default::[not_specified]</TD>
|
|
<TD>-include_dirs=default::[not_specified]</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>-keep_equivalent_registers=default::[not_specified]</TD>
|
|
<TD>-max_bram=default::-1</TD>
|
|
<TD>-max_bram_cascade_height=default::-1</TD>
|
|
<TD>-max_dsp=default::-1</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>-max_uram=default::-1</TD>
|
|
<TD>-max_uram_cascade_height=default::-1</TD>
|
|
<TD>-mode=default::default</TD>
|
|
<TD>-name=default::[not_specified]</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>-no_lc=default::[not_specified]</TD>
|
|
<TD>-no_srlextract=default::[not_specified]</TD>
|
|
<TD>-no_timing_driven=default::[not_specified]</TD>
|
|
<TD>-part=xc7a35tcpg236-1</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>-resource_sharing=default::auto</TD>
|
|
<TD>-retiming=default::[not_specified]</TD>
|
|
<TD>-rtl=default::[not_specified]</TD>
|
|
<TD>-rtl_skip_constraints=default::[not_specified]</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>-rtl_skip_ip=default::[not_specified]</TD>
|
|
<TD>-seu_protect=default::none</TD>
|
|
<TD>-shreg_min_size=default::3</TD>
|
|
<TD>-top=GPIO_demo</TD>
|
|
</TR><TR ALIGN='LEFT'> <TD>-verilog_define=default::[not_specified]</TD>
|
|
</TR> </TABLE>
|
|
</TD></TR>
|
|
<TR><TD>
|
|
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
|
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
|
<TR ALIGN='LEFT'> <TD>elapsed=00:00:34s</TD>
|
|
<TD>hls_ip=0</TD>
|
|
<TD>memory_gain=424.176MB</TD>
|
|
<TD>memory_peak=692.656MB</TD>
|
|
</TR> </TABLE>
|
|
</TD></TR>
|
|
</TABLE><BR>
|
|
</BODY>
|
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</HTML>
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