Raphaël LACROIX
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f6a33bfaf0
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Merge remote-tracking branch 'origin/master'
# Conflicts:
# VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
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2023-05-29 23:49:23 +02:00 |
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Raphaël LACROIX
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c0b06b9565
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added hardcoded operations (from cross compiler) in the InstructionMemory.vhd
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2023-05-29 23:46:32 +02:00 |
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Raphaël LACROIX
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3885da0ea5
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added more operand (again)
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2023-05-29 23:45:26 +02:00 |
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Raphaël LACROIX
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8f5be60008
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updated opcodes
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2023-05-29 23:43:05 +02:00 |
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Lacroix Raphael
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c462cd7fe7
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WIP tried stuff
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2023-05-29 21:57:46 +02:00 |
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Lacroix Raphael
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12859bebe9
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Merge remote-tracking branch 'origin/master'
# Conflicts:
# VHDL/ALU/ALU.cache/wt/project.wpc
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.reloc
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb
# VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
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2023-05-29 21:42:46 +02:00 |
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alejeune
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134db4c2c9
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Update ALU
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2023-05-29 21:39:05 +02:00 |
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Lacroix Raphael
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474ba6b265
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added test files for full CPU
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2023-05-29 21:37:49 +02:00 |
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Raphaël LACROIX
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873502243b
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Merge remote-tracking branch 'origin/ALU'
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2023-05-29 20:33:37 +02:00 |
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alejeune
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6997cf24e8
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work in progress ALU
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2023-05-29 20:30:32 +02:00 |
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Raphaël LACROIX
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ae447be456
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added the alea handling and IP implementation
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2023-05-29 19:54:40 +02:00 |
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alejeune
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46465784b8
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added IP
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2023-05-29 14:28:17 +02:00 |
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alejeune
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22c945e716
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Added VHDL part of the project
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2023-05-29 13:58:26 +02:00 |
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