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pfaure:Compteur
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6 個提交
Compteur ... master

作者 SHA1 備註 日期
pfaure
805b597ab6 Fixing some warnings 2021-05-17 13:22:31 +02:00
pfaure
399492d9cf Nettoyage 2021-05-17 13:16:04 +02:00
pfaure
73a2d861b7 Processeur finito 2021-05-12 21:35:53 +02:00
pfaure
d1bbb37208 Processeur OK 22 Instructions, reste a sécuriser les accès mémoire avec des modulo 2021-05-08 23:09:39 +02:00
pfaure
4f64f6664a Suppression fichiers inutiles 2021-05-03 15:56:14 +02:00
pfaure
24bb67c7e3 Processeur 16 Instructions : NOP, ADD, SUB, MUL, DIV, INF, SUP, EQU, AFC, CPY, LOAD, JMP, JMZ, STORE, CALL, RET (ordre non garanti) 2021-05-03 15:54:29 +02:00
共有 123 個檔案被更改，包括 3091 行新增 和 10543 行删除
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12
.gitignore vendored
查看文件

@ -1,5 +1,7 @@
Compteur8BitsBasys3.ip_user_files/*
Compteur8BitsBasys3.cache/*
Compteur8BitsBasys3.hw/*
Compteur8BitsBasys3.runs/*
Compteur8BitsBasys3.sim/*
Processeur.ip_user_files/*
Processeur.cache/*
Processeur.hw/*
Processeur.runs/*
Processeur.sim/*
vivado*
.Xil

64
Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd
查看文件

@ -1,64 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.04.2021 21:20:39
-- Design Name:
-- Module Name: Compteur - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Compteur is
Port ( CK : in STD_LOGIC;
RST : in STD_LOGIC;
SENS : in STD_LOGIC;
LOAD : in STD_LOGIC;
EN : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (7 downto 0);
Dout : out STD_LOGIC_VECTOR (7 downto 0));
end Compteur;
architecture Behavioral of Compteur is
signal aux: STD_LOGIC_VECTOR (7 downto 0);
begin
Dout <= aux;
process
begin
wait until CK'event and CK='1';
if RST = '0' then
aux <= (others => '0');
elsif LOAD = '1' then
aux <= Din;
elsif EN = '0' then
if SENS = '1' then
aux <= aux + 1;
else
aux <= aux - 1;
end if;
end if;
end process;
end Behavioral;

66
Compteur8BitsBasys3.srcs/sources_1/new/System.vhd
查看文件

@ -1,66 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.04.2021 22:03:10
-- Design Name:
-- Module Name: System - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity System is
Port ( SW : in STD_LOGIC_VECTOR (0 to 7);
btnL : in STD_LOGIC;
btnC : in STD_LOGIC;
btnR : in STD_LOGIC;
btnD : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (0 to 7);
CLK : in STD_LOGIC);
end System;
architecture Structural of System is
component ClockDivider1000
Port ( clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC);
end component;
component Compteur
Port ( CK : in STD_LOGIC;
RST : in STD_LOGIC;
SENS : in STD_LOGIC;
LOAD : in STD_LOGIC;
EN : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (7 downto 0);
Dout : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal CLK_DIV_1000, CLK_DIV_1000000 : STD_LOGIC;
begin
DIV1: ClockDivider1000 port map(CLK, CLK_DIV_1000);
DIV2: ClockDivider1000 port map(CLK_DIV_1000, CLK_DIV_1000000);
CMPT: Compteur port map(CLK_DIV_1000000, btnC, btnR, btnL, btnD, SW, LED);
end Structural;

159
Compteur8BitsBasys3.xpr
查看文件

@ -1,159 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2016.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="b3843060a8224f8699d89033689dec00"/>
<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="SimulatorLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PPRDIR/Compteur8BitsBasys3.ip_user_files"/>
<Option Name="IPStaticSourceDir" Val="$PPRDIR/Compteur8BitsBasys3.ip_user_files/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="64"/>
<Option Name="XSimTraceLimit" Val="65536"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ClockDivider10.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ClockDivider1000.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/System.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="System"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../../../Xilinx/digilent-xdc-master/Basys-3-Master.xdc"/>
<Attr Name="ImportTime" Val="1614979917"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="System"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SimMode" Val="post-implementation"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
</Project>

96
Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc → Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
查看文件

@ -9,22 +9,22 @@ set_property IOSTANDARD LVCMOS33 [get_ports CLK]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
## Switches
set_property PACKAGE_PIN V17 [get_ports {SW[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
set_property PACKAGE_PIN V16 [get_ports {SW[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
set_property PACKAGE_PIN W16 [get_ports {SW[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
set_property PACKAGE_PIN W17 [get_ports {SW[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
set_property PACKAGE_PIN W15 [get_ports {SW[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[4]}]
set_property PACKAGE_PIN V15 [get_ports {SW[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[5]}]
set_property PACKAGE_PIN W14 [get_ports {SW[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[6]}]
set_property PACKAGE_PIN W13 [get_ports {SW[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[7]}]
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
@ -44,22 +44,22 @@ set_property IOSTANDARD LVCMOS33 [get_ports {SW[7]}]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
@ -68,14 +68,14 @@ set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
#set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {flag[0]}]
#set_property PACKAGE_PIN N3 [get_ports {flag[1]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {flag[1]}]
#set_property PACKAGE_PIN P1 [get_ports {flag[2]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {flag[2]}]
#set_property PACKAGE_PIN L1 [get_ports {flag[3]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {flag[3]}]
##7 segment display
@ -110,14 +110,14 @@ set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
##Buttons
set_property PACKAGE_PIN U18 [get_ports btnC]
set_property IOSTANDARD LVCMOS33 [get_ports btnC]
#set_property PACKAGE_PIN T18 [get_ports btnU]
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
set_property PACKAGE_PIN W19 [get_ports btnL]
set_property IOSTANDARD LVCMOS33 [get_ports btnL]
set_property PACKAGE_PIN T17 [get_ports btnR]
set_property IOSTANDARD LVCMOS33 [get_ports btnR]
set_property PACKAGE_PIN U17 [get_ports btnD]
set_property IOSTANDARD LVCMOS33 [get_ports btnD]
##set_property PACKAGE_PIN T18 [get_ports btnU]
# #set_property IOSTANDARD LVCMOS33 [get_ports btnU]
#set_property PACKAGE_PIN W19 [get_ports btnL]
# set_property IOSTANDARD LVCMOS33 [get_ports btnL]
#set_property PACKAGE_PIN T17 [get_ports btnR]
# set_property IOSTANDARD LVCMOS33 [get_ports btnR]
#set_property PACKAGE_PIN U17 [get_ports btnD]
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]

84
Processeur.srcs/sim_1/new/TestALU.vhd 一般檔案
查看文件

@ -0,0 +1,84 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16.04.2021 21:25:53
-- Design Name:
-- Module Name: TestALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestALU is
-- Port ( );
end TestALU;
architecture Behavioral of TestALU is
component ALU is
Generic (Nb_bits : Natural);
Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
OP : in STD_LOGIC_VECTOR (1 downto 0);
S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC);
end component;
signal my_A : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal my_B : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal my_OP : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
signal my_S : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal my_N : STD_LOGIC := '0';
signal my_O : STD_LOGIC := '0';
signal my_Z : STD_LOGIC := '0';
signal my_C : STD_LOGIC := '0';
begin
instance : ALU
generic map (Nb_bits => 16)
port map (
A => my_A,
B => my_B,
OP => my_OP,
S => my_S,
N => my_N,
O => my_O,
Z => my_Z,
C => my_C
);
process
begin
my_A <= x"0007" after 10 ns, x"00ff" after 100 ns;
my_B <= x"0008" after 10 ns, x"ff01" after 100 ns;
my_OP <= "01" after 10 ns, "10" after 30 ns, "11" after 50 ns, "01" after 67 ns, "00" after 100 ns;
wait;
end process;
end Behavioral;

104
Processeur.srcs/sim_1/new/TestBancRegistres.vhd 一般檔案
查看文件

@ -0,0 +1,104 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16.04.2021 12:58:02
-- Design Name:
-- Module Name: TestBancRegistres - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestBancRegistres is
-- Port ( );
end TestBancRegistres;
architecture Behavioral of TestBancRegistres is
component BancRegistres
Generic (Nb_bits : Natural;
Addr_size : Natural;
Nb_regs : Natural);
Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
W : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
end component;
signal my_AddrA : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
signal my_AddrB : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
signal my_AddrW : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
signal my_W : STD_LOGIC := '0';
signal my_DATA : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_RST : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
signal my_QA : STD_LOGIC_VECTOR (7 downto 0);
signal my_QB : STD_LOGIC_VECTOR (7 downto 0);
constant CLK_period : time := 10 ns;
begin
instance : BancRegistres
generic map (Nb_bits => 8,
Addr_size => 2,
Nb_regs => 4
)
port map (
AddrA => my_AddrA,
AddrB => my_AddrB,
AddrW => my_AddrW,
W => my_W,
DATA => my_DATA,
RST => my_RST,
CLK => my_CLK,
QA => my_QA,
QB => my_QB
);
CLK_process :process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
my_RST <= '1' after 0 ns, '0' after 100 ns;
my_AddrA <= "11" after 20 ns, "00" after 50 ns;
my_AddrB <= "11" after 30 ns;
my_AddrW <= "11" after 10 ns, "00" after 50 ns;
my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 60 ns, '1' after 110 ns;
my_DATA <= "01010101" after 10 ns, "11111111" after 50 ns;
wait;
end process;
end Behavioral;

99
Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd 一般檔案
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16.04.2021 12:58:02
-- Design Name:
-- Module Name: TestMemoireAdressesRetour - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestMemoireAdressesRetour is
-- Port ( );
end TestMemoireAdressesRetour;
architecture Behavioral of TestMemoireAdressesRetour is
component MemoireAdressesRetour is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
E : out STD_LOGIC;
F : out STD_LOGIC);
end component;
signal my_R : STD_LOGIC := '0';
signal my_W : STD_LOGIC := '0';
signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_RST : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
signal my_E : STD_LOGIC;
signal my_F : STD_LOGIC;
constant CLK_period : time := 10 ns;
begin
instance : MemoireAdressesRetour
generic map (Nb_bits => 8,
Addr_size => 2,
Mem_size => 4
)
port map (
R => my_R,
W => my_W,
D_IN => my_D_IN,
RST => my_RST,
CLK => my_CLK,
D_OUT => my_D_OUT,
E => my_E,
F => my_F
);
CLK_process :process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
my_RST <= '1' after 0 ns, '0' after 100 ns;
my_R <= '1' after 20 ns, '0' after 30 ns;
my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 90 ns, '0' after 110 ns;
my_D_IN <= "01010101" after 10 ns, "11100111" after 30 ns, "11111111" after 50 ns, "11111110" after 60 ns, "11111101" after 70 ns, "11111100" after 80 ns;
wait;
end process;
end Behavioral;

93
Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd 一般檔案
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16.04.2021 12:58:02
-- Design Name:
-- Module Name: TestMemoireDonnees - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestMemoireDonnees is
-- Port ( );
end TestMemoireDonnees;
architecture Behavioral of TestMemoireDonnees is
component MemoireDonnees is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
RW : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
end component;
signal my_Addr : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
signal my_RW : STD_LOGIC := '1';
signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_RST : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
constant CLK_period : time := 10 ns;
begin
instance : MemoireDonnees
generic map (Nb_bits => 8,
Addr_size => 2,
Mem_size => 4
)
port map (
Addr => my_Addr,
RW => my_RW,
D_IN => my_D_IN,
RST => my_RST,
CLK => my_CLK,
D_OUT => my_D_OUT
);
CLK_process :process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
my_RST <= '1' after 0 ns, '0' after 100 ns;
my_RW <= '1' after 0 ns, '0' after 10 ns, '1' after 30 ns;
my_Addr <= "01" after 10 ns, "10" after 20 ns, "11" after 40 ns, "01" after 70 ns;
my_D_IN <= "01010101" after 10 ns, "11100111" after 20 ns, "11111111" after 50 ns;
wait;
end process;
end Behavioral;

67
Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd 一般檔案
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16.04.2021 12:58:02
-- Design Name:
-- Module Name: TestMemoireInstructions - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestMemoireInstructions is
-- Port ( );
end TestMemoireInstructions;
architecture Behavioral of TestMemoireInstructions is
component MemoireInstructions is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
end component;
signal my_Addr : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_D_OUT : STD_LOGIC_VECTOR (27 downto 0);
begin
instance : MemoireInstructions
generic map (Nb_bits => 28,
Addr_size => 4,
Mem_size => 16
)
port map (
Addr => my_Addr,
D_OUT => my_D_OUT
);
process
begin
my_Addr <= "0001" after 10 ns, "0010" after 20 ns, "0011" after 30 ns;
wait;
end process;
end Behavioral;

121
Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd 一般檔案
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.04.2021 14:31:37
-- Design Name:
-- Module Name: Test_Etage2_5_Registres - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Etage2_5_Registres is
-- Port ( );
end Test_Etage2_5_Registres;
architecture Behavioral of Test_Etage2_5_Registres is
component Etage2_5_Registres is
Generic ( Nb_bits : Natural;
Nb_registres : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end component;
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
signal my_IN_2_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_2_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_2_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_2_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal my_OUT_2_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_2_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_2_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_2_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal my_IN_5_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_5_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_5_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (7 downto 0) := "01111110";
constant Bits_Controle_MUX_2 : STD_LOGIC_VECTOR (7 downto 0) := "01100001";
constant CLK_period : time := 10 ns;
begin
instance : Etage2_5_Registres
generic map( Nb_bits => 8,
Nb_Registres => 16,
Instruction_bus_size => 3,
Bits_Controle_LC_5 => Bits_Controle_LC_5,
Bits_Controle_MUX_2 => Bits_Controle_MUX_2)
port map( CLK => my_CLK,
RST => my_RST,
IN_2_A => my_IN_2_A,
IN_2_B => my_IN_2_B,
IN_2_C => my_IN_2_C,
IN_2_Instruction => my_IN_2_Instruction,
OUT_2_A => my_OUT_2_A,
OUT_2_B => my_OUT_2_B,
OUT_2_C => my_OUT_2_C,
OUT_2_Instruction => my_OUT_2_Instruction,
IN_5_A => my_IN_5_A,
IN_5_B => my_IN_5_B,
IN_5_Instruction => my_IN_5_Instruction);
CLK_process :process
begin
my_CLK <= '1';
wait for CLK_period/2;
my_CLK <= '0';
wait for CLK_period/2;
end process;
process
begin
my_RST <= '0' after 33 ns;
my_IN_2_A <= "01011111" after 0 ns;
my_IN_2_B <= "00000011" after 0 ns, "00000100" after 40 ns;
my_IN_2_C <= "00000001" after 0 ns, "00000000" after 40 ns;
my_IN_2_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
my_IN_5_A <= "00000010" after 0 ns, "00000000" after 10 ns, "00000011" after 20 ns, "00000010" after 30 ns;
my_IN_5_B <= "11111111" after 0 ns, "11111110" after 10 ns, "11111101" after 20 ns, "11111100" after 30 ns;
my_IN_5_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
wait;
end process;
end Behavioral;

105
Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd 一般檔案
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.04.2021 11:26:48
-- Design Name:
-- Module Name: Test_Etage3_Calcul - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Etage3_Calcul is
-- Port ( );
end Test_Etage3_Calcul;
architecture Behavioral of Test_Etage3_Calcul is
component Etage3_Calcul is
Generic ( Nb_bits : Natural;
OP_vector_size : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX : STD_LOGIC_VECTOR);
Port ( RST : STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC);
end component;
signal my_RST : STD_LOGIC := '1';
signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal my_N : STD_LOGIC;
signal my_O : STD_LOGIC;
signal my_Z : STD_LOGIC;
signal my_C : STD_LOGIC;
constant Bits_Controle_LC : STD_LOGIC_VECTOR (15 downto 0) := x"00b4";
constant Bits_Controle_MUX : STD_LOGIC_VECTOR (7 downto 0) := "11110001";
begin
instance : Etage3_Calcul
generic map( Nb_bits => 8,
OP_vector_size => 2,
Instruction_bus_size => 3,
Bits_Controle_LC => Bits_Controle_LC,
Bits_Controle_MUX => Bits_Controle_MUX)
port map( RST => my_RST,
IN_A => my_IN_A,
IN_B => my_IN_B,
IN_C => my_IN_C,
IN_Instruction => my_IN_Instruction,
OUT_A => my_OUT_A,
OUT_B => my_OUT_B,
OUT_Instruction => my_OUT_Instruction,
N => my_N,
O => my_O,
Z => my_Z,
C => my_C);
process
begin
my_IN_A <= "01011111";
my_IN_B <= "10100110";
my_IN_C <= "01101101";
my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
my_RST <= '0' after 45 ns;
wait;
end process;
end Behavioral;

105
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd 一般檔案
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.04.2021 13:37:04
-- Design Name:
-- Module Name: Test_Etage4_Memoire - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Etage4_Memoire is
-- Port ( );
end Test_Etage4_Memoire;
architecture Behavioral of Test_Etage4_Memoire is
component Etage4_Memoire is
Generic ( Nb_bits : Natural;
Mem_size : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end component;
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
constant Bits_Controle_LC : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (7 downto 0) := "10111111";
constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant CLK_period : time := 10 ns;
begin
instance : Etage4_Memoire
generic map( Nb_bits => 8,
Mem_size => 256,
Instruction_bus_size => 3,
Bits_Controle_LC => Bits_Controle_LC,
Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT)
port map( CLK => my_CLK,
RST => my_RST,
IN_A => my_IN_A,
IN_B => my_IN_B,
IN_Instruction => my_IN_Instruction,
OUT_A => my_OUT_A,
OUT_B => my_OUT_B,
OUT_Instruction => my_OUT_Instruction);
CLK_process :process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
my_IN_A <= "01011111" after 0 ns, "11111111" after 124 ns;
my_IN_B <= "10100110" after 0 ns, "01011111" after 124 ns;
my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns, "110" after 100 ns, "111" after 110 ns, "110" after 120 ns;
my_RST <= '0' after 125 ns;
wait;
end process;
end Behavioral;

118
Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd 一般檔案
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18.04.2021 22:28:40
-- Design Name:
-- Module Name: Test_Etape1_LectureInstruction - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Etape1_LectureInstruction is
-- Port ( );
end Test_Etape1_LectureInstruction;
architecture Behavioral of Test_Etape1_LectureInstruction is
component Etage1_LectureInstruction is
Generic (Instruction_size_in_memory : Natural;
Addr_size_mem_instruction : Natural;
Mem_instruction_size : Natural;
Nb_bits : Natural;
Instruction_bus_size : Natural;
Nb_registres : Natural;
Mem_adresse_retour_size : Natural;
Adresse_size_mem_adresse_retour : Natural;
Instructions_critiques_lecture : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
Code_Instruction_JMP : STD_LOGIC_VECTOR;
Code_Instruction_JMZ : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Z : in STD_LOGIC;
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end component;
signal my_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
signal my_Z : STD_LOGIC := '1';
constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (15 downto 0) := "0000100111111110";
constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (15 downto 0) := "0000000011111110";
constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (15 downto 0) := "0000011111111110";
constant CLK_period : time := 10 ns;
begin
instance : Etage1_LectureInstruction
generic map (Instruction_size_in_memory => 28,
Addr_size_mem_instruction => 4,
Mem_instruction_size => 16,
Nb_bits => 8,
Instruction_bus_size => 4,
Nb_registres => 16,
Mem_adresse_retour_size => 4,
Adresse_size_mem_adresse_retour => 2,
Instructions_critiques_lecture => Instructions_critiques_lecture,
Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
Instructions_critiques_ecriture => Instructions_critiques_ecriture,
Code_Instruction_JMP => "1100",
Code_Instruction_JMZ => "1101",
Code_Instruction_CALL => "1110",
Code_Instruction_RET => "1111"
)
port map (
CLK => my_CLK,
RST => my_RST,
z => my_Z,
A => my_A,
B => my_B,
C => my_C,
Instruction => my_Instruction
);
CLK_process :process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
wait;
end process;
end Behavioral;

66
Processeur.srcs/sim_1/new/Test_LC.vhd 一般檔案
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@ -0,0 +1,66 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17.04.2021 22:43:43
-- Design Name:
-- Module Name: Test_LC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_LC is
-- Port ( );
end Test_LC;
architecture Behavioral of Test_LC is
component LC is
Generic (Instruction_Vector_Size : Natural;
Command_size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
end component;
signal my_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal my_Commande : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
constant Bits_Controle : STD_LOGIC_VECTOR (15 downto 0) := x"c138";
begin
instance : LC
generic map (Instruction_Vector_Size => 3,
Command_size => 2,
Bits_Controle => Bits_Controle)
port map (
Instruction => my_Instruction,
Commande => my_Commande
);
process
begin
my_Instruction <= "000" after 1 ns, "001" after 2 ns, "010" after 3 ns, "011" after 4 ns, "100" after 5 ns, "101" after 6 ns, "110" after 7 ns, "111" after 8 ns;
wait;
end process;
end Behavioral;

74
Processeur.srcs/sim_1/new/Test_MUX.vhd 一般檔案
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@ -0,0 +1,74 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17.04.2021 22:43:43
-- Design Name:
-- Module Name: Test_MUX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_MUX is
-- Port ( );
end Test_MUX;
architecture Behavioral of Test_MUX is
component MUX is
Generic (Nb_bits : Natural;
Instruction_Vector_Size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_IN1 : STD_LOGIC_VECTOR (15 downto 0);
signal my_IN2 : STD_LOGIC_VECTOR (15 downto 0);
signal my_OUTPUT : STD_LOGIC_VECTOR (15 downto 0);
begin
instance : MUX
generic map (Nb_bits => 16,
Instruction_Vector_Size => 4,
Bits_Controle => x"aaaa")
port map (
Instruction => my_Instruction,
IN1 => my_IN1,
IN2 => my_IN2,
OUTPUT => my_OUTPUT
);
process
begin
my_IN1 <= x"abcd";
my_IN2 <= x"1234";
my_Instruction <= "0000" after 1 ns, "0001" after 2 ns, "0010" after 3 ns, "0011" after 4 ns, "0100" after 5 ns, "0101" after 6 ns, "0110" after 7 ns, "0111" after 8 ns;
wait;
end process;
end Behavioral;

85
Processeur.srcs/sim_1/new/Test_Pipeline.vhd 一般檔案
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@ -0,0 +1,85 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.04.2021 17:35:57
-- Design Name:
-- Module Name: Test_Pipeline - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Pipeline is
-- Port ( );
end Test_Pipeline;
architecture Behavioral of Test_Pipeline is
component Pipeline is
Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3;
Memoire_Instruction_Size : Natural := 8;
Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16;
Memoire_Size : Natural := 32;
Memoire_Adresses_Retour_Size : Natural := 16;
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
Port (CLK : STD_LOGIC;
RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
signal my_STD_IN : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
signal my_STD_OUT : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
constant CLK_period : time := 10 ns;
begin
instance : Pipeline
generic map (Addr_Memoire_Instruction_Size => 7,
Memoire_Instruction_Size => 128)
port map (CLK => my_CLK,
RST => my_RST,
STD_IN => my_STD_IN,
STD_OUT => my_STD_OUT);
CLK_process :process
begin
my_CLK <= '1';
wait for CLK_period/2;
my_CLK <= '0';
wait for CLK_period/2;
end process;
process
begin
wait;
end process;
end Behavioral;

85
Processeur.srcs/sources_1/new/ALU.vhd 一般檔案
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@ -0,0 +1,85 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.04.2021 10:07:41
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Generic (Nb_bits : Natural);
Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC);
end ALU;
architecture Behavioral of ALU is
signal A9 : STD_LOGIC_VECTOR (Nb_bits downto 0);
signal B9 : STD_LOGIC_VECTOR (Nb_bits downto 0);
signal ADD : STD_LOGIC_VECTOR (Nb_bits downto 0);
signal SUB : STD_LOGIC_VECTOR (Nb_bits downto 0);
signal MUL : STD_LOGIC_VECTOR ((2*Nb_bits)-1 downto 0);
signal intern_N : STD_LOGIC;
signal intern_Z : STD_LOGIC;
constant ZERO_N : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
constant ZERO_N1 : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
begin
A9 <= '0' & A;
B9 <= '0' & B;
ADD <= A9 + B9;
SUB <= A9 - B9;
MUL <= A * B;
S <= ADD (Nb_bits-1 downto 0) when OP = "001" else
SUB (Nb_bits-1 downto 0) when OP = "010" else
MUL (Nb_bits-1 downto 0) when OP = "011" else
-- Add division
(0 => intern_N, others => '0') when OP = "101" else
(0 => '1', others => '0') when OP = "110" and intern_Z = '0' and intern_N = '0' else
(0 => intern_Z, others => '0') when OP = "111" else
(others => '0');
intern_N <= SUB (Nb_bits);
intern_Z <= '1' when (SUB = ZERO_N1) else
'0';
N <= intern_N;
O <= '0' when (MUL ((2*Nb_bits)-1 downto Nb_bits) = ZERO_N) else
'1';
Z <= intern_Z;
C <= ADD (Nb_bits);
end Behavioral;

71
Processeur.srcs/sources_1/new/BancRegistres.vhd 一般檔案
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@ -0,0 +1,71 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15.04.2021 08:23:48
-- Design Name:
-- Module Name: BancRegistres - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BancRegistres is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Nb_regs : Natural);
Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrC : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
W : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
QC : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
end BancRegistres;
-- ASK MEILLEURE IDEE UN TABLEAU
architecture Behavioral of BancRegistres is
signal REGISTRES : STD_LOGIC_VECTOR ((Nb_regs * Nb_bits)-1 downto 0) := (others => '0');
begin
process
begin
wait until CLK'event and CLK = '1';
if (RST = '0') then
REGISTRES <= (others => '0');
else
if (W = '1') then
REGISTRES (((to_integer(unsigned(AddrW)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(AddrW))) <= DATA;
end if;
end if;
end process;
QA <= REGISTRES (((to_integer(unsigned(AddrA)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrA)));
QB <= REGISTRES (((to_integer(unsigned(AddrB)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrB)));
QC <= REGISTRES (((to_integer(unsigned(AddrC)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrC)));
end Behavioral;

31
Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider10.vhd → Processeur.srcs/sources_1/new/Clock_Divider.vhd
查看文件

@ -2,9 +2,9 @@
-- Company:
-- Engineer:
--
-- Create Date: 09.04.2021 21:42:26
-- Create Date: 08.05.2021 21:00:25
-- Design Name:
-- Module Name: ClockDivider10 - Behavioral
-- Module Name: Clock_Divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
@ -31,24 +31,27 @@ use IEEE.STD_LOGIC_1164.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity ClockDivider10 is
Port ( clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC);
end ClockDivider10;
entity Clock_Divider is
Port ( CLK_IN : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end Clock_Divider;
architecture Behavioral of ClockDivider10 is
subtype int10 is INTEGER range 0 to 10;
signal N : int10 := 0;
signal aux : STD_LOGIC;
architecture Behavioral of Clock_Divider is
signal N : Integer := 0;
signal CLK : STD_LOGIC := '1';
begin
process
begin
wait until clk_in'event and clk_in = '1';
wait until CLK_IN'event and CLK_IN = '1';
N <= N + 1;
if N = 10 then
aux <= not aux;
if (N = 1000) then
N <= 0;
if (CLK = '1') then
CLK <= '0';
else
CLK <= '1';
end if;
end if;
end process;
clk_out <= aux;
CLK_OUT <= CLK;
end Behavioral;

259
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd 一般檔案
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@ -0,0 +1,259 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18.04.2021 21:19:41
-- Design Name:
-- Module Name: Etage1_LectureInstruction - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Etage1_LectureInstruction is
Generic (Instruction_size_in_memory : Natural;
Addr_size_mem_instruction : Natural;
Mem_instruction_size : Natural;
Nb_bits : Natural;
Instruction_bus_size : Natural;
Nb_registres : Natural;
Mem_adresse_retour_size : Natural;
Adresse_size_mem_adresse_retour : Natural;
Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
Code_Instruction_JMP : STD_LOGIC_VECTOR;
Code_Instruction_JMZ : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR;
Code_Instruction_STOP : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Z : in STD_LOGIC;
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end Etage1_LectureInstruction;
architecture Behavioral of Etage1_LectureInstruction is
component MemoireInstructions is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
end component;
component MemoireAdressesRetour is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
E : out STD_LOGIC;
F : out STD_LOGIC);
end component;
signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0');
signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
subtype Registre is integer range -1 to Nb_registres - 1;
type Tab_registres is array (1 to 3) of Registre;
signal Tableau : Tab_registres := (others => - 1);
signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
signal E : STD_LOGIC;
signal F : STD_LOGIC;
signal R_Aux : STD_LOGIC := '0';
signal W_Aux : STD_LOGIC := '0';
constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0');
constant Argument_nul : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal bulles : boolean := false;
signal compteur : integer := 0;
signal locked : boolean := false;
begin
instance : MemoireInstructions
generic map (Nb_bits => Instruction_size_in_memory,
Addr_size => Addr_size_mem_instruction,
Mem_size => Mem_instruction_size)
port map (Addr => Pointeur_Instruction,
D_OUT => Instruction_courante);
instance_MemoireAdressesRetour : MemoireAdressesRetour
generic map (Nb_bits => Addr_size_mem_instruction,
Addr_size => Adresse_size_mem_adresse_retour,
Mem_size => Mem_adresse_retour_size
)
port map ( R => R_Aux,
W => W_Aux,
D_IN => Pointeur_instruction_next,
RST => RST,
CLK => CLK,
D_OUT => Adresse_Retour,
E => E,
F => F
);
process
begin
wait until CLK'event and CLK = '1';
if (RST = '0') then
Tableau <= (others => -1);
Pointeur_Instruction <= (others => '0');
compteur <= 0;
locked <= false;
C <= Argument_nul;
B <= Argument_nul;
A <= Argument_nul;
Instruction <= Instruction_nulle;
else
Tableau(3) <= Tableau(2);
Tableau(2) <= Tableau(1);
Tableau(1) <= -1;
if (not bulles) then
if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
Pointeur_Instruction <= Adresse_Retour;
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
compteur <= compteur + 1;
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
if (compteur = 2) then
if (Z = '1') then
Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
else
Pointeur_Instruction <= Pointeur_Instruction + 1;
end if;
compteur <= 0;
end if;
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_STOP) then
if (not locked) then
if (Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits) = Argument_nul) then
locked <= true;
end if;
compteur <= compteur + 1;
if (compteur + 1 = to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)))) then
Pointeur_Instruction <= Pointeur_Instruction + 1;
compteur <= 0;
end if;
end if;
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
else
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
if (Instructions_critiques_ecriture(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') then
Tableau(1) <= to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)));
end if;
Pointeur_Instruction <= Pointeur_Instruction + 1;
end if;
else
C <= Argument_nul;
B <= Argument_nul;
A <= Argument_nul;
Instruction <= Instruction_nulle;
end if;
end if;
end process;
-- Condition degueu -> Instruction critique en lecture simple qui lit dans B et B dans tableau ou instruction critique en lecture double qui lit dans C et C dans tableau
bulles <=
(
(
Instructions_critiques_lecture_A(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
)
and
(
(to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(1))
or
(to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(2))
or
(to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(3))
)
)
or
(
(
Instructions_critiques_lecture_B(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
)
and
(
(to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(1))
or
(to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(2))
or
(to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(3))
)
)
or
(
(
Instructions_critiques_lecture_C(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
)
and
(
(to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(1))
or
(to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(2))
or
(to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))
)
);
R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
'0';
W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else
'0';
Pointeur_instruction_next <= Pointeur_instruction + 1;
end Behavioral;

176
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd 一般檔案
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18.04.2021 21:19:41
-- Design Name:
-- Module Name: Etage2_5_Registres - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Etage2_5_Registres is
Generic ( Nb_bits : Natural;
Nb_registres : Natural;
Addr_registres_size : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
Code_Instruction_PRI : STD_LOGIC_VECTOR;
Code_Instruction_GET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end Etage2_5_Registres;
architecture Behavioral of Etage2_5_Registres is
component BancRegistres is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Nb_regs : Natural);
Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrC : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
W : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
QC : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
end component;
component LC is
Generic (Instruction_Vector_Size : Natural;
Command_size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
end component;
component MUX is
Generic (Nb_bits : Natural;
Instruction_Vector_Size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
signal Commande_BancRegistres : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal Entree_BancRegistre_DATA : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal Sortie_BancRegistres_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal Sortie_BancRegistres_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_2_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_STD_OUT : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
begin
instance_LC : LC
generic map (Instruction_Vector_Size => Instruction_bus_size,
Command_size => 1,
Bits_Controle => Bits_Controle_LC_5)
port map ( Instruction => IN_5_Instruction,
Commande => Commande_BancRegistres);
instance_MUX_A : MUX
generic map (Nb_bits => Nb_bits,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_2_A)
port map ( Instruction => IN_2_Instruction,
IN1 => IN_2_A,
IN2 => Sortie_BancRegistres_A,
OUTPUT => intern_OUT_2_A);
instance_MUX_B : MUX
generic map (Nb_bits => Nb_bits,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_2_B)
port map ( Instruction => IN_2_Instruction,
IN1 => IN_2_B,
IN2 => Sortie_BancRegistres_B,
OUTPUT => intern_OUT_2_B);
instance_BancRegistres : BancRegistres
generic map (Nb_bits => Nb_bits,
Addr_size => Addr_registres_size,
Nb_regs => Nb_registres)
port map ( AddrA => IN_2_A(Addr_registres_size - 1 downto 0),
AddrB => IN_2_B(Addr_registres_size - 1 downto 0),
AddrC => IN_2_C(Addr_registres_size - 1 downto 0),
AddrW => IN_5_A(Addr_registres_size - 1 downto 0),
W => Commande_BancRegistres(0),
DATA => Entree_BancRegistre_DATA,
RST => RST,
CLK => CLK,
QA => Sortie_BancRegistres_A,
QB => Sortie_BancRegistres_B,
QC => intern_OUT_2_C);
OUT_2_A <= (others => '0') when RST = '0' else
intern_OUT_2_A;
OUT_2_B <= (others => '0') when RST = '0' else
intern_OUT_2_B;
OUT_2_C <= (others => '0') when RST = '0' else
intern_OUT_2_C;
OUT_2_Instruction <= (others => '0') when RST = '0' else
IN_2_Instruction;
process
begin
wait until CLK'event and CLK = '1';
if (RST = '0') then
intern_STD_OUT <= (others => '0');
else
if (IN_2_Instruction = Code_Instruction_PRI) then
intern_STD_OUT <= intern_OUT_2_A;
end if;
end if;
end process;
STD_OUT <= intern_STD_OUT when RST = '1' else
(others => '0');
Entree_BancRegistre_DATA <= (others => '0') when RST = '0' else
STD_IN when IN_2_Instruction = Code_Instruction_GET else
IN_5_B;
end Behavioral;

136
Processeur.srcs/sources_1/new/Etage3_Calcul.vhd 一般檔案
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18.04.2021 21:19:41
-- Design Name:
-- Module Name: Etage3_Calcul - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Etage3_Calcul is
Generic ( Nb_bits : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX : STD_LOGIC_VECTOR);
Port ( RST : in STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC);
end Etage3_Calcul;
architecture Structural of Etage3_Calcul is
component ALU is
Generic (Nb_bits : Natural);
Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC);
end component;
component LC is
Generic (Instruction_Vector_Size : Natural;
Command_size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
end component;
component MUX is
Generic (Nb_bits : Natural;
Instruction_Vector_Size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
signal OP_ALU : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal Sortie_ALU : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_N : STD_LOGIC := '0';
signal intern_O : STD_LOGIC := '0';
signal intern_Z : STD_LOGIC := '0';
signal intern_C : STD_LOGIC := '0';
begin
instance_LC : LC
generic map (Instruction_Vector_Size => Instruction_bus_size,
Command_size => 3,
Bits_Controle => Bits_Controle_LC)
port map ( Instruction => IN_Instruction,
Commande => OP_ALU);
instance_MUX : MUX
generic map (Nb_bits => Nb_bits,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX)
port map ( Instruction => IN_Instruction,
IN1 => IN_B,
IN2 => Sortie_ALU,
OUTPUT => intern_OUT_B);
instance_ALU : ALU
generic map (Nb_bits => Nb_bits)
port map (A => IN_B,
B => IN_C,
OP => OP_ALU,
S => Sortie_ALU,
N => intern_N,
O => intern_O,
Z => intern_Z,
C => intern_C);
OUT_A <= (others => '0') when RST = '0' else
IN_A;
OUT_B <= (others => '0') when RST = '0' else
intern_OUT_B;
OUT_Instruction <= (others => '0') when RST = '0' else
IN_Instruction;
N <= '0' when RST = '0' else
intern_N;
O <= '0' when RST = '0' else
intern_O;
Z <= '0' when RST = '0' else
intern_Z;
C <= '0' when RST = '0' else
intern_C;
end Structural;

193
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd 一般檔案
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@ -0,0 +1,193 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18.04.2021 21:19:41
-- Design Name:
-- Module Name: Etage4_Memoire - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Etage4_Memoire is
Generic ( Nb_bits : Natural;
Mem_size : Natural;
Adresse_mem_size : Natural;
Instruction_bus_size : Natural;
Mem_EBP_size : Natural;
Adresse_size_mem_EBP : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end Etage4_Memoire;
architecture Structural of Etage4_Memoire is
component MemoireDonnees is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
RW : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
end component;
component MemoireAdressesRetour is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
E : out STD_LOGIC;
F : out STD_LOGIC);
end component;
component LC is
Generic (Instruction_Vector_Size : Natural;
Command_size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
end component;
component MUX is
Generic (Nb_bits : Natural;
Instruction_Vector_Size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0');
signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0');
signal Addr_MemoireDonnees_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0');
signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0');
signal New_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0');
signal R_Aux : STD_LOGIC := '0';
signal W_Aux : STD_LOGIC := '0';
signal E : STD_LOGIC;
signal F : STD_LOGIC;
begin
instance_LC : LC
generic map (Instruction_Vector_Size => Instruction_bus_size,
Command_size => 1,
Bits_Controle => Bits_Controle_LC)
port map ( Instruction => IN_Instruction,
Commande => Commande_MemoireDonnees);
instance_MUX_IN : MUX
generic map (Nb_bits => Adresse_mem_size,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_IN)
port map ( Instruction => IN_Instruction,
IN1 => IN_A (Adresse_mem_size - 1 downto 0),
IN2 => IN_B (Adresse_mem_size - 1 downto 0),
OUTPUT => IN_Addr_MemoireDonnees);
instance_MUX_IN_EBP : MUX
generic map (Nb_bits => Adresse_mem_size,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_IN_EBP)
port map ( Instruction => IN_Instruction,
IN1 => IN_Addr_MemoireDonnees,
IN2 => Addr_MemoireDonnees_EBP,
OUTPUT => Addr_MemoireDonnees);
instance_MUX_OUT : MUX
generic map (Nb_bits => Nb_bits,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_OUT)
port map ( Instruction => IN_Instruction,
IN1 => Sortie_MemoireDonnees,
IN2 => IN_B,
OUTPUT => intern_OUT_B);
instance_MemoireDonnees : MemoireDonnees
generic map (Nb_bits => Nb_bits,
Addr_size => Adresse_mem_size,
Mem_size => Mem_size)
port map ( Addr => Addr_MemoireDonnees,
RW => Commande_MemoireDonnees(0),
D_IN => IN_B,
RST => RST,
CLK => CLK,
D_OUT => Sortie_MemoireDonnees);
instance_MemoireEBP : MemoireAdressesRetour
generic map (Nb_bits => Adresse_mem_size,
Addr_size => Adresse_size_mem_EBP,
Mem_size => Mem_EBP_size
)
port map ( R => R_Aux,
W => W_Aux,
D_IN => New_EBP,
RST => RST,
CLK => CLK,
D_OUT => EBP,
E => E,
F => F
);
OUT_A <= (others => '0') when RST = '0' else
IN_A;
OUT_B <= (others => '0') when RST = '0' else
intern_OUT_B;
OUT_Instruction <= (others => '0') when RST = '0' else
IN_Instruction;
R_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
'0';
W_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
'0';
Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0);
end Structural;

31
Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider1000.vhd → Processeur.srcs/sources_1/new/LC.vhd
查看文件

@ -2,9 +2,9 @@
-- Company:
-- Engineer:
--
-- Create Date: 09.04.2021 21:44:36
-- Create Date: 17.04.2021 21:49:57
-- Design Name:
-- Module Name: ClockDivider1000 - Structural
-- Module Name: LC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
@ -24,27 +24,22 @@ use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ClockDivider1000 is
Port ( clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC);
end ClockDivider1000;
entity LC is
Generic (Instruction_Vector_Size : Natural;
Command_size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
end LC;
architecture Structural of ClockDivider1000 is
component ClockDivider10
Port ( clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC);
end component;
signal aux1, aux2 : STD_LOGIC;
architecture Behavioral of LC is
begin
U1: ClockDivider10 port map(clk_in, aux1);
U2: ClockDivider10 port map(aux1, aux2);
U3: ClockDivider10 port map(aux2, clk_out);
end Structural;
Commande <= Bits_Controle (((1 + to_integer(unsigned(Instruction))) * Command_size - 1) downto (Command_size * to_integer(unsigned(Instruction))));
end Behavioral;

48
Processeur.srcs/sources_1/new/MUX.vhd 一般檔案
查看文件

@ -0,0 +1,48 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17.04.2021 21:49:57
-- Design Name:
-- Module Name: MUX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX is
Generic (Nb_bits : Natural;
Instruction_Vector_Size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end MUX;
architecture Behavioral of MUX is
begin
OUTPUT <= IN1 when (Bits_Controle(to_integer(unsigned(Instruction))) = '1') else
IN2;
end Behavioral;

78
Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd 一般檔案
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@ -0,0 +1,78 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16.04.2021 14:35:04
-- Design Name:
-- Module Name: MemoireAdressesRetour - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MemoireAdressesRetour is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
E : out STD_LOGIC;
F : out STD_LOGIC);
end MemoireAdressesRetour;
architecture Behavioral of MemoireAdressesRetour is
signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
signal Addr : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0');
constant EMPTY : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0');
constant FULL : STD_LOGIC_VECTOR (Addr_size downto 0) := (Addr_size => '1', others => '0');
begin
process
begin
wait until CLK'event and CLK = '1';
if (RST = '0' ) then
MEMORY <= (others => '0');
Addr <= (others => '0');
else
if (W = '1') then
MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
Addr <= Addr + 1;
elsif (R = '1') then
Addr <= Addr - 1;
end if;
end if;
end process;
E <= '1' when Addr = EMPTY else
'0';
F <= '1' when Addr = FULL else
'0';
D_OUT <= (others => '0') when Addr = EMPTY else
MEMORY (to_integer(unsigned(Addr)) * Nb_bits - 1 downto Nb_bits * (to_integer(unsigned(Addr)) - 1));
end Behavioral;

62
Processeur.srcs/sources_1/new/MemoireDonnees.vhd 一般檔案
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@ -0,0 +1,62 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16.04.2021 14:35:04
-- Design Name:
-- Module Name: MemoireDonnees - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MemoireDonnees is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
RW : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
end MemoireDonnees;
architecture Behavioral of MemoireDonnees is
signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
begin
process
begin
wait until CLK'event and CLK = '1';
if (RST = '0') then
MEMORY <= (others => '0');
else
if (RW = '0') then
MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
end if;
end if;
end process;
D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
end Behavioral;

47
Processeur.srcs/sources_1/new/MemoireInstructions.vhd 一般檔案
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@ -0,0 +1,47 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16.04.2021 14:35:04
-- Design Name:
-- Module Name: MemoireInstructions - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MemoireInstructions is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
end MemoireInstructions;
architecture Behavioral of MemoireInstructions is
signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) :=
"00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "10101000000000000000000000000" & "10001000000000000000000000000" & "01100000000000000000000000000" & "00001000000000000001000000000" & "01010000000100000010100000000" & "00010000000000000000100000000" & "01001000000010000000100000000" & "01110000001010000000100000000" & "01001000000010000000000000000" & "01001000000000000000000000000" & "10011000101110000010000000000" & "01011000001010000001100000000" & "01011000000110000001000000000" & "01110000001000000000100000000" & "01001000000010000000000000000" & "01011000001100000000100000000" & "01101000000100000001100000000" & "01001000000110000110000000000" & "00001000000100000000000000010" & "01010000000000000010000000000" & "01011000000100000000000000000" & "00010000000100000000100000010" & "01001000000010000000100000000" & "01110000001000000000100000000" & "01001000000010000000000000000" & "01011000001010000000100000000" & "01001000000100000000100000000" & "01101000000000000001100000000" & "01001000000110000000100000000" & "00001000000000000001000000000" & "01010000000100000001100000000" & "00010000000000000000100000000" & "01001000000010000000100000000" & "01110000000110000000100000000" & "01001000000010000000000000000" & "01001000000000000000000000000" & "10100000000000000000000000000" & "01011000000010000000000000000" & "01011000000000000000100000000" & "01000000000010000000000000000" & "01001000000000000000100000000" & "10011000000010000000100000000" & "01011000000110000001100000000" & "01011000000100000001000000000" & "01011000000010000000000000000" & "01000000000000000000100000000" & "01101000000000000001000000000" & "01001000000100000101000000000" & "00001000000000000001000000000" & "00010000000000000001100000000" & "01001000000110000000100000000" & "01000000000100000000100000000" & "01001000000000000000100000000" & "10001000000000000000000000000" & "01100000000000000000000000000" & "00001000000000000001000000000" & "00010000000000000001100000000" & "01001000000110000000100000000" & "01000000000100000000100000000" & "01010000000010000000000000000" & "01001000000000000000000000000" & "10100000000000000000000000000" & "01011000000110000001100000000" & "01011000000100000001000000000" & "01011000000010000000000000000" & "01011000000000000000100000000" & "01000000000010000000000000000" & "01001000000000000001000000000" & "01101000000000000001000000000" & "01001000000100000111000000000" & "00001000000000000001000000000" & "00010000000000000001100000000" & "01001000000110000000100000000" & "01000000000100000000100000000" & "01001000000000000000000000000" & "10001000000000000000000000000" & "01100000000000000000000000000" & "00001000000000000001000000000" & "00010000000000000001100000000" & "01001000000110000000100000000" & "01000000000100000000100000000" & "01010000000010000000000000000" & "01001000000000000000100000000" & "01111001100000000000000000000";
begin
D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
end Behavioral;

328
Processeur.srcs/sources_1/new/Pipeline.vhd 一般檔案
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@ -0,0 +1,328 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.04.2021 16:57:41
-- Design Name:
-- Module Name: Pipeline - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Pipeline is
Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3;
Memoire_Instruction_Size : Natural := 8;
Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16;
Addr_registres_size : Natural := 4;
Memoire_Size : Natural := 32;
Adresse_mem_size : Natural := 5;
Memoire_Adresses_Retour_Size : Natural := 16;
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
Port (CLK : STD_LOGIC;
RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end Pipeline;
architecture Behavioral of Pipeline is
component Etage1_LectureInstruction is
Generic (Instruction_size_in_memory : Natural;
Addr_size_mem_instruction : Natural;
Mem_instruction_size : Natural;
Nb_bits : Natural;
Instruction_bus_size : Natural;
Nb_registres : Natural;
Mem_adresse_retour_size : Natural;
Adresse_size_mem_adresse_retour : Natural;
Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
Code_Instruction_JMP : STD_LOGIC_VECTOR;
Code_Instruction_JMZ : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR;
Code_Instruction_STOP : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Z : in STD_LOGIC;
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end component;
component Etage2_5_Registres is
Generic ( Nb_bits : Natural;
Nb_registres : Natural;
Addr_registres_size : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
Code_Instruction_PRI : STD_LOGIC_VECTOR;
Code_Instruction_GET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end component;
component Etage3_Calcul is
Generic ( Nb_bits : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX : STD_LOGIC_VECTOR);
Port ( RST : in STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC);
end component;
component Etage4_Memoire is
Generic ( Nb_bits : Natural;
Mem_size : Natural;
Adresse_mem_size : Natural;
Instruction_bus_size : Natural;
Mem_EBP_size : Natural;
Adresse_size_mem_EBP : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end component;
signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal C_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal C_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal C_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal C_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal Instruction_from_1 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_from_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_from_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_from_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_to_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_to_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_to_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_to_5 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal N : STD_LOGIC := '0';
signal Z : STD_LOGIC := '0';
signal O : STD_LOGIC := '0';
signal C : STD_LOGIC := '0';
constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111";
constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000";
constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001";
constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010";
constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000100010000000000000";
constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000111100111111110";
constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
begin
instance_Etage1 : Etage1_LectureInstruction
generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
Mem_instruction_size => Memoire_Instruction_Size,
Nb_bits => Nb_bits,
Instruction_bus_size => Instruction_Bus_Size,
Nb_registres => Nb_Registres,
Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
Instructions_critiques_ecriture => Instructions_critiques_ecriture,
Code_Instruction_JMP => Code_Instruction_JMP,
Code_Instruction_JMZ => Code_Instruction_JMZ,
Code_Instruction_CALL => Code_Instruction_CALL,
Code_Instruction_RET => Code_Instruction_RET,
Code_Instruction_STOP => Code_Instruction_STOP
)
port map (
CLK => CLK,
RST => RST,
Z => Z,
A => A_from_1,
B => B_from_1,
C => C_from_1,
Instruction => Instruction_from_1
);
instance_Etage2_5 : Etage2_5_Registres
generic map( Nb_bits => Nb_bits,
Nb_Registres => Nb_Registres,
Addr_registres_size => Addr_registres_size,
Instruction_bus_size => Instruction_Bus_Size,
Bits_Controle_LC_5 => Bits_Controle_LC_5,
Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B,
Code_Instruction_PRI => Code_Instruction_PRI,
Code_Instruction_GET => Code_Instruction_GET
)
port map( CLK => CLK,
RST => RST,
STD_IN => STD_IN,
STD_OUT => STD_OUT,
IN_2_A => A_to_2,
IN_2_B => B_to_2,
IN_2_C => C_to_2,
IN_2_Instruction => Instruction_to_2,
OUT_2_A => A_from_2,
OUT_2_B => B_from_2,
OUT_2_C => C_from_2,
OUT_2_Instruction => Instruction_from_2,
IN_5_A => A_to_5,
IN_5_B => B_to_5,
IN_5_Instruction => Instruction_to_5
);
instance_Etage3 : Etage3_Calcul
generic map( Nb_bits => Nb_bits,
Instruction_bus_size => Instruction_Bus_Size,
Bits_Controle_LC => Bits_Controle_LC_3,
Bits_Controle_MUX => Bits_Controle_MUX_3
)
port map( RST => RST,
IN_A => A_to_3,
IN_B => B_to_3,
IN_C => C_to_3,
IN_Instruction => Instruction_to_3,
OUT_A => A_from_3,
OUT_B => B_from_3,
OUT_Instruction => Instruction_from_3,
N => N,
O => O,
Z => Z,
C => C
);
instance_Etage4 : Etage4_Memoire
generic map( Nb_bits => Nb_bits,
Mem_size => Memoire_Size,
Adresse_mem_size => Adresse_mem_size,
Instruction_bus_size => Instruction_Bus_Size,
Mem_EBP_size => Memoire_Adresses_Retour_Size,
Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,
Bits_Controle_LC => Bits_Controle_LC_4,
Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT,
Code_Instruction_CALL => Code_Instruction_CALL,
Code_Instruction_RET => Code_Instruction_RET
)
port map( CLK => CLK,
RST => RST,
IN_A => A_to_4,
IN_B => B_to_4,
IN_Instruction => Instruction_to_4,
OUT_A => A_from_4,
OUT_B => B_from_4,
OUT_Instruction => Instruction_from_4
);
process
begin
wait until CLK'event and CLK = '1';
A_to_2 <= A_from_1;
B_to_2 <= B_from_1;
C_to_2 <= C_from_1;
Instruction_to_2 <= Instruction_from_1;
A_to_3 <= A_from_2;
B_to_3 <= B_from_2;
C_to_3 <= C_from_2;
Instruction_to_3 <= Instruction_from_2;
A_to_4 <= A_from_3;
B_to_4 <= B_from_3;
Instruction_to_4 <= Instruction_from_3;
A_to_5 <= A_from_4;
B_to_5 <= B_from_4;
Instruction_to_5 <= Instruction_from_4;
end process;
end Behavioral;

88
Processeur.srcs/sources_1/new/System.vhd 一般檔案
查看文件

@ -0,0 +1,88 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.04.2021 10:19:15
-- Design Name:
-- Module Name: System - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity System is
Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
sw : in STD_LOGIC_VECTOR (7 downto 0);
btnC : in STD_LOGIC;
CLK : STD_LOGIC);
end System;
architecture Structural of System is
component Pipeline is
Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3;
Memoire_Instruction_Size : Natural := 8;
Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16;
Memoire_Size : Natural := 32;
Memoire_Adresses_Retour_Size : Natural := 16;
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
Port (CLK : STD_LOGIC;
RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
component Clock_Divider is
Port ( CLK_IN : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end component;
signal my_RST : STD_LOGIC;
signal my_CLK : STD_LOGIC;
signal buff_CLK : STD_LOGIC;
begin
clk_div : Clock_Divider
port map (CLK_IN => CLK,
CLK_OUT => buff_CLK);
clk_div_2 : Clock_Divider
port map (CLK_IN => buff_CLK,
CLK_OUT => my_CLK);
instance : Pipeline
generic map (Addr_Memoire_Instruction_Size => 7,
Memoire_Instruction_Size => 128)
port map (CLK => my_CLK,
RST => my_RST,
STD_IN => sw,
STD_OUT => led);
my_RST <= '0' when btnC = '1' else
'1';
end Structural;

180
proj/GPIO.xpr → Processeur.xpr
查看文件

@ -3,10 +3,10 @@
<!-- -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.xpr">
<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/TestGITProcesseur/FPGA_PIR/Processeur.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="0138f6f78b4b4ef3a03837b84ae3d333"/>
<Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/>
<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@ -17,21 +17,22 @@
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="SimulatorLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../repo"/>
<Option Name="IPOutputRepo" Val="$PPRDIR/../repo/cache"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PPRDIR/GPIO.ip_user_files"/>
<Option Name="IPStaticSourceDir" Val="$PPRDIR/GPIO.ip_user_files/ipstatic"/>
<Option Name="IPUserFilesDir" Val="$PPRDIR/Processeur.ip_user_files"/>
<Option Name="IPStaticSourceDir" Val="$PPRDIR/Processeur.ip_user_files/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTXSimLaunchSim" Val="231"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -54,55 +55,85 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../src/hdl/Ps2Interface.vhd">
<File Path="$PSRCDIR/sources_1/new/ALU.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/clk_wiz_0_clk_wiz.vhd">
<File Path="$PSRCDIR/sources_1/new/System.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/MouseDisplay.vhd">
<File Path="$PSRCDIR/sources_1/new/BancRegistres.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/MouseCtl.vhd">
<File Path="$PSRCDIR/sources_1/new/MemoireAdressesRetour.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/clk_wiz_0.vhd">
<File Path="$PSRCDIR/sources_1/new/MemoireInstructions.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/vga_ctrl.vhd">
<File Path="$PSRCDIR/sources_1/new/MemoireDonnees.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/UART_TX_CTRL.vhd">
<File Path="$PSRCDIR/sources_1/new/MUX.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/debouncer.vhd">
<File Path="$PSRCDIR/sources_1/new/LC.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/GPIO_Demo.vhd">
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@ -110,14 +141,16 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="GPIO_demo"/>
<Option Name="TopModule" Val="System"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../src/constraints/Basys3_Master.xdc">
<File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../../../../Xilinx/digilent-xdc-master/Basys-3-Master.xdc"/>
<Attr Name="ImportTime" Val="1614979917"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
@ -127,14 +160,89 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/TestMemoireDonnees.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TestMemoireAdressesRetour.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TestBancRegistres.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TestALU.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TestMemoireInstructions.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_LC.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_MUX.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_Etape1_LectureInstruction.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_Etage3_Calcul.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_Etage4_Memoire.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_Etage2_5_Registres.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_Pipeline.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="GPIO_demo"/>
<Option Name="TopModule" Val="Test_Pipeline"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
</Config>
</FileSet>
</FileSets>
@ -157,42 +265,26 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design">
<Option Id="Directive">0</Option>
<Option Id="FlattenHierarchy">1</Option>
<Option Id="FsmExtraction">0</Option>
</Step>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015">
<Desc>Vivado Implementation Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
<Step Id="opt_design">
<Option Id="Directive">4</Option>
</Step>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design">
<Option Id="Directive">14</Option>
</Step>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design">
<Option Id="Directive">5</Option>
</Step>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>

165
SimulationsConfig/Test_Pipeline_behav1.wcfg 一般檔案
查看文件

@ -0,0 +1,165 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="Test_Pipeline_behav1.wdb" id="1">
<top_modules>
<top_module name="Test_Pipeline" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="320666666fs"></ZoomStartTime>
<ZoomEndTime time="441266667fs"></ZoomEndTime>
<Cursor1Time time="404267000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="146"></NameColumnWidth>
<ValueColumnWidth column_width="73"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="10" />
<wvobject fp_name="/Test_Pipeline/my_CLK" type="logic">
<obj_property name="ElementShortName">my_CLK</obj_property>
<obj_property name="ObjectShortName">my_CLK</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/my_RST" type="logic">
<obj_property name="ElementShortName">my_RST</obj_property>
<obj_property name="ObjectShortName">my_RST</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/my_STD_IN" type="array">
<obj_property name="ElementShortName">my_STD_IN[7:0]</obj_property>
<obj_property name="ObjectShortName">my_STD_IN[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/my_STD_OUT" type="array">
<obj_property name="ElementShortName">my_STD_OUT[7:0]</obj_property>
<obj_property name="ObjectShortName">my_STD_OUT[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/CLK_period" type="other">
<obj_property name="ElementShortName">CLK_period</obj_property>
<obj_property name="ObjectShortName">CLK_period</obj_property>
</wvobject>
<wvobject fp_name="group20" type="group">
<obj_property name="label">Etage1</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject fp_name="/Test_Pipeline/instance/Instruction_from_1" type="array">
<obj_property name="ElementShortName">Instruction_from_1[4:0]</obj_property>
<obj_property name="ObjectShortName">Instruction_from_1[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/A_from_1" type="array">
<obj_property name="ElementShortName">A_from_1[7:0]</obj_property>
<obj_property name="ObjectShortName">A_from_1[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/B_from_1" type="array">
<obj_property name="ElementShortName">B_from_1[7:0]</obj_property>
<obj_property name="ObjectShortName">B_from_1[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/C_from_1" type="array">
<obj_property name="ElementShortName">C_from_1[7:0]</obj_property>
<obj_property name="ObjectShortName">C_from_1[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group21" type="group">
<obj_property name="label">Etage2</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject fp_name="/Test_Pipeline/instance/Instruction_from_2" type="array">
<obj_property name="ElementShortName">Instruction_from_2[4:0]</obj_property>
<obj_property name="ObjectShortName">Instruction_from_2[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/A_from_2" type="array">
<obj_property name="ElementShortName">A_from_2[7:0]</obj_property>
<obj_property name="ObjectShortName">A_from_2[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/B_from_2" type="array">
<obj_property name="ElementShortName">B_from_2[7:0]</obj_property>
<obj_property name="ObjectShortName">B_from_2[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/C_from_2" type="array">
<obj_property name="ElementShortName">C_from_2[7:0]</obj_property>
<obj_property name="ObjectShortName">C_from_2[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group22" type="group">
<obj_property name="label">Etage3</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject fp_name="/Test_Pipeline/instance/Instruction_from_3" type="array">
<obj_property name="ElementShortName">Instruction_from_3[4:0]</obj_property>
<obj_property name="ObjectShortName">Instruction_from_3[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/A_from_3" type="array">
<obj_property name="ElementShortName">A_from_3[7:0]</obj_property>
<obj_property name="ObjectShortName">A_from_3[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/B_from_3" type="array">
<obj_property name="ElementShortName">B_from_3[7:0]</obj_property>
<obj_property name="ObjectShortName">B_from_3[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group23" type="group">
<obj_property name="label">Etage4</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject fp_name="/Test_Pipeline/instance/Instruction_from_4" type="array">
<obj_property name="ElementShortName">Instruction_from_4[4:0]</obj_property>
<obj_property name="ObjectShortName">Instruction_from_4[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/A_from_4" type="array">
<obj_property name="ElementShortName">A_from_4[7:0]</obj_property>
<obj_property name="ObjectShortName">A_from_4[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/B_from_4" type="array">
<obj_property name="ElementShortName">B_from_4[7:0]</obj_property>
<obj_property name="ObjectShortName">B_from_4[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group31" type="group">
<obj_property name="label">Registres</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/REGISTRES" type="array">
<obj_property name="ElementShortName">REGISTRES[127:0]</obj_property>
<obj_property name="ObjectShortName">REGISTRES[127:0]</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrA" type="array">
<obj_property name="ElementShortName">AddrA[3:0]</obj_property>
<obj_property name="ObjectShortName">AddrA[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrB" type="array">
<obj_property name="ElementShortName">AddrB[3:0]</obj_property>
<obj_property name="ObjectShortName">AddrB[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrC" type="array">
<obj_property name="ElementShortName">AddrC[3:0]</obj_property>
<obj_property name="ObjectShortName">AddrC[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrW" type="array">
<obj_property name="ElementShortName">AddrW[3:0]</obj_property>
<obj_property name="ObjectShortName">AddrW[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/W" type="logic">
<obj_property name="ElementShortName">W</obj_property>
<obj_property name="ObjectShortName">W</obj_property>
</wvobject>
<wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/DATA" type="array">
<obj_property name="ElementShortName">DATA[7:0]</obj_property>
<obj_property name="ObjectShortName">DATA[7:0]</obj_property>
</wvobject>
</wvobject>
</wave_config>

13
proj/GPIO.cache/wt/gui_resources.wdf
查看文件

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9
proj/GPIO.cache/wt/java_command_handlers.wdf
查看文件

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4
proj/GPIO.cache/wt/project.wpc
查看文件

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38
proj/GPIO.cache/wt/synthesis.wdf
查看文件

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3
proj/GPIO.cache/wt/synthesis_details.wdf
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48
proj/GPIO.cache/wt/webtalk_pa.xml
查看文件

@ -1,48 +0,0 @@
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Fri Apr 09 23:28:53 2021">
<section name="Project Information" visible="false">
<property name="ProjectID" value="f5d1f37f0c514482aeb99b8a58e27639" type="ProjectID"/>
<property name="ProjectIteration" value="3" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AutoConnectTarget" value="1" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="1" type="JavaHandler"/>
<property name="OpenHardwareManager" value="1" type="JavaHandler"/>
<property name="RunBitgen" value="1" type="JavaHandler"/>
<property name="RunImplementation" value="1" type="JavaHandler"/>
<property name="RunSynthesis" value="1" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
</item>
<item name="Gui Resources Info">
<property name="BaseDialog_OK" value="6" type="GuiResourceData"/>
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="5" type="GuiResourceData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="13" type="GuiResourceData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="2" type="GuiResourceData"/>
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="1" type="GuiResourceData"/>
<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="1" type="GuiResourceData"/>
<property name="PACommandNames_RUN_BITGEN" value="1" type="GuiResourceData"/>
<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiResourceData"/>
<property name="ProgramDebugTab_PROGRAM_DEVICE" value="1" type="GuiResourceData"/>
<property name="ProgramFpgaDialog_PROGRAM" value="1" type="GuiResourceData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiResourceData"/>
</item>
<item name="Other">
<property name="GuiMode" value="4" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="3" type="TclMode"/>
</item>
</section>
</application>
</document>

8
proj/GPIO.hw/GPIO.lpr
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@ -1,8 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2016.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0">
<HWSession Dir="hw_1" File="hw.xml"/>
</labtools>

15
proj/GPIO.hw/hw_1/hw.xml
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@ -1,15 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2016.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<hwsession version="1" minor="2">
<device name="xc7a35t_0" gui_info=""/>
<ObjectList object_type="hw_device" gui_info="">
<Object name="xc7a35t_0" gui_info="">
<Properties Property="PROBES.FILE" value=""/>
<Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/$_project_name__demo.bit"/>
</Object>
</ObjectList>
<probeset name="hw project" active="false"/>
</hwsession>

5
proj/GPIO.runs/.jobs/vrs_config_1.xml
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
proj/GPIO.runs/.jobs/vrs_config_2.xml
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
</Runs>

5
proj/GPIO.runs/.jobs/vrs_config_3.xml
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
</Runs>

0
proj/GPIO.runs/impl_1/.Vivado_Implementation.queue.rst
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5
proj/GPIO.runs/impl_1/.init_design.begin.rst
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
</Process>
</ProcessHandle>

0
proj/GPIO.runs/impl_1/.init_design.end.rst
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5
proj/GPIO.runs/impl_1/.opt_design.begin.rst
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
</Process>
</ProcessHandle>

0
proj/GPIO.runs/impl_1/.opt_design.end.rst
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5
proj/GPIO.runs/impl_1/.place_design.begin.rst
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
</Process>
</ProcessHandle>

0
proj/GPIO.runs/impl_1/.place_design.end.rst
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5
proj/GPIO.runs/impl_1/.route_design.begin.rst
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
</Process>
</ProcessHandle>

0
proj/GPIO.runs/impl_1/.route_design.end.rst
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10
proj/GPIO.runs/impl_1/.vivado.begin.rst
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@ -1,10 +0,0 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="2772">
</Process>
</ProcessHandle>
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="12740">
</Process>
</ProcessHandle>

0
proj/GPIO.runs/impl_1/.vivado.end.rst
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5
proj/GPIO.runs/impl_1/.write_bitstream.begin.rst
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="1988">
</Process>
</ProcessHandle>

0
proj/GPIO.runs/impl_1/.write_bitstream.end.rst
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二進制
proj/GPIO.runs/impl_1/GPIO_demo.bit
查看文件

未顯示二進位檔案。

67
proj/GPIO.runs/impl_1/GPIO_demo.tcl
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@ -1,67 +0,0 @@
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
set_msg_config -id {HDL 9-1061} -limit 100000
set_msg_config -id {HDL 9-1654} -limit 100000
start_step write_bitstream
set ACTIVE_STEP write_bitstream
set rc [catch {
create_msg_db write_bitstream.pb
open_checkpoint GPIO_demo_routed.dcp
set_property webtalk.parent_dir C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.cache/wt [current_project]
catch { write_mem_info -force GPIO_demo.mmi }
write_bitstream -force -no_partial_bitfile GPIO_demo.bit
catch { write_sysdef -hwdef GPIO_demo.hwdef -bitfile GPIO_demo.bit -meminfo GPIO_demo.mmi -file GPIO_demo.sysdef }
catch {write_debug_probes -quiet -force debug_nets}
close_msg_db -file write_bitstream.pb
} RESULT]
if {$rc} {
step_failed write_bitstream
return -code error $RESULT
} else {
end_step write_bitstream
unset ACTIVE_STEP
}

475
proj/GPIO.runs/impl_1/GPIO_demo.vdi
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@ -1,475 +0,0 @@
#-----------------------------------------------------------
# Vivado v2016.4 (64-bit)
# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
# Start of session at: Fri Apr 09 23:15:32 2021
# Process ID: 960
# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source GPIO_demo.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2016.4
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
Command: opt_design -directive RuntimeOptimized
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
Starting Logic Optimization Task
Implement Debug Cores | Checksum: 11fc7498c
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 16f269fca
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 6 cells.
Phase 2 Constant propagation | Checksum: 233a26f9e
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 363 unconnected nets.
INFO: [Opt 31-11] Eliminated 2 unconnected cells.
Phase 3 Sweep | Checksum: 1bb596469
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Phase 4 BUFG optimization
INFO: [Opt 31-12] Eliminated 0 unconnected nets.
INFO: [Opt 31-11] Eliminated 0 unconnected cells.
Phase 4 BUFG optimization | Checksum: 1bb596469
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1bb596469
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design -directive RuntimeOptimized
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 1.2 Build Placer Netlist Model
Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 1.3 Constrain Clocks/Macros
Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 1 Placer Initialization | Checksum: f331096b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 7e244a0f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3 Detail Placement | Checksum: 1c30709cd
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Ending Placer Task | Checksum: dd20239e
Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
INFO: [Common 17-83] Releasing license: Implementation
41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
Command: route_design -directive RuntimeOptimized
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 111c71c3e
Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198 | TNS=0.000 | WHS=-0.144 | THS=-6.171 |
Phase 2 Router Initialization | Checksum: 1ee683561
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 10e02a291
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 107
Number of Nodes with overlaps = 0
Phase 4.1.1 Update Timing
Phase 4.1.1 Update Timing | Checksum: da308246
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
Phase 4.2.1 Update Timing
Phase 4.2.1 Update Timing | Checksum: 1185cfc05
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 16251cbd9
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717 | TNS=0.000 | WHS=0.062 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 6 Post Hold Fix | Checksum: 12245b0d3
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.234075 %
Global Horizontal Routing Utilization = 0.228267 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1af3f3601
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1af3f3601
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 15d59118d
Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717 | TNS=0.000 | WHS=0.062 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 15d59118d
Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-35] Done setting XDC timing constraints.
Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
#-----------------------------------------------------------
# Vivado v2016.4 (64-bit)
# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
# Start of session at: Fri Apr 09 23:19:20 2021
# Process ID: 1988
# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source GPIO_demo.tcl -notrace
Command: open_checkpoint GPIO_demo_routed.dcp
Starting open_checkpoint Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 215.074 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2016.4
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
INFO: [Project 1-604] Checkpoint was created with Vivado v2016.4 (64-bit) build 1756540
open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 528.973 ; gain = 318.734
Command: write_bitstream -force -no_partial_bitfile GPIO_demo.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 13383552 bits.
Writing bitstream ./GPIO_demo.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 965.129 ; gain = 436.156
INFO: [Vivado_Tcl 4-395] Unable to parse hwdef file GPIO_demo.hwdef
INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:19:56 2021...

414
proj/GPIO.runs/impl_1/GPIO_demo_960.backup.vdi
查看文件

@ -1,414 +0,0 @@
#-----------------------------------------------------------
# Vivado v2016.4 (64-bit)
# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
# Start of session at: Fri Apr 09 23:15:32 2021
# Process ID: 960
# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source GPIO_demo.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2016.4
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
Command: opt_design -directive RuntimeOptimized
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
Starting Logic Optimization Task
Implement Debug Cores | Checksum: 11fc7498c
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 16f269fca
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 6 cells.
Phase 2 Constant propagation | Checksum: 233a26f9e
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 363 unconnected nets.
INFO: [Opt 31-11] Eliminated 2 unconnected cells.
Phase 3 Sweep | Checksum: 1bb596469
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Phase 4 BUFG optimization
INFO: [Opt 31-12] Eliminated 0 unconnected nets.
INFO: [Opt 31-11] Eliminated 0 unconnected cells.
Phase 4 BUFG optimization | Checksum: 1bb596469
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1bb596469
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design -directive RuntimeOptimized
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 1.2 Build Placer Netlist Model
Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 1.3 Constrain Clocks/Macros
Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 1 Placer Initialization | Checksum: f331096b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 7e244a0f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3 Detail Placement | Checksum: 1c30709cd
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Ending Placer Task | Checksum: dd20239e
Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
INFO: [Common 17-83] Releasing license: Implementation
41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
Command: route_design -directive RuntimeOptimized
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 111c71c3e
Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198 | TNS=0.000 | WHS=-0.144 | THS=-6.171 |
Phase 2 Router Initialization | Checksum: 1ee683561
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 10e02a291
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 107
Number of Nodes with overlaps = 0
Phase 4.1.1 Update Timing
Phase 4.1.1 Update Timing | Checksum: da308246
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
Phase 4.2.1 Update Timing
Phase 4.2.1 Update Timing | Checksum: 1185cfc05
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 16251cbd9
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717 | TNS=0.000 | WHS=0.062 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 6 Post Hold Fix | Checksum: 12245b0d3
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.234075 %
Global Horizontal Routing Utilization = 0.228267 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1af3f3601
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1af3f3601
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 15d59118d
Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717 | TNS=0.000 | WHS=0.062 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 15d59118d
Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-35] Done setting XDC timing constraints.
Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...

235
proj/GPIO.runs/impl_1/GPIO_demo_clock_utilization_routed.rpt
查看文件

@ -1,235 +0,0 @@
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
| Date : Fri Apr 09 23:16:39 2021
| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
| Command : report_clock_utilization -file GPIO_demo_clock_utilization_routed.rpt
| Design : GPIO_demo
| Device : 7a35t-cpg236
| Speed File : -1 PRODUCTION 1.16 2016-11-09
---------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Cell Type Counts per Global Clock: Region X0Y0
7. Cell Type Counts per Global Clock: Region X1Y0
8. Cell Type Counts per Global Clock: Region X0Y1
9. Load Cell Placement Summary for Global Clock g0
10. Load Cell Placement Summary for Global Clock g1
11. Load Cell Placement Summary for Global Clock g2
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 3 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 72 | 0 | 0 | 0 |
| BUFIO | 0 | 20 | 0 | 0 | 0 |
| BUFMR | 0 | 10 | 0 | 0 | 0 |
| BUFR | 0 | 20 | 0 | 0 | 0 |
| MMCM | 1 | 5 | 0 | 0 | 0 |
| PLL | 0 | 5 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | | | 2 | 336 | 0 | 9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | | | 2 | 243 | 0 | 10.000 | sys_clk_pin | CLK_IBUF_BUFG_inst/O | CLK_IBUF_BUFG |
| g2 | src0 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | | | 1 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf/O | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y0 | X1Y0 | 1 | 0 | 9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 |
| src0 | g2 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y0 | X1Y0 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 |
| src1 | g1 | IBUF/O | IOB_X1Y26 | IOB_X1Y26 | X1Y0 | 1 | 0 | 10.000 | sys_clk_pin | CLK_IBUF_inst/O | CLK_IBUF |
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 484 | 1200 | 206 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 31 | 1500 | 2 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 63 | 1200 | 21 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y2 | 0 | 0 |
| Y1 | 1 | 0 |
| Y0 | 2 | 2 |
+----+----+----+
6. Cell Type Counts per Global Clock: Region X0Y0
-------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
| g0 | n/a | BUFG/O | None | 273 | 0 | 273 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
| g1 | n/a | BUFG/O | None | 211 | 0 | 211 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLK_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
7. Cell Type Counts per Global Clock: Region X1Y0
-------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
| g1 | n/a | BUFG/O | None | 32 | 0 | 31 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLK_IBUF_BUFG |
| g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
8. Cell Type Counts per Global Clock: Region X0Y1
-------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
| g0 | n/a | BUFG/O | None | 63 | 0 | 63 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
9. Load Cell Placement Summary for Global Clock g0
--------------------------------------------------
+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
| g0 | BUFG/O | n/a | clk_out1_clk_wiz_0 | 9.259 | {0.000 4.630} | | 336 | 0 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+------+----+
| | X0 | X1 |
+----+------+----+
| Y2 | 0 | 0 |
| Y1 | 63 | 0 |
| Y0 | 273 | 0 |
+----+------+----+
10. Load Cell Placement Summary for Global Clock g1
---------------------------------------------------
+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
| g1 | BUFG/O | n/a | sys_clk_pin | 10.000 | {0.000 5.000} | | 242 | 0 | 1 | 0 | CLK_IBUF_BUFG |
+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+------+-----+
| | X0 | X1 |
+----+------+-----+
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 211 | 32 |
+----+------+-----+
11. Load Cell Placement Summary for Global Clock g2
---------------------------------------------------
+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
| g2 | BUFG/O | n/a | clkfbout_clk_wiz_0 | 10.000 | {0.000 5.000} | | 0 | 0 | 1 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 1 |
+----+----+----+
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y2 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf]
set_property LOC BUFGCTRL_X0Y0 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf]
set_property LOC BUFGCTRL_X0Y1 [get_cells CLK_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X1Y26 [get_ports CLK]
# Clock net "Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1" driven by instance "Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}
add_cells_to_pblock [get_pblocks {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1"}]]]
resize_pblock [get_pblocks {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
#endgroup
# Clock net "CLK_IBUF_BUFG" driven by instance "CLK_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y1"
#startgroup
create_pblock {CLKAG_CLK_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_CLK_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="CLK_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_CLK_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
#endgroup

104
proj/GPIO.runs/impl_1/GPIO_demo_control_sets_placed.rpt
查看文件

@ -1,104 +0,0 @@
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
| Date : Fri Apr 09 23:16:08 2021
| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file GPIO_demo_control_sets_placed.rpt
| Design : GPIO_demo
| Device : xc7a35t
--------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 36 |
| Unused register locations in slices containing registers | 94 |
+----------------------------------------------------------+-------+
2. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 132 | 57 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 226 | 57 |
| Yes | No | No | 105 | 40 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 115 | 32 |
+--------------+-----------------------+------------------------+-----------------+--------------+
3. Detailed Control Set Information
-----------------------------------
+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk_inter0 | 1 | 4 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/data_inter0 | 1 | 4 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_overflow_i_1_n_0 | | 2 | 4 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/shift_frame | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/reset_bit_count | 1 | 4 |
| CLK_IBUF_BUFG | eqOp2_in | tmrVal[3]_i_1_n_0 | 2 | 4 |
| CLK_IBUF_BUFG | | sendStr[3][0] | 1 | 5 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_1_n_0 | 2 | 7 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/g0_b0_n_0 | | 2 | 7 |
| CLK_IBUF_BUFG | uartSend | | 2 | 7 |
| CLK_IBUF_BUFG | uartData | | 6 | 7 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/load_rx_data_reg_n_0 | | 2 | 8 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_inc[7]_i_1_n_0 | | 3 | 8 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_inc[7]_i_1_n_0 | | 4 | 8 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_1_n_0 | | 2 | 10 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_new_reg_n_0 | | 3 | 11 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_1_n_0 | 3 | 11 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/eqOp4_in | Inst_vga_ctrl/v_cntr_reg0 | 3 | 12 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/vga_red_reg[3]_i_1_n_0 | 2 | 12 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/eqOp4_in | 3 | 12 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_new_reg_n_0 | | 4 | 12 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_1_n_0 | 4 | 14 |
| CLK_IBUF_BUFG | | Inst_UART_TX_CTRL/bitTmr[0]_i_1_n_0 | 4 | 14 |
| CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[4][0]_i_1_n_0 | 4 | 16 |
| CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[1][0]_i_1_n_0 | 4 | 16 |
| CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[2][0]_i_1_n_0 | 4 | 16 |
| CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[3][0]_i_1_n_0 | 4 | 16 |
| CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[0][0]_i_1_n_0 | 4 | 16 |
| CLK_IBUF_BUFG | | | 10 | 17 |
| CLK_IBUF_BUFG | | reset_cntr0 | 5 | 18 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/v_sync_reg | | 10 | 23 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/reset_timeout_cnt_reg_n_0 | 7 | 24 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/reset_periodic_check_cnt | 6 | 26 |
| CLK_IBUF_BUFG | | tmrCntr0 | 7 | 27 |
| CLK_IBUF_BUFG | uartData | strIndex0 | 8 | 31 |
| CLK_IBUF_BUFG | Inst_UART_TX_CTRL/txBit_i_1_n_0 | Inst_UART_TX_CTRL/READY | 9 | 32 |
| Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | | 47 | 115 |
+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
+--------+-----------------------+
| Fanout | Number of ControlSets |
+--------+-----------------------+
| 4 | 5 |
| 5 | 1 |
| 7 | 4 |
| 8 | 3 |
| 10 | 1 |
| 11 | 2 |
| 12 | 4 |
| 14 | 2 |
| 16+ | 14 |
+--------+-----------------------+

35
proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt
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@ -1,35 +0,0 @@
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
| Date : Fri Apr 09 23:16:01 2021
| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
| Command : report_drc -file GPIO_demo_drc_opted.rpt
| Design : GPIO_demo
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Synthesized
------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 0
+------+----------+-------------+------------+
| Rule | Severity | Description | Violations |
+------+----------+-------------+------------+
+------+----------+-------------+------------+
2. REPORT DETAILS
-----------------

二進制
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.pb
查看文件

未顯示二進位檔案。

35
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt
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@ -1,35 +0,0 @@
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
| Date : Fri Apr 09 23:16:37 2021
| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
| Command : report_drc -file GPIO_demo_drc_routed.rpt -pb GPIO_demo_drc_routed.pb -rpx GPIO_demo_drc_routed.rpx
| Design : GPIO_demo
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Routed
---------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 0
+------+----------+-------------+------------+
| Rule | Severity | Description | Violations |
+------+----------+-------------+------------+
+------+----------+-------------+------------+
2. REPORT DETAILS
-----------------

二進制
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpx
查看文件

未顯示二進位檔案。

277
proj/GPIO.runs/impl_1/GPIO_demo_io_placed.rpt
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@ -1,277 +0,0 @@
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
| Date : Fri Apr 09 23:16:08 2021
| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
| Command : report_io -file GPIO_demo_io_placed.rpt
| Design : GPIO_demo
| Device : xc7a35t
| Speed File : -1
| Package : cpg236
------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 67 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity |
+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
| A1 | | | GND | GND | | | | | | | 0.0 | | | | | |
| A2 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | |
| A3 | | | GND | GND | | | | | | | 0.0 | | | | | |
| A4 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | |
| A5 | | | GND | GND | | | | | | | 0.0 | | | | | |
| A6 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | |
| A7 | | | GND | GND | | | | | | | 0.0 | | | | | |
| A8 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | |
| A9 | | | GND | GND | | | | | | | 0.0 | | | | | |
| A10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | |
| A11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | |
| A12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | |
| A13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | |
| A14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | |
| A15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | |
| A16 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | |
| A17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | |
| A18 | UART_TXD | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| A19 | | | GND | GND | | | | | | | 0.0 | | | | | |
| B1 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | |
| B2 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | |
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | |
| B4 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | |
| B5 | | | GND | GND | | | | | | | 0.0 | | | | | |
| B6 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | |
| B7 | | | GND | GND | | | | | | | 0.0 | | | | | |
| B8 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | |
| B9 | | | GND | GND | | | | | | | 0.0 | | | | | |
| B10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | |
| B11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | |
| B12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | |
| B13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | |
| B14 | | | GND | GND | | | | | | | 0.0 | | | | | |
| B15 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | |
| B16 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | |
| B17 | PS2_DATA | High Range | IO_L14N_T2_SRCC_16 | BIDIR | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | PULLUP | | | NONE |
| B18 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | |
| B19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | |
| C1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | |
| C2 | | | GND | GND | | | | | | | 0.0 | | | | | |
| C3 | | | GND | GND | | | | | | | 0.0 | | | | | |
| C4 | | | GND | GND | | | | | | | 0.0 | | | | | |
| C5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | |
| C6 | | | GND | GND | | | | | | | 0.0 | | | | | |
| C7 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | |
| C8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | |
| C9 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | |
| C10 | | | GND | GND | | | | | | | 0.0 | | | | | |
| C11 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | |
| C12 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | |
| C13 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | |
| C14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | |
| C15 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | |
| C16 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | |
| C17 | PS2_CLK | High Range | IO_L14P_T2_SRCC_16 | BIDIR | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | PULLUP | | | NONE |
| C18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | |
| C19 | | | GND | GND | | | | | | | 0.0 | | | | | |
| D1 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | |
| D2 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | |
| D3 | | | GND | GND | | | | | | | 0.0 | | | | | |
| D17 | VGA_GREEN[3] | High Range | IO_0_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| D18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | |
| D19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | |
| E1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | |
| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | |
| E3 | | | GND | GND | | | | | | | 0.0 | | | | | |
| E17 | | | GND | GND | | | | | | | 0.0 | | | | | |
| E18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | |
| E19 | LED[1] | High Range | IO_L3N_T0_DQS_EMCCLK_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| F1 | | | GND | GND | | | | | | | 0.0 | | | | | |
| F2 | | | GND | GND | | | | | | | 0.0 | | | | | |
| F3 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | |
| F17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | |
| F18 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | |
| F19 | | | GND | GND | | | | | | | 0.0 | | | | | |
| G1 | | | GND | GND | | | | | | | 0.0 | | | | | |
| G2 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | |
| G3 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | |
| G7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | |
| G8 | | | GND | GND | | | | | | | 0.0 | | | | | |
| G9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | |
| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | |
| G11 | | | GND | GND | | | | | | | 0.0 | | | | | |
| G12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | |
| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | |
| G17 | VGA_GREEN[2] | High Range | IO_L5N_T0_D07_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | |
| G19 | VGA_RED[0] | High Range | IO_L4N_T0_D05_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| H1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | |
| H2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | |
| H3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | |
| H7 | | | GND | GND | | | | | | | 0.0 | | | | | |
| H8 | | | GND | GND | | | | | | | 0.0 | | | | | |
| H9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | |
| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | |
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | |
| H12 | | | GND | GND | | | | | | | 0.0 | | | | | |
| H13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | |
| H17 | VGA_GREEN[1] | High Range | IO_L5P_T0_D06_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| H18 | | | GND | GND | | | | | | | 0.0 | | | | | |
| H19 | VGA_RED[1] | High Range | IO_L4P_T0_D04_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| J1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | |
| J2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | |
| J3 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | |
| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | |
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | |
| J9 | | | GND | GND | | | | | | | 0.0 | | | | | |
| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | |
| J11 | | | GND | GND | | | | | | | 0.0 | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | |
| J13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | |
| J17 | VGA_GREEN[0] | High Range | IO_L7P_T1_D09_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| J18 | VGA_BLUE[3] | High Range | IO_L7N_T1_D10_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| J19 | VGA_RED[2] | High Range | IO_L6N_T0_D08_VREF_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| K1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | |
| K2 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | |
| K3 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | |
| K7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | |
| K8 | | | GND | GND | | | | | | | 0.0 | | | | | |
| K12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | |
| K13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | |
| K17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | |
| K18 | VGA_BLUE[2] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| K19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | |
| L1 | LED[15] | High Range | IO_L6N_T0_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| L2 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | |
| L3 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | |
| L7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | |
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | |
| L9 | | | GND | GND | | | | | | | 0.0 | | | | | |
| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | |
| L11 | | | GND | GND | | | | | | | 0.0 | | | | | |
| L12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | |
| L13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | |
| L17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | |
| L18 | VGA_BLUE[1] | High Range | IO_L8P_T1_D11_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| L19 | | | GND | GND | | | | | | | 0.0 | | | | | |
| M1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | |
| M2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | |
| M3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | |
| M7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | |
| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | |
| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | |
| M11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | |
| M12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | |
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | |
| M17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | |
| M18 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | |
| M19 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | |
| N1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | |
| N2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | |
| N3 | LED[13] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| N7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | |
| N8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | |
| N9 | | | GND | GND | | | | | | | 0.0 | | | | | |
| N10 | | | VCCINT | VCCINT | | | | | | | | | | | | |
| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | |
| N12 | | | GND | GND | | | | | | | 0.0 | | | | | |
| N13 | | | GND | GND | | | | | | | 0.0 | | | | | |
| N17 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | |
| N18 | VGA_BLUE[0] | High Range | IO_L9P_T1_DQS_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| N19 | VGA_RED[3] | High Range | IO_L9N_T1_DQS_D13_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| P1 | LED[14] | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| P2 | | | GND | GND | | | | | | | 0.0 | | | | | |
| P3 | LED[12] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| P17 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | |
| P18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | |
| P19 | VGA_HS | High Range | IO_L10P_T1_D14_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| R1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | |
| R2 | SW[15] | High Range | IO_L1P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE |
| R3 | SW[11] | High Range | IO_L2P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE |
| R17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | |
| R18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | |
| R19 | VGA_VS | High Range | IO_L10N_T1_D15_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| T1 | SW[14] | High Range | IO_L3P_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE |
| T2 | SW[10] | High Range | IO_L1N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE |
| T3 | SW[9] | High Range | IO_L2N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE |
| T17 | BTN[2] | High Range | IO_L17P_T2_A14_D30_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| T18 | BTN[0] | High Range | IO_L17N_T2_A13_D29_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| T19 | | | GND | GND | | | | | | | 0.0 | | | | | |
| U1 | SW[13] | High Range | IO_L3N_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE |
| U2 | SSEG_AN[0] | High Range | IO_L9N_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| U3 | LED[11] | High Range | IO_L9P_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| U4 | SSEG_AN[1] | High Range | IO_L11P_T1_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| U5 | SSEG_CA[4] | High Range | IO_L16P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| U6 | | | GND | GND | | | | | | | 0.0 | | | | | |
| U7 | SSEG_CA[6] | High Range | IO_L19P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| U8 | SSEG_CA[2] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| U9 | | | GND | GND | | | | | | | 0.0 | | | | | |
| U10 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | |
| U11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | |
| U12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | |
| U13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | |
| U14 | LED[6] | High Range | IO_25_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| U15 | LED[5] | High Range | IO_L23P_T3_A03_D19_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| U16 | LED[0] | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| U17 | BTN[3] | High Range | IO_L18P_T2_A12_D28_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| U18 | BTN[4] | High Range | IO_L18N_T2_A11_D27_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| U19 | LED[2] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| V1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | |
| V2 | SW[8] | High Range | IO_L5P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE |
| V3 | LED[9] | High Range | IO_L6P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| V4 | SSEG_AN[2] | High Range | IO_L11N_T1_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| V5 | SSEG_CA[5] | High Range | IO_L16N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | |
| V7 | SSEG_CA[7] | High Range | IO_L19N_T3_VREF_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| V8 | SSEG_CA[3] | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| V9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | |
| V10 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | |
| V11 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | |
| V12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | |
| V13 | LED[8] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| V14 | LED[7] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| V15 | SW[5] | High Range | IO_L21P_T3_DQS_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| V16 | SW[1] | High Range | IO_L19P_T3_A10_D26_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| V17 | SW[0] | High Range | IO_L19N_T3_A09_D25_VREF_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| V18 | | | GND | GND | | | | | | | 0.0 | | | | | |
| V19 | LED[3] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| W1 | | | GND | GND | | | | | | | 0.0 | | | | | |
| W2 | SW[12] | High Range | IO_L5N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE |
| W3 | LED[10] | High Range | IO_L6N_T0_VREF_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| W4 | SSEG_AN[3] | High Range | IO_L12N_T1_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| W5 | CLK | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE |
| W6 | SSEG_CA[1] | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| W7 | SSEG_CA[0] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| W8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | |
| W9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | |
| W10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | |
| W11 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | |
| W12 | | | GND | GND | | | | | | | 0.0 | | | | | |
| W13 | SW[7] | High Range | IO_L22P_T3_A05_D21_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| W14 | SW[6] | High Range | IO_L22N_T3_A04_D20_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| W15 | SW[4] | High Range | IO_L21N_T3_DQS_A06_D22_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| W16 | SW[2] | High Range | IO_L20P_T3_A08_D24_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| W17 | SW[3] | High Range | IO_L20N_T3_A07_D23_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
| W18 | LED[4] | High Range | IO_L16P_T2_CSI_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE |
| W19 | BTN[1] | High Range | IO_L16N_T2_A15_D31_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE |
+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
* Default value

205
proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt
查看文件

@ -1,205 +0,0 @@
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
| Date : Fri Apr 09 23:16:38 2021
| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
| Command : report_methodology -file GPIO_demo_methodology_drc_routed.rpt -rpx GPIO_demo_methodology_drc_routed.rpx
| Design : GPIO_demo
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------
Report Methodology
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 34
+-----------+----------+-------------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-------------------------------+------------+
| TIMING-18 | Warning | Missing input or output delay | 34 |
+-----------+----------+-------------------------------+------------+
2. REPORT DETAILS
-----------------
TIMING-18#1 Warning
Missing input or output delay
An input delay is missing on BTN[0] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#2 Warning
Missing input or output delay
An input delay is missing on BTN[1] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#3 Warning
Missing input or output delay
An input delay is missing on BTN[2] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#4 Warning
Missing input or output delay
An input delay is missing on BTN[3] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#5 Warning
Missing input or output delay
An input delay is missing on BTN[4] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#6 Warning
Missing input or output delay
An input delay is missing on PS2_CLK relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#7 Warning
Missing input or output delay
An input delay is missing on PS2_DATA relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#8 Warning
Missing input or output delay
An output delay is missing on SSEG_AN[0] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#9 Warning
Missing input or output delay
An output delay is missing on SSEG_AN[1] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#10 Warning
Missing input or output delay
An output delay is missing on SSEG_AN[2] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#11 Warning
Missing input or output delay
An output delay is missing on SSEG_AN[3] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#12 Warning
Missing input or output delay
An output delay is missing on SSEG_CA[0] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#13 Warning
Missing input or output delay
An output delay is missing on SSEG_CA[1] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#14 Warning
Missing input or output delay
An output delay is missing on SSEG_CA[2] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#15 Warning
Missing input or output delay
An output delay is missing on SSEG_CA[3] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#16 Warning
Missing input or output delay
An output delay is missing on SSEG_CA[4] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#17 Warning
Missing input or output delay
An output delay is missing on SSEG_CA[5] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#18 Warning
Missing input or output delay
An output delay is missing on SSEG_CA[6] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#19 Warning
Missing input or output delay
An output delay is missing on SSEG_CA[7] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#20 Warning
Missing input or output delay
An output delay is missing on UART_TXD relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#21 Warning
Missing input or output delay
An output delay is missing on VGA_BLUE[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#22 Warning
Missing input or output delay
An output delay is missing on VGA_BLUE[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#23 Warning
Missing input or output delay
An output delay is missing on VGA_BLUE[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#24 Warning
Missing input or output delay
An output delay is missing on VGA_BLUE[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#25 Warning
Missing input or output delay
An output delay is missing on VGA_GREEN[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#26 Warning
Missing input or output delay
An output delay is missing on VGA_GREEN[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#27 Warning
Missing input or output delay
An output delay is missing on VGA_GREEN[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#28 Warning
Missing input or output delay
An output delay is missing on VGA_GREEN[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#29 Warning
Missing input or output delay
An output delay is missing on VGA_HS relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#30 Warning
Missing input or output delay
An output delay is missing on VGA_RED[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#31 Warning
Missing input or output delay
An output delay is missing on VGA_RED[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#32 Warning
Missing input or output delay
An output delay is missing on VGA_RED[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#33 Warning
Missing input or output delay
An output delay is missing on VGA_RED[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>
TIMING-18#34 Warning
Missing input or output delay
An output delay is missing on VGA_VS relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
Related violations: <none>

二進制
proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpx
查看文件

未顯示二進位檔案。

二進制
proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp
查看文件

未顯示二進位檔案。

二進制
proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp
查看文件

未顯示二進位檔案。

157
proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpt
查看文件

@ -1,157 +0,0 @@
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
| Date : Fri Apr 09 23:16:38 2021
| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
| Command : report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
| Design : GPIO_demo
| Device : xc7a35tcpg236-1
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
-------------------------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+-------+
| Total On-Chip Power (W) | 0.223 |
| Dynamic (W) | 0.151 |
| Device Static (W) | 0.072 |
| Effective TJA (C/W) | 5.0 |
| Max Ambient (C) | 83.9 |
| Junction Temperature (C) | 26.1 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+-------+
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Clocks | 0.005 | 5 | --- | --- |
| Slice Logic | 0.003 | 1426 | --- | --- |
| LUT as Logic | 0.002 | 564 | 20800 | 2.71 |
| CARRY4 | <0.001 | 132 | 8150 | 1.62 |
| Register | <0.001 | 578 | 41600 | 1.39 |
| F7/F8 Muxes | <0.001 | 3 | 32600 | <0.01 |
| Others | 0.000 | 18 | --- | --- |
| Signals | 0.002 | 1137 | --- | --- |
| MMCM | 0.123 | 1 | 5 | 20.00 |
| I/O | 0.018 | 67 | 106 | 63.21 |
| Static Power | 0.072 | | | |
| Total | 0.223 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 1.000 | 0.020 | 0.010 | 0.010 |
| Vccaux | 1.800 | 0.081 | 0.069 | 0.013 |
| Vcco33 | 3.300 | 0.006 | 0.005 | 0.001 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 5.0 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 4.6 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+--------------------+----------------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+--------------------+----------------------------------------------------+-----------------+
| clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 | 9.3 |
| clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 | 10.0 |
| sys_clk_pin | CLK | 10.0 |
+--------------------+----------------------------------------------------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+-----------------------------+-----------+
| Name | Power (W) |
+-----------------------------+-----------+
| GPIO_demo | 0.151 |
| Inst_UART_TX_CTRL | <0.001 |
| Inst_btn_debounce | <0.001 |
| Inst_vga_ctrl | 0.130 |
| Inst_MouseCtl | 0.004 |
| Inst_Ps2Interface | 0.001 |
| ps2_clk_IOBUF_inst | 0.000 |
| ps2_data_IOBUF_inst | 0.000 |
| Inst_MouseDisplay | <0.001 |
| clk_wiz_0_inst | 0.124 |
| U0 | 0.124 |
+-----------------------------+-----------+

二進制
proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpx
查看文件

未顯示二進位檔案。

二進制
proj/GPIO.runs/impl_1/GPIO_demo_power_summary_routed.pb
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未顯示二進位檔案。

二進制
proj/GPIO.runs/impl_1/GPIO_demo_route_status.pb
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未顯示二進位檔案。

11
proj/GPIO.runs/impl_1/GPIO_demo_route_status.rpt
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@ -1,11 +0,0 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 1888 :
# of nets not needing routing.......... : 743 :
# of internally routed nets........ : 743 :
# of routable nets..................... : 1145 :
# of fully routed nets............. : 1145 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

二進制
proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp
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未顯示二進位檔案。

2891
proj/GPIO.runs/impl_1/GPIO_demo_timing_summary_routed.rpt
查看文件

檔案差異因為檔案過大而被隱藏 載入差異

二進制
proj/GPIO.runs/impl_1/GPIO_demo_timing_summary_routed.rpx
查看文件

未顯示二進位檔案。

二進制
proj/GPIO.runs/impl_1/GPIO_demo_utilization_placed.pb
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未顯示二進位檔案。

212
proj/GPIO.runs/impl_1/GPIO_demo_utilization_placed.rpt
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@ -1,212 +0,0 @@
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
| Date : Fri Apr 09 23:16:08 2021
| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
| Command : report_utilization -file GPIO_demo_utilization_placed.rpt -pb GPIO_demo_utilization_placed.pb
| Design : GPIO_demo
| Device : 7a35tcpg236-1
| Design State : Fully Placed
---------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 564 | 0 | 20800 | 2.71 |
| LUT as Logic | 564 | 0 | 20800 | 2.71 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 578 | 0 | 41600 | 1.39 |
| Register as Flip Flop | 578 | 0 | 41600 | 1.39 |
| Register as Latch | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 3 | 0 | 16300 | 0.02 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 2 | Yes | Set | - |
| 576 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+------+-------+-----------+-------+
| Slice | 282 | 0 | 8150 | 3.46 |
| SLICEL | 182 | 0 | | |
| SLICEM | 100 | 0 | | |
| LUT as Logic | 564 | 0 | 20800 | 2.71 |
| using O5 output only | 0 | | | |
| using O6 output only | 433 | | | |
| using O5 and O6 | 131 | | | |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| LUT Flip Flop Pairs | 171 | 0 | 20800 | 0.82 |
| fully used LUT-FF pairs | 54 | | | |
| LUT-FF pairs with one unused LUT output | 110 | | | |
| LUT-FF pairs with one unused Flip Flop | 111 | | | |
| Unique Control Sets | 36 | | | |
+-------------------------------------------+------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 0 | 0 | 100 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 67 | 67 | 106 | 63.21 |
| IOB Master Pads | 30 | | | |
| IOB Slave Pads | 35 | | | |
| Bonded IPADs | 0 | 0 | 10 | 0.00 |
| Bonded OPADs | 0 | 0 | 4 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 104 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 106 | 0.00 |
| OLOGIC | 0 | 0 | 106 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 3 | 0 | 32 | 9.38 |
| BUFIO | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 1 | 0 | 5 | 20.00 |
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 20 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+------------+------+---------------------+
| Ref Name | Used | Functional Category |
+------------+------+---------------------+
| FDRE | 576 | Flop & Latch |
| LUT2 | 207 | LUT |
| LUT6 | 157 | LUT |
| LUT4 | 136 | LUT |
| CARRY4 | 132 | CarryLogic |
| LUT3 | 93 | LUT |
| LUT5 | 72 | LUT |
| OBUF | 43 | IO |
| LUT1 | 30 | LUT |
| IBUF | 24 | IO |
| MUXF7 | 3 | MuxFx |
| BUFG | 3 | Clock |
| OBUFT | 2 | IO |
| FDSE | 2 | Flop & Latch |
| MMCME2_ADV | 1 | Clock |
+------------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

244
proj/GPIO.runs/impl_1/ISEWrap.js
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@ -1,244 +0,0 @@
//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}

63
proj/GPIO.runs/impl_1/ISEWrap.sh
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@ -1,63 +0,0 @@
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
if [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL

157
proj/GPIO.runs/impl_1/gen_run.xml
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@ -1,157 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1618002924">
<File Type="PWROPT-DRC" Name="GPIO_demo_drc_pwropted.rpt"/>
<File Type="OPT-METHODOLOGY-DRC" Name="GPIO_demo_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="GPIO_demo_timing_summary_init.rpt"/>
<File Type="ROUTE-PWR-RPX" Name="GPIO_demo_power_routed.rpx"/>
<File Type="PA-TCL" Name="GPIO_demo.tcl"/>
<File Type="OPT-HWDEF" Name="GPIO_demo.hwdef"/>
<File Type="RDI-RDI" Name="GPIO_demo.vdi"/>
<File Type="OPT-DCP" Name="GPIO_demo_opt.dcp"/>
<File Type="OPT-DRC" Name="GPIO_demo_drc_opted.rpt"/>
<File Type="OPT-TIMING" Name="GPIO_demo_timing_summary_opted.rpt"/>
<File Type="PWROPT-DCP" Name="GPIO_demo_pwropt.dcp"/>
<File Type="PWROPT-TIMING" Name="GPIO_demo_timing_summary_pwropted.rpt"/>
<File Type="PLACE-DCP" Name="GPIO_demo_placed.dcp"/>
<File Type="PLACE-IO" Name="GPIO_demo_io_placed.rpt"/>
<File Type="PLACE-CLK" Name="GPIO_demo_clock_utilization_placed.rpt"/>
<File Type="PLACE-UTIL" Name="GPIO_demo_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="GPIO_demo_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="GPIO_demo_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="GPIO_demo_incremental_reuse_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="GPIO_demo_incremental_reuse_pre_placed.rpt"/>
<File Type="PLACE-TIMING" Name="GPIO_demo_timing_summary_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="GPIO_demo_postplace_pwropt.dcp"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="GPIO_demo_timing_summary_postplace_pwropted.rpt"/>
<File Type="PHYSOPT-DCP" Name="GPIO_demo_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="GPIO_demo_drc_physopted.rpt"/>
<File Type="PHYSOPT-TIMING" Name="GPIO_demo_timing_summary_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="GPIO_demo_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="GPIO_demo_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="GPIO_demo_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="GPIO_demo_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="GPIO_demo_drc_routed.pb"/>
<File Type="BG-BIN" Name="GPIO_demo.bin"/>
<File Type="ROUTE-DRC-RPX" Name="GPIO_demo_drc_routed.rpx"/>
<File Type="BG-DRC" Name="GPIO_demo.drc"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="GPIO_demo_methodology_drc_routed.rpt"/>
<File Type="BITSTR-MSK" Name="GPIO_demo.msk"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="GPIO_demo_methodology_drc_routed.rpx"/>
<File Type="BG-BGN" Name="GPIO_demo.bgn"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="GPIO_demo_methodology_drc_routed.pb"/>
<File Type="ROUTE-PWR" Name="GPIO_demo_power_routed.rpt"/>
<File Type="ROUTE-PWR-SUM" Name="GPIO_demo_power_summary_routed.pb"/>
<File Type="ROUTE-STATUS" Name="GPIO_demo_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="GPIO_demo_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="GPIO_demo_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-PB" Name="GPIO_demo_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="GPIO_demo_timing_summary_routed.rpx"/>
<File Type="ROUTE-SIMILARITY" Name="GPIO_demo_incremental_reuse_routed.rpt"/>
<File Type="ROUTE-CLK" Name="GPIO_demo_clock_utilization_routed.rpt"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="GPIO_demo_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="GPIO_demo_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="GPIO_demo_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="GPIO_demo_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="GPIO_demo_timing_summary_postroute_physopted.rpx"/>
<File Type="BG-BIT" Name="GPIO_demo.bit"/>
<File Type="BITSTR-RBT" Name="GPIO_demo.rbt"/>
<File Type="BITSTR-NKY" Name="GPIO_demo.nky"/>
<File Type="BITSTR-BMM" Name="GPIO_demo_bd.bmm"/>
<File Type="BITSTR-MMI" Name="GPIO_demo.mmi"/>
<File Type="BITSTR-SYSDEF" Name="GPIO_demo.sysdef"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../src/hdl/Ps2Interface.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/clk_wiz_0_clk_wiz.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/MouseDisplay.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/MouseCtl.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/clk_wiz_0.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/vga_ctrl.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/UART_TX_CTRL.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/debouncer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/GPIO_Demo.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="GPIO_demo"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../src/constraints/Basys3_Master.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015">
<Desc>Vivado Implementation Defaults</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design">
<Option Id="Directive">4</Option>
</Step>
<Step Id="power_opt_design"/>
<Step Id="place_design">
<Option Id="Directive">14</Option>
</Step>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design">
<Option Id="Directive">5</Option>
</Step>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</GenRun>

9
proj/GPIO.runs/impl_1/htr.txt
查看文件

@ -1,9 +0,0 @@
REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
REM
vivado -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace

二進制
proj/GPIO.runs/impl_1/init_design.pb
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未顯示二進位檔案。

二進制
proj/GPIO.runs/impl_1/opt_design.pb
查看文件

未顯示二進位檔案。

二進制
proj/GPIO.runs/impl_1/place_design.pb
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未顯示二進位檔案。

31
proj/GPIO.runs/impl_1/project.wdf
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@ -1,31 +0,0 @@
version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:39:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3031333866366637386234623465663361303338333762383461653364333333:506172656e742050412070726f6a656374204944:00
eof:1785114370

二進制
proj/GPIO.runs/impl_1/route_design.pb
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未顯示二進位檔案。

40
proj/GPIO.runs/impl_1/rundef.js
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@ -1,40 +0,0 @@
//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2016.4/bin;";
} else {
PathVal = "C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2016.4/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
// pre-commands:
ISETouchFile( "write_bitstream", "begin" );
ISEStep( "vivado",
"-log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}

10
proj/GPIO.runs/impl_1/runme.bat
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@ -1,10 +0,0 @@
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*

473
proj/GPIO.runs/impl_1/runme.log
查看文件

@ -1,473 +0,0 @@
*** Running vivado
with args -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
****** Vivado v2016.4 (64-bit)
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
source GPIO_demo.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2016.4
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
Command: opt_design -directive RuntimeOptimized
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
Starting Logic Optimization Task
Implement Debug Cores | Checksum: 11fc7498c
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 16f269fca
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 6 cells.
Phase 2 Constant propagation | Checksum: 233a26f9e
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 363 unconnected nets.
INFO: [Opt 31-11] Eliminated 2 unconnected cells.
Phase 3 Sweep | Checksum: 1bb596469
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Phase 4 BUFG optimization
INFO: [Opt 31-12] Eliminated 0 unconnected nets.
INFO: [Opt 31-11] Eliminated 0 unconnected cells.
Phase 4 BUFG optimization | Checksum: 1bb596469
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1bb596469
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design -directive RuntimeOptimized
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 1.2 Build Placer Netlist Model
Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 1.3 Constrain Clocks/Macros
Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 1 Placer Initialization | Checksum: f331096b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 7e244a0f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 3 Detail Placement | Checksum: 1c30709cd
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
Ending Placer Task | Checksum: dd20239e
Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
INFO: [Common 17-83] Releasing license: Implementation
41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
Command: route_design -directive RuntimeOptimized
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 111c71c3e
Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198 | TNS=0.000 | WHS=-0.144 | THS=-6.171 |
Phase 2 Router Initialization | Checksum: 1ee683561
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 10e02a291
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 107
Number of Nodes with overlaps = 0
Phase 4.1.1 Update Timing
Phase 4.1.1 Update Timing | Checksum: da308246
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
Phase 4.2.1 Update Timing
Phase 4.2.1 Update Timing | Checksum: 1185cfc05
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 16251cbd9
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717 | TNS=0.000 | WHS=0.062 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 6 Post Hold Fix | Checksum: 12245b0d3
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.234075 %
Global Horizontal Routing Utilization = 0.228267 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1af3f3601
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1af3f3601
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 15d59118d
Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717 | TNS=0.000 | WHS=0.062 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 15d59118d
Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-35] Done setting XDC timing constraints.
Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
*** Running vivado
with args -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
****** Vivado v2016.4 (64-bit)
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
source GPIO_demo.tcl -notrace
Command: open_checkpoint GPIO_demo_routed.dcp
Starting open_checkpoint Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 215.074 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2016.4
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
INFO: [Project 1-604] Checkpoint was created with Vivado v2016.4 (64-bit) build 1756540
open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 528.973 ; gain = 318.734
Command: write_bitstream -force -no_partial_bitfile GPIO_demo.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 13383552 bits.
Writing bitstream ./GPIO_demo.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 965.129 ; gain = 436.156
INFO: [Vivado_Tcl 4-395] Unable to parse hwdef file GPIO_demo.hwdef
INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:19:56 2021...

47
proj/GPIO.runs/impl_1/runme.sh
查看文件

@ -1,47 +0,0 @@
#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
#
echo "This script was generated under a different operating system."
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
exit
if [ -z "$PATH" ]; then
PATH=C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2016.4/bin
else
PATH=C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2016.4/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
# pre-commands:
/bin/touch .write_bitstream.begin.rst
EAStep vivado -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace

506
proj/GPIO.runs/impl_1/usage_statistics_webtalk.html
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@ -1,506 +0,0 @@
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>1756540</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Fri Apr 09 23:19:55 2021</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2016.4 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>0138f6f78b4b4ef3a03837b84ae3d333</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>1</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>89e526329a235cb691995f8457477284</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>89e526329a235cb691995f8457477284</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a35t</TD>
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>cpg236</TD>
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz</TD>
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2592 MHz</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'> <TD>runbitgen=1</TD>
<TD>runimplementation=1</TD>
<TD>runsynthesis=1</TD>
</TR> </TABLE>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'> <TD>guimode=1</TD>
</TR> </TABLE>
</TR><TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'> <TD>constraintsetcount=1</TD>
<TD>core_container=false</TD>
<TD>currentimplrun=impl_1</TD>
<TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'> <TD>default_library=xil_defaultlib</TD>
<TD>designmode=RTL</TD>
<TD>export_simulation_activehdl=0</TD>
<TD>export_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'> <TD>export_simulation_modelsim=0</TD>
<TD>export_simulation_questa=0</TD>
<TD>export_simulation_riviera=0</TD>
<TD>export_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'> <TD>export_simulation_xsim=0</TD>
<TD>implstrategy=Vivado Implementation Defaults</TD>
<TD>launch_simulation_activehdl=0</TD>
<TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_modelsim=0</TD>
<TD>launch_simulation_questa=0</TD>
<TD>launch_simulation_riviera=0</TD>
<TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_xsim=0</TD>
<TD>simulator_language=Mixed</TD>
<TD>srcsetcount=9</TD>
<TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'> <TD>target_language=VHDL</TD>
<TD>target_simulator=XSim</TD>
<TD>totalimplruns=1</TD>
<TD>totalsynthesisruns=1</TD>
</TR> </TABLE>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg=3</TD>
<TD>carry4=132</TD>
<TD>fdre=579</TD>
<TD>fdse=2</TD>
</TR><TR ALIGN='LEFT'> <TD>gnd=8</TD>
<TD>ibuf=24</TD>
<TD>lut1=368</TD>
<TD>lut2=207</TD>
</TR><TR ALIGN='LEFT'> <TD>lut3=91</TD>
<TD>lut4=138</TD>
<TD>lut5=73</TD>
<TD>lut6=157</TD>
</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv=1</TD>
<TD>muxf7=3</TD>
<TD>obuf=43</TD>
<TD>obuft=2</TD>
</TR><TR ALIGN='LEFT'> <TD>vcc=8</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg=3</TD>
<TD>carry4=132</TD>
<TD>fdre=579</TD>
<TD>fdse=2</TD>
</TR><TR ALIGN='LEFT'> <TD>gnd=8</TD>
<TD>ibuf=22</TD>
<TD>iobuf=2</TD>
<TD>lut1=368</TD>
</TR><TR ALIGN='LEFT'> <TD>lut2=207</TD>
<TD>lut3=91</TD>
<TD>lut4=138</TD>
<TD>lut5=73</TD>
</TR><TR ALIGN='LEFT'> <TD>lut6=157</TD>
<TD>mmcme2_adv=1</TD>
<TD>muxf7=3</TD>
<TD>obuf=43</TD>
</TR><TR ALIGN='LEFT'> <TD>vcc=8</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v5_1/1</B></TD></TR>
<TR ALIGN='LEFT'> <TD>clkin1_period=10.0</TD>
<TD>clkin2_period=10.0</TD>
<TD>clock_mgr_type=NA</TD>
<TD>component_name=clk_wiz_0</TD>
</TR><TR ALIGN='LEFT'> <TD>core_container=NA</TD>
<TD>enable_axi=0</TD>
<TD>feedback_source=FDBK_AUTO</TD>
<TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'> <TD>iptotal=1</TD>
<TD>manual_override=false</TD>
<TD>num_out_clk=1</TD>
<TD>primitive=MMCM</TD>
</TR><TR ALIGN='LEFT'> <TD>use_dyn_phase_shift=false</TD>
<TD>use_dyn_reconfig=false</TD>
<TD>use_inclk_stopped=false</TD>
<TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'> <TD>use_locked=false</TD>
<TD>use_max_i_jitter=false</TD>
<TD>use_min_o_jitter=false</TD>
<TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'> <TD>use_power_down=false</TD>
<TD>use_reset=false</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
<TD>-checks=default::[not_specified]</TD>
<TD>-fail_on=default::[not_specified]</TD>
<TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
<TD>-messages=default::[not_specified]</TD>
<TD>-name=default::[not_specified]</TD>
<TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-ruledecks=default::[not_specified]</TD>
<TD>-upgrade_cw=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufgctrl_available=32</TD>
<TD>bufgctrl_fixed=0</TD>
<TD>bufgctrl_used=3</TD>
<TD>bufgctrl_util_percentage=9.38</TD>
</TR><TR ALIGN='LEFT'> <TD>bufhce_available=72</TD>
<TD>bufhce_fixed=0</TD>
<TD>bufhce_used=0</TD>
<TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufio_available=20</TD>
<TD>bufio_fixed=0</TD>
<TD>bufio_used=0</TD>
<TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufmrce_available=10</TD>
<TD>bufmrce_fixed=0</TD>
<TD>bufmrce_used=0</TD>
<TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufr_available=20</TD>
<TD>bufr_fixed=0</TD>
<TD>bufr_used=0</TD>
<TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv_available=5</TD>
<TD>mmcme2_adv_fixed=0</TD>
<TD>mmcme2_adv_used=1</TD>
<TD>mmcme2_adv_util_percentage=20.00</TD>
</TR><TR ALIGN='LEFT'> <TD>plle2_adv_available=5</TD>
<TD>plle2_adv_fixed=0</TD>
<TD>plle2_adv_used=0</TD>
<TD>plle2_adv_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'> <TD>dsps_available=90</TD>
<TD>dsps_fixed=0</TD>
<TD>dsps_used=0</TD>
<TD>dsps_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'> <TD>blvds_25=0</TD>
<TD>diff_hstl_i=0</TD>
<TD>diff_hstl_i_18=0</TD>
<TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_hstl_ii_18=0</TD>
<TD>diff_hsul_12=0</TD>
<TD>diff_mobile_ddr=0</TD>
<TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_sstl135_r=0</TD>
<TD>diff_sstl15=0</TD>
<TD>diff_sstl15_r=0</TD>
<TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_sstl18_ii=0</TD>
<TD>hstl_i=0</TD>
<TD>hstl_i_18=0</TD>
<TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>hstl_ii_18=0</TD>
<TD>hsul_12=0</TD>
<TD>lvcmos12=0</TD>
<TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lvcmos18=0</TD>
<TD>lvcmos25=0</TD>
<TD>lvcmos33=1</TD>
<TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lvttl=0</TD>
<TD>mini_lvds_25=0</TD>
<TD>mobile_ddr=0</TD>
<TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'> <TD>ppds_25=0</TD>
<TD>rsds_25=0</TD>
<TD>sstl135=0</TD>
<TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'> <TD>sstl15=0</TD>
<TD>sstl15_r=0</TD>
<TD>sstl18_i=0</TD>
<TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>tmds_33=0</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'> <TD>block_ram_tile_available=50</TD>
<TD>block_ram_tile_fixed=0</TD>
<TD>block_ram_tile_used=0</TD>
<TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>ramb18_available=100</TD>
<TD>ramb18_fixed=0</TD>
<TD>ramb18_used=0</TD>
<TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>ramb36_fifo_available=50</TD>
<TD>ramb36_fifo_fixed=0</TD>
<TD>ramb36_fifo_used=0</TD>
<TD>ramb36_fifo_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg_functional_category=Clock</TD>
<TD>bufg_used=3</TD>
<TD>carry4_functional_category=CarryLogic</TD>
<TD>carry4_used=132</TD>
</TR><TR ALIGN='LEFT'> <TD>fdre_functional_category=Flop &amp; Latch</TD>
<TD>fdre_used=576</TD>
<TD>fdse_functional_category=Flop &amp; Latch</TD>
<TD>fdse_used=2</TD>
</TR><TR ALIGN='LEFT'> <TD>ibuf_functional_category=IO</TD>
<TD>ibuf_used=24</TD>
<TD>lut1_functional_category=LUT</TD>
<TD>lut1_used=30</TD>
</TR><TR ALIGN='LEFT'> <TD>lut2_functional_category=LUT</TD>
<TD>lut2_used=207</TD>
<TD>lut3_functional_category=LUT</TD>
<TD>lut3_used=93</TD>
</TR><TR ALIGN='LEFT'> <TD>lut4_functional_category=LUT</TD>
<TD>lut4_used=136</TD>
<TD>lut5_functional_category=LUT</TD>
<TD>lut5_used=72</TD>
</TR><TR ALIGN='LEFT'> <TD>lut6_functional_category=LUT</TD>
<TD>lut6_used=157</TD>
<TD>mmcme2_adv_functional_category=Clock</TD>
<TD>mmcme2_adv_used=1</TD>
</TR><TR ALIGN='LEFT'> <TD>muxf7_functional_category=MuxFx</TD>
<TD>muxf7_used=3</TD>
<TD>obuf_functional_category=IO</TD>
<TD>obuf_used=43</TD>
</TR><TR ALIGN='LEFT'> <TD>obuft_functional_category=IO</TD>
<TD>obuft_used=2</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'> <TD>f7_muxes_available=16300</TD>
<TD>f7_muxes_fixed=0</TD>
<TD>f7_muxes_used=3</TD>
<TD>f7_muxes_util_percentage=0.02</TD>
</TR><TR ALIGN='LEFT'> <TD>f8_muxes_available=8150</TD>
<TD>f8_muxes_fixed=0</TD>
<TD>f8_muxes_used=0</TD>
<TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=20800</TD>
<TD>lut_as_logic_fixed=0</TD>
<TD>lut_as_logic_used=564</TD>
<TD>lut_as_logic_util_percentage=2.71</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=9600</TD>
<TD>lut_as_memory_fixed=0</TD>
<TD>lut_as_memory_used=0</TD>
<TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>register_as_flip_flop_available=41600</TD>
<TD>register_as_flip_flop_fixed=0</TD>
<TD>register_as_flip_flop_used=578</TD>
<TD>register_as_flip_flop_util_percentage=1.39</TD>
</TR><TR ALIGN='LEFT'> <TD>register_as_latch_available=41600</TD>
<TD>register_as_latch_fixed=0</TD>
<TD>register_as_latch_used=0</TD>
<TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_luts_available=20800</TD>
<TD>slice_luts_fixed=0</TD>
<TD>slice_luts_used=564</TD>
<TD>slice_luts_util_percentage=2.71</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_registers_available=41600</TD>
<TD>slice_registers_fixed=0</TD>
<TD>slice_registers_used=578</TD>
<TD>slice_registers_util_percentage=1.39</TD>
</TR><TR ALIGN='LEFT'> <TD>fully_used_lut_ff_pairs_fixed=1.39</TD>
<TD>fully_used_lut_ff_pairs_used=54</TD>
<TD>lut_as_distributed_ram_fixed=0</TD>
<TD>lut_as_distributed_ram_used=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=20800</TD>
<TD>lut_as_logic_fixed=0</TD>
<TD>lut_as_logic_used=564</TD>
<TD>lut_as_logic_util_percentage=2.71</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=9600</TD>
<TD>lut_as_memory_fixed=0</TD>
<TD>lut_as_memory_used=0</TD>
<TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_shift_register_fixed=0</TD>
<TD>lut_as_shift_register_used=0</TD>
<TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=0</TD>
<TD>lut_ff_pairs_with_one_unused_flip_flop_used=111</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=111</TD>
<TD>lut_ff_pairs_with_one_unused_lut_output_used=110</TD>
<TD>lut_flip_flop_pairs_available=20800</TD>
<TD>lut_flip_flop_pairs_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_flip_flop_pairs_used=171</TD>
<TD>lut_flip_flop_pairs_util_percentage=0.82</TD>
<TD>slice_available=8150</TD>
<TD>slice_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_used=282</TD>
<TD>slice_util_percentage=3.46</TD>
<TD>slicel_fixed=0</TD>
<TD>slicel_used=182</TD>
</TR><TR ALIGN='LEFT'> <TD>slicem_fixed=0</TD>
<TD>slicem_used=100</TD>
<TD>unique_control_sets_used=36</TD>
<TD>using_o5_and_o6_fixed=36</TD>
</TR><TR ALIGN='LEFT'> <TD>using_o5_and_o6_used=131</TD>
<TD>using_o5_output_only_fixed=131</TD>
<TD>using_o5_output_only_used=0</TD>
<TD>using_o6_output_only_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>using_o6_output_only_used=433</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bscane2_available=4</TD>
<TD>bscane2_fixed=0</TD>
<TD>bscane2_used=0</TD>
<TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>capturee2_available=1</TD>
<TD>capturee2_fixed=0</TD>
<TD>capturee2_used=0</TD>
<TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>dna_port_available=1</TD>
<TD>dna_port_fixed=0</TD>
<TD>dna_port_used=0</TD>
<TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>efuse_usr_available=1</TD>
<TD>efuse_usr_fixed=0</TD>
<TD>efuse_usr_used=0</TD>
<TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>frame_ecce2_available=1</TD>
<TD>frame_ecce2_fixed=0</TD>
<TD>frame_ecce2_used=0</TD>
<TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>icape2_available=2</TD>
<TD>icape2_fixed=0</TD>
<TD>icape2_used=0</TD>
<TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>pcie_2_1_available=1</TD>
<TD>pcie_2_1_fixed=0</TD>
<TD>pcie_2_1_used=0</TD>
<TD>pcie_2_1_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>startupe2_available=1</TD>
<TD>startupe2_fixed=0</TD>
<TD>startupe2_used=0</TD>
<TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>xadc_available=1</TD>
<TD>xadc_fixed=0</TD>
<TD>xadc_used=0</TD>
<TD>xadc_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>actual_expansions=695075</TD>
<TD>bogomips=0</TD>
<TD>bram18=0</TD>
<TD>bram36=0</TD>
</TR><TR ALIGN='LEFT'> <TD>bufg=0</TD>
<TD>bufr=0</TD>
<TD>congestion_level=0</TD>
<TD>ctrls=36</TD>
</TR><TR ALIGN='LEFT'> <TD>dsp=0</TD>
<TD>effort=2</TD>
<TD>estimated_expansions=723384</TD>
<TD>ff=578</TD>
</TR><TR ALIGN='LEFT'> <TD>global_clocks=3</TD>
<TD>high_fanout_nets=0</TD>
<TD>iob=67</TD>
<TD>lut=609</TD>
</TR><TR ALIGN='LEFT'> <TD>movable_instances=1499</TD>
<TD>nets=1904</TD>
<TD>pins=8775</TD>
<TD>pll=0</TD>
</TR><TR ALIGN='LEFT'> <TD>router_runtime=0.000000</TD>
<TD>router_timing_driven=1</TD>
<TD>threads=2</TD>
<TD>timing_constraints_exist=1</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-assert=default::[not_specified]</TD>
<TD>-bufg=default::12</TD>
<TD>-cascade_dsp=default::auto</TD>
<TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-control_set_opt_threshold=default::auto</TD>
<TD>-directive=RuntimeOptimized</TD>
<TD>-fanout_limit=default::10000</TD>
<TD>-flatten_hierarchy=none</TD>
</TR><TR ALIGN='LEFT'> <TD>-fsm_extraction=off</TD>
<TD>-gated_clock_conversion=default::off</TD>
<TD>-generic=default::[not_specified]</TD>
<TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-keep_equivalent_registers=default::[not_specified]</TD>
<TD>-max_bram=default::-1</TD>
<TD>-max_bram_cascade_height=default::-1</TD>
<TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'> <TD>-max_uram=default::-1</TD>
<TD>-max_uram_cascade_height=default::-1</TD>
<TD>-mode=default::default</TD>
<TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-no_lc=default::[not_specified]</TD>
<TD>-no_srlextract=default::[not_specified]</TD>
<TD>-no_timing_driven=default::[not_specified]</TD>
<TD>-part=xc7a35tcpg236-1</TD>
</TR><TR ALIGN='LEFT'> <TD>-resource_sharing=default::auto</TD>
<TD>-retiming=default::[not_specified]</TD>
<TD>-rtl=default::[not_specified]</TD>
<TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-rtl_skip_ip=default::[not_specified]</TD>
<TD>-seu_protect=default::none</TD>
<TD>-shreg_min_size=default::3</TD>
<TD>-top=GPIO_demo</TD>
</TR><TR ALIGN='LEFT'> <TD>-verilog_define=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>elapsed=00:00:34s</TD>
<TD>hls_ip=0</TD>
<TD>memory_gain=424.176MB</TD>
<TD>memory_peak=692.656MB</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
</BODY>
</HTML>

453
proj/GPIO.runs/impl_1/usage_statistics_webtalk.xml
查看文件

@ -1,453 +0,0 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_webtalk.xml' majorVersion='1' minorVersion='0' timeStamp='Fri Apr 09 23:19:55 2021'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="1756540" description="" />
<keyValuePair key="date_generated" value="Fri Apr 09 23:19:55 2021" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="Vivado v2016.4 (64-bit)" description="" />
<keyValuePair key="project_id" value="0138f6f78b4b4ef3a03837b84ae3d333" description="" />
<keyValuePair key="project_iteration" value="1" description="" />
<keyValuePair key="random_id" value="89e526329a235cb691995f8457477284" description="" />
<keyValuePair key="registration_id" value="89e526329a235cb691995f8457477284" description="" />
<keyValuePair key="route_design" value="TRUE" description="" />
<keyValuePair key="target_device" value="xc7a35t" description="" />
<keyValuePair key="target_family" value="artix7" description="" />
<keyValuePair key="target_package" value="cpg236" description="" />
<keyValuePair key="target_speed" value="-1" description="" />
<keyValuePair key="tool_flow" value="Vivado" description="" />
</section>
<section name="user_environment" level="1" order="2" description="">
<keyValuePair key="cpu_name" value="Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz" description="" />
<keyValuePair key="cpu_speed" value="2592 MHz" description="" />
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
<keyValuePair key="system_ram" value="8.000 GB" description="" />
<keyValuePair key="total_processors" value="1" description="" />
</section>
<section name="ip_statistics" level="1" order="3" description="">
<section name="clk_wiz_v5_1/1" level="2" order="1" description="">
<keyValuePair key="clkin1_period" value="10.0" description="" />
<keyValuePair key="clkin2_period" value="10.0" description="" />
<keyValuePair key="clock_mgr_type" value="NA" description="" />
<keyValuePair key="component_name" value="clk_wiz_0" description="" />
<keyValuePair key="core_container" value="NA" description="" />
<keyValuePair key="enable_axi" value="0" description="" />
<keyValuePair key="feedback_source" value="FDBK_AUTO" description="" />
<keyValuePair key="feedback_type" value="SINGLE" description="" />
<keyValuePair key="iptotal" value="1" description="" />
<keyValuePair key="manual_override" value="false" description="" />
<keyValuePair key="num_out_clk" value="1" description="" />
<keyValuePair key="primitive" value="MMCM" description="" />
<keyValuePair key="use_dyn_phase_shift" value="false" description="" />
<keyValuePair key="use_dyn_reconfig" value="false" description="" />
<keyValuePair key="use_inclk_stopped" value="false" description="" />
<keyValuePair key="use_inclk_switchover" value="false" description="" />
<keyValuePair key="use_locked" value="false" description="" />
<keyValuePair key="use_max_i_jitter" value="false" description="" />
<keyValuePair key="use_min_o_jitter" value="false" description="" />
<keyValuePair key="use_phase_alignment" value="true" description="" />
<keyValuePair key="use_power_down" value="false" description="" />
<keyValuePair key="use_reset" value="false" description="" />
</section>
</section>
<section name="report_drc" level="1" order="4" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="-append" value="default::[not_specified]" description="" />
<keyValuePair key="-checks" value="default::[not_specified]" description="" />
<keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
<keyValuePair key="-force" value="default::[not_specified]" description="" />
<keyValuePair key="-format" value="default::[not_specified]" description="" />
<keyValuePair key="-messages" value="default::[not_specified]" description="" />
<keyValuePair key="-name" value="default::[not_specified]" description="" />
<keyValuePair key="-return_string" value="default::[not_specified]" description="" />
<keyValuePair key="-ruledecks" value="default::[not_specified]" description="" />
<keyValuePair key="-upgrade_cw" value="default::[not_specified]" description="" />
</section>
</section>
<section name="report_utilization" level="1" order="5" description="">
<section name="clocking" level="2" order="1" description="">
<keyValuePair key="bufgctrl_available" value="32" description="" />
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</section>
<section name="dsp" level="2" order="2" description="">
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</section>
<section name="io_standard" level="2" order="3" description="">
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</section>
<section name="memory" level="2" order="4" description="">
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</section>
<section name="primitives" level="2" order="5" description="">
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<keyValuePair key="mmcme2_adv_functional_category" value="Clock" description="" />
<keyValuePair key="mmcme2_adv_used" value="1" description="" />
<keyValuePair key="muxf7_functional_category" value="MuxFx" description="" />
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<keyValuePair key="obuf_functional_category" value="IO" description="" />
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<keyValuePair key="obuft_functional_category" value="IO" description="" />
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</section>
<section name="slice_logic" level="2" order="6" description="">
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<keyValuePair key="lut_as_memory_available" value="9600" description="" />
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<keyValuePair key="slice_used" value="282" description="" />
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</section>
<section name="specific_feature" level="2" order="7" description="">
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<keyValuePair key="capturee2_available" value="1" description="" />
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<keyValuePair key="frame_ecce2_available" value="1" description="" />
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<keyValuePair key="icape2_available" value="2" description="" />
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<keyValuePair key="xadc_available" value="1" description="" />
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</section>
</section>
<section name="router" level="1" order="6" description="">
<section name="usage" level="2" order="1" description="">
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<keyValuePair key="bogomips" value="0" description="" />
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<keyValuePair key="nets" value="1904" description="" />
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</section>
</section>
<section name="synthesis" level="1" order="7" description="">
<section name="command_line_options" level="2" order="1" description="">
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</section>
<section name="usage" level="2" order="2" description="">
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</section>
</section>
<section name="unisim_transformation" level="1" order="8" description="">
<section name="post_unisim_transformation" level="2" order="1" description="">
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</section>
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</section>
</section>
<section name="vivado_usage" level="1" order="9" description="">
<section name="java_command_handlers" level="2" order="1" description="">
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</section>
<section name="project_data" level="2" order="3" description="">
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</section>
</section>
</section>
</webTalkData>

12
proj/GPIO.runs/impl_1/vivado.jou
查看文件

@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Vivado v2016.4 (64-bit)
# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
# Start of session at: Fri Apr 09 23:19:20 2021
# Process ID: 1988
# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source GPIO_demo.tcl -notrace

二進制
proj/GPIO.runs/impl_1/vivado.pb
查看文件

未顯示二進位檔案。

12
proj/GPIO.runs/impl_1/vivado_960.backup.jou
查看文件

@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Vivado v2016.4 (64-bit)
# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
# Start of session at: Fri Apr 09 23:15:32 2021
# Process ID: 960
# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source GPIO_demo.tcl -notrace

本差異變更的檔案數量過多導致部分檔案未顯示 顯示更多