FPGA_PIR/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt

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Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
| Date : Fri Apr 09 23:16:01 2021
| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
| Command : report_drc -file GPIO_demo_drc_opted.rpt
| Design : GPIO_demo
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Synthesized
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Report DRC
Table of Contents
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1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
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Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 0
+------+----------+-------------+------------+
| Rule | Severity | Description | Violations |
+------+----------+-------------+------------+
+------+----------+-------------+------------+
2. REPORT DETAILS
-----------------