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Processeur OK 22 Instructions, reste a sécuriser les accès mémoire avec des modulo

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Paul Faure 2021-05-08 23:09:39 +02:00
parent 4f64f6664a
commit d1bbb37208
14 changed files with 446 additions and 4365 deletions
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66
Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
View file

@ -4,9 +4,9 @@
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
#set_property PACKAGE_PIN W5 [get_ports clk]
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
set_property PACKAGE_PIN W5 [get_ports CLK]
set_property IOSTANDARD LVCMOS33 [get_ports CLK]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
## Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
@ -25,22 +25,22 @@ set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
## LEDs
@ -68,14 +68,14 @@ set_property PACKAGE_PIN V14 [get_ports {led[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {flag[0]}]
set_property PACKAGE_PIN N3 [get_ports {flag[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {flag[1]}]
set_property PACKAGE_PIN P1 [get_ports {flag[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {flag[2]}]
set_property PACKAGE_PIN L1 [get_ports {flag[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {flag[3]}]
#set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {flag[0]}]
#set_property PACKAGE_PIN N3 [get_ports {flag[1]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {flag[1]}]
#set_property PACKAGE_PIN P1 [get_ports {flag[2]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {flag[2]}]
#set_property PACKAGE_PIN L1 [get_ports {flag[3]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {flag[3]}]
##7 segment display
@ -110,12 +110,12 @@ set_property PACKAGE_PIN L1 [get_ports {flag[3]}]
##Buttons
set_property PACKAGE_PIN U18 [get_ports btnC]
set_property IOSTANDARD LVCMOS33 [get_ports btnC]
#set_property PACKAGE_PIN T18 [get_ports btnU]
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
set_property PACKAGE_PIN W19 [get_ports btnL]
set_property IOSTANDARD LVCMOS33 [get_ports btnL]
set_property PACKAGE_PIN T17 [get_ports btnR]
set_property IOSTANDARD LVCMOS33 [get_ports btnR]
##set_property PACKAGE_PIN T18 [get_ports btnU]
# #set_property IOSTANDARD LVCMOS33 [get_ports btnU]
#set_property PACKAGE_PIN W19 [get_ports btnL]
# set_property IOSTANDARD LVCMOS33 [get_ports btnL]
#set_property PACKAGE_PIN T17 [get_ports btnR]
# set_property IOSTANDARD LVCMOS33 [get_ports btnR]
#set_property PACKAGE_PIN U17 [get_ports btnD]
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]

20
Processeur.srcs/sim_1/new/Test_Pipeline.vhd
View file

@ -39,30 +39,34 @@ architecture Behavioral of Test_Pipeline is
component Pipeline is
Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 28;
Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3;
Memoire_Instruction_Size : Natural := 8;
Instruction_Bus_Size : Natural := 4;
Nb_Instructions : Natural := 16;
Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16;
Memoire_Size : Natural := 8;
Memoire_Size : Natural := 32;
Memoire_Adresses_Retour_Size : Natural := 16;
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
Port (CLK : STD_LOGIC;
RST : STD_LOGIC);
RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
signal my_STD_IN : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
signal my_STD_OUT : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
constant CLK_period : time := 10 ns;
begin
instance : Pipeline
generic map (Addr_Memoire_Instruction_Size => 4,
Memoire_Instruction_Size => 16)
port map (CLK => my_CLK,
RST => my_RST);
RST => my_RST,
STD_IN => my_STD_IN,
STD_OUT => my_STD_OUT);
CLK_process :process
begin

5
Processeur.srcs/sources_1/new/BancRegistres.vhd
View file

@ -39,13 +39,15 @@ entity BancRegistres is
Nb_regs : Natural);
Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrC : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
W : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
QC : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
end BancRegistres;
-- ASK MEILLEURE IDEE UN TABLEAU
@ -65,4 +67,5 @@ begin
end process;
QA <= REGISTRES (((to_integer(unsigned(AddrA)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrA)));
QB <= REGISTRES (((to_integer(unsigned(AddrB)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrB)));
QC <= REGISTRES (((to_integer(unsigned(AddrC)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrC)));
end Behavioral;

57
Processeur.srcs/sources_1/new/Clock_Divider.vhd Normal file
View file

@ -0,0 +1,57 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08.05.2021 21:00:25
-- Design Name:
-- Module Name: Clock_Divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Clock_Divider is
Port ( CLK_IN : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end Clock_Divider;
architecture Behavioral of Clock_Divider is
signal N : Integer := 0;
signal CLK : STD_LOGIC := '1';
begin
process
begin
wait until CLK_IN'event and CLK_IN = '1';
N <= N + 1;
if (N = 1000) then
N <= 0;
if (CLK = '1') then
CLK <= '0';
else
CLK <= '1';
end if;
end if;
end process;
CLK_OUT <= CLK;
end Behavioral;

107
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd
View file

@ -41,13 +41,15 @@ entity Etage1_LectureInstruction is
Nb_registres : Natural;
Mem_adresse_retour_size : Natural;
Adresse_size_mem_adresse_retour : Natural;
Instructions_critiques_lecture : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
Code_Instruction_JMP : STD_LOGIC_VECTOR;
Code_Instruction_JMZ : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR);
Code_Instruction_RET : STD_LOGIC_VECTOR;
Code_Instruction_STOP : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Z : in STD_LOGIC;
@ -85,11 +87,12 @@ architecture Behavioral of Etage1_LectureInstruction is
signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
subtype Registre is integer range -1 to Nb_registres - 1;
type Tab_registres is array (1 to 4) of Registre;
type Tab_registres is array (1 to 3) of Registre;
signal Tableau : Tab_registres := (others => - 1);
signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
signal Nul : STD_LOGIC := '0';
signal E : STD_LOGIC;
signal F : STD_LOGIC;
signal R_Aux : STD_LOGIC := '0';
signal W_Aux : STD_LOGIC := '0';
@ -99,6 +102,7 @@ architecture Behavioral of Etage1_LectureInstruction is
signal bulles : boolean := false;
signal compteur : integer := 0;
signal locked : boolean := false;
begin
instance : MemoireInstructions
@ -119,8 +123,8 @@ begin
RST => RST,
CLK => CLK,
D_OUT => Adresse_Retour,
E => Nul,
F => Nul
E => E,
F => F
);
@ -130,34 +134,35 @@ begin
if (RST = '0') then
Tableau <= (others => -1);
Pointeur_Instruction <= (others => '0');
compteur <= 0;
locked <= false;
C <= Argument_nul;
B <= Argument_nul;
A <= Argument_nul;
Instruction <= Instruction_nulle;
else
Tableau(4) <= Tableau(3);
Tableau(3) <= Tableau(2);
Tableau(2) <= Tableau(1);
Tableau(1) <= -1;
if (not bulles) then
if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
C <= Argument_nul;
B <= Argument_nul;
A <= Argument_nul;
Instruction <= Instruction_nulle;
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
C <= Argument_nul;
B <= Argument_nul;
A <= Argument_nul;
Instruction <= Instruction_nulle;
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
Pointeur_Instruction <= Adresse_Retour;
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
compteur <= compteur + 1;
C <= Argument_nul;
B <= Argument_nul;
A <= Argument_nul;
Instruction <= Instruction_nulle;
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
if (compteur = 2) then
if (Z = '1') then
Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
@ -166,6 +171,21 @@ begin
end if;
compteur <= 0;
end if;
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_STOP) then
if (not locked) then
if (Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits) = Argument_nul) then
locked <= true;
end if;
compteur <= compteur + 1;
if (compteur + 1 = to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)))) then
Pointeur_Instruction <= Pointeur_Instruction + 1;
compteur <= 0;
end if;
end if;
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
else
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
@ -186,8 +206,51 @@ begin
end process;
-- Condition degueu -> Instruction qui lit dans B et B dans tableau ou instruction qui lit dans C et C dans tableau
bulles <= ((Instructions_critiques_lecture(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') and ((to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(1)) or (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(2)) or (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(3)))) or ((Instructions_critiques_lecture_double(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') and ((to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(1)) or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(2)) or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))));
-- Condition degueu -> Instruction critique en lecture simple qui lit dans B et B dans tableau ou instruction critique en lecture double qui lit dans C et C dans tableau
bulles <=
(
(
Instructions_critiques_lecture_A(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
)
and
(
(to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(1))
or
(to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(2))
or
(to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(3))
)
)
or
(
(
Instructions_critiques_lecture_B(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
)
and
(
(to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(1))
or
(to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(2))
or
(to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(3))
)
)
or
(
(
Instructions_critiques_lecture_C(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
)
and
(
(to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(1))
or
(to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(2))
or
(to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))
)
);
R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
'0';
W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else

67
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd
View file

@ -36,9 +36,14 @@ entity Etage2_5_Registres is
Nb_registres : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
Code_Instruction_PRI : STD_LOGIC_VECTOR;
Code_Instruction_GET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@ -59,13 +64,15 @@ architecture Behavioral of Etage2_5_Registres is
Nb_regs : Natural);
Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrC : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
W : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
QC : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
end component;
component LC is
@ -87,9 +94,13 @@ architecture Behavioral of Etage2_5_Registres is
end component;
signal Commande_BancRegistres : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal Sortie_BancRegistres : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal Entree_BancRegistre_DATA : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal Sortie_BancRegistres_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal Sortie_BancRegistres_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_2_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_STD_OUT : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
begin
instance_LC : LC
@ -99,36 +110,66 @@ begin
port map ( Instruction => IN_5_Instruction,
Commande => Commande_BancRegistres);
instance_MUX : MUX
instance_MUX_A : MUX
generic map (Nb_bits => Nb_bits,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_2)
Bits_Controle => Bits_Controle_MUX_2_A)
port map ( Instruction => IN_2_Instruction,
IN1 => IN_2_A,
IN2 => Sortie_BancRegistres_A,
OUTPUT => intern_OUT_2_A);
instance_MUX_B : MUX
generic map (Nb_bits => Nb_bits,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_2_B)
port map ( Instruction => IN_2_Instruction,
IN1 => IN_2_B,
IN2 => Sortie_BancRegistres,
IN2 => Sortie_BancRegistres_B,
OUTPUT => intern_OUT_2_B);
instance_BancRegistres : BancRegistres
generic map (Nb_bits => Nb_bits,
Addr_size => Nb_bits,
Nb_regs => Nb_registres)
port map ( AddrA => IN_2_B,
AddrB => IN_2_C,
port map ( AddrA => IN_2_A,
AddrB => IN_2_B,
AddrC => IN_2_C,
AddrW => IN_5_A,
W => Commande_BancRegistres(0),
DATA => IN_5_B,
DATA => Entree_BancRegistre_DATA,
RST => RST,
CLK => CLK,
QA => Sortie_BancRegistres,
QB => intern_OUT_2_C);
QA => Sortie_BancRegistres_A,
QB => Sortie_BancRegistres_B,
QC => intern_OUT_2_C);
OUT_2_A <= (others => '0') when RST = '0' else
IN_2_A;
intern_OUT_2_A;
OUT_2_B <= (others => '0') when RST = '0' else
intern_OUT_2_B;
OUT_2_C <= (others => '0') when RST = '0' else
intern_OUT_2_C;
OUT_2_Instruction <= (others => '0') when RST = '0' else
IN_2_Instruction;
IN_2_Instruction;
process
begin
wait until CLK'event and CLK = '1';
if (RST = '0') then
intern_STD_OUT <= (others => '0');
else
if (IN_2_Instruction = Code_Instruction_PRI) then
intern_STD_OUT <= intern_OUT_2_A;
end if;
end if;
end process;
STD_OUT <= intern_STD_OUT when RST = '1' else
(others => '0');
Entree_BancRegistre_DATA <= (others => '0') when RST = '0' else
STD_IN when IN_2_Instruction = Code_Instruction_GET else
IN_5_B;
end Behavioral;

65
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
View file

@ -21,10 +21,11 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
@ -35,9 +36,14 @@ entity Etage4_Memoire is
Generic ( Nb_bits : Natural;
Mem_size : Natural;
Instruction_bus_size : Natural;
Mem_EBP_size : Natural;
Adresse_size_mem_EBP : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@ -61,6 +67,20 @@ architecture Structural of Etage4_Memoire is
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
end component;
component MemoireAdressesRetour is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
E : out STD_LOGIC;
F : out STD_LOGIC);
end component;
component LC is
Generic (Instruction_Vector_Size : Natural;
Command_size : Natural;
@ -80,9 +100,17 @@ architecture Structural of Etage4_Memoire is
end component;
signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal Addr_MemoireDonnees_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal R_Aux : STD_LOGIC := '0';
signal W_Aux : STD_LOGIC := '0';
signal E : STD_LOGIC;
signal F : STD_LOGIC;
begin
instance_LC : LC
@ -99,6 +127,15 @@ begin
port map ( Instruction => IN_Instruction,
IN1 => IN_A,
IN2 => IN_B,
OUTPUT => IN_Addr_MemoireDonnees);
instance_MUX_IN_EBP : MUX
generic map (Nb_bits => Nb_bits,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_IN_EBP)
port map ( Instruction => IN_Instruction,
IN1 => IN_Addr_MemoireDonnees,
IN2 => Addr_MemoireDonnees_EBP,
OUTPUT => Addr_MemoireDonnees);
instance_MUX_OUT : MUX
@ -120,6 +157,21 @@ begin
RST => RST,
CLK => CLK,
D_OUT => Sortie_MemoireDonnees);
instance_MemoireEBP : MemoireAdressesRetour
generic map (Nb_bits => Nb_bits,
Addr_size => Adresse_size_mem_EBP,
Mem_size => Mem_EBP_size
)
port map ( R => R_Aux,
W => W_Aux,
D_IN => IN_B,
RST => RST,
CLK => CLK,
D_OUT => EBP,
E => E,
F => F
);
OUT_A <= (others => '0') when RST = '0' else
IN_A;
@ -127,5 +179,12 @@ begin
intern_OUT_B;
OUT_Instruction <= (others => '0') when RST = '0' else
IN_Instruction;
R_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
'0';
W_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
'0';
Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
end Structural;

1
Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
View file

@ -67,6 +67,7 @@ begin
end if;
end if;
end process;
E <= '1' when Addr = EMPTY else
'0';
F <= '1' when Addr = FULL else

2
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
View file

@ -40,7 +40,7 @@ entity MemoireInstructions is
end MemoireInstructions;
architecture Behavioral of MemoireInstructions is
signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"f000000"&x"7040001"&x"6030001"&x"5020001"&x"9010500"&x"9000300"&x"d010000"&x"2000000"&x"e030000";
signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := "10100"&x"000000"&"10001"&x"020000"&"01111"&x"010000"&"10101"&x"0a0000"&"10001"&x"000000"&"10101"&x"0a0000"&"10001"&x"010000"&"01001"&x"01ff00";
begin
D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
end Behavioral;

92
Processeur.srcs/sources_1/new/Pipeline.vhd
View file

@ -33,17 +33,19 @@ use IEEE.STD_LOGIC_1164.ALL;
entity Pipeline is
Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 28;
Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3;
Memoire_Instruction_Size : Natural := 8;
Instruction_Bus_Size : Natural := 4;
Nb_Instructions : Natural := 16;
Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16;
Memoire_Size : Natural := 8;
Memoire_Size : Natural := 32;
Memoire_Adresses_Retour_Size : Natural := 16;
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
Port (CLK : STD_LOGIC;
RST : STD_LOGIC);
RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end Pipeline;
architecture Behavioral of Pipeline is
@ -57,13 +59,15 @@ architecture Behavioral of Pipeline is
Nb_registres : Natural;
Mem_adresse_retour_size : Natural;
Adresse_size_mem_adresse_retour : Natural;
Instructions_critiques_lecture : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
Code_Instruction_JMP : STD_LOGIC_VECTOR;
Code_Instruction_JMZ : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR);
Code_Instruction_RET : STD_LOGIC_VECTOR;
Code_Instruction_STOP : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Z : in STD_LOGIC;
@ -78,9 +82,14 @@ architecture Behavioral of Pipeline is
Nb_registres : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
Code_Instruction_PRI : STD_LOGIC_VECTOR;
Code_Instruction_GET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@ -117,9 +126,14 @@ architecture Behavioral of Pipeline is
Generic ( Nb_bits : Natural;
Mem_size : Natural;
Instruction_bus_size : Natural;
Mem_EBP_size : Natural;
Adresse_size_mem_EBP : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@ -163,21 +177,27 @@ architecture Behavioral of Pipeline is
signal O : STD_LOGIC := '0';
signal C : STD_LOGIC := '0';
constant Bits_Controle_MUX_2 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1101011000000001";
constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111100000001";
constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111011111111111";
constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111101111111111";
constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000010000000000";
constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000011111111110";
constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1100";
constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1101";
constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1110";
constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1111";
constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111100001111111111";
constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000";
constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001";
constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010";
constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000100111111110";
constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000000011111110";
constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000011111111110";
constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000100010000000000000";
constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000111100111111110";
constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
begin
instance_Etage1 : Etage1_LectureInstruction
generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
@ -188,13 +208,15 @@ begin
Nb_registres => Nb_Registres,
Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
Instructions_critiques_lecture => Instructions_critiques_lecture,
Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
Instructions_critiques_ecriture => Instructions_critiques_ecriture,
Code_Instruction_JMP => Code_Instruction_JMP,
Code_Instruction_JMZ => Code_Instruction_JMZ,
Code_Instruction_CALL => Code_Instruction_CALL,
Code_Instruction_RET => Code_Instruction_RET
Code_Instruction_RET => Code_Instruction_RET,
Code_Instruction_STOP => Code_Instruction_STOP
)
port map (
CLK => CLK,
@ -211,10 +233,15 @@ begin
Nb_Registres => Nb_Registres,
Instruction_bus_size => Instruction_Bus_Size,
Bits_Controle_LC_5 => Bits_Controle_LC_5,
Bits_Controle_MUX_2 => Bits_Controle_MUX_2
Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B,
Code_Instruction_PRI => Code_Instruction_PRI,
Code_Instruction_GET => Code_Instruction_GET
)
port map( CLK => CLK,
RST => RST,
STD_IN => STD_IN,
STD_OUT => STD_OUT,
IN_2_A => A_to_2,
IN_2_B => B_to_2,
IN_2_C => C_to_2,
@ -247,14 +274,19 @@ begin
Z => Z,
C => C
);
instance_Etage4 : Etage4_Memoire
generic map( Nb_bits => Nb_bits,
Mem_size => Memoire_Size,
Instruction_bus_size => Instruction_Bus_Size,
Mem_EBP_size => Memoire_Adresses_Retour_Size,
Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,
Bits_Controle_LC => Bits_Controle_LC_4,
Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT
Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT,
Code_Instruction_CALL => Code_Instruction_CALL,
Code_Instruction_RET => Code_Instruction_RET
)
port map( CLK => CLK,
RST => RST,

69
Processeur.srcs/sources_1/new/System.vhd
View file

@ -33,35 +33,54 @@ use IEEE.STD_LOGIC_1164.ALL;
entity System is
Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
flag : out STD_LOGIC_VECTOR (3 downto 0);
sw : in STD_LOGIC_VECTOR (15 downto 0);
sw : in STD_LOGIC_VECTOR (7 downto 0);
btnC : in STD_LOGIC;
btnL : in STD_LOGIC;
btnR : in STD_LOGIC);
CLK : STD_LOGIC);
end System;
architecture Structural of System is
component ALU
Generic (Nb_bits : Natural);
Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
OP : in STD_LOGIC_VECTOR (1 downto 0);
S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC);
component Pipeline is
Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3;
Memoire_Instruction_Size : Natural := 8;
Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16;
Memoire_Size : Natural := 32;
Memoire_Adresses_Retour_Size : Natural := 16;
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
Port (CLK : STD_LOGIC;
RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
signal aux: STD_LOGIC_VECTOR (1 downto 0);
signal aux4: STD_LOGIC;
signal aux5: STD_LOGIC;
signal aux6: STD_LOGIC;
signal aux7: STD_LOGIC;
component Clock_Divider is
Port ( CLK_IN : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end component;
signal my_RST : STD_LOGIC;
signal my_CLK : STD_LOGIC;
signal buff_CLK : STD_LOGIC;
begin
aux <= "01" when btnC = '1' else
"10" when btnR = '1' else
"11" when btnL = '1' else
"00";
flag <= aux4 & aux5 & aux6 & aux7;
My_ALU: ALU generic map (Nb_bits => 8) port map(sw (15 downto 8), sw (7 downto 0), aux, led, aux4, aux5, aux6, aux7);
clk_div : Clock_Divider
port map (CLK_IN => CLK,
CLK_OUT => buff_CLK);
clk_div_2 : Clock_Divider
port map (CLK_IN => buff_CLK,
CLK_OUT => my_CLK);
instance : Pipeline
port map (CLK => my_CLK,
RST => my_RST,
STD_IN => sw,
STD_OUT => led);
my_RST <= '0' when btnC = '1' else
'1';
end Structural;

14
Processeur.xpr
View file

@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Processeur/Processeur.xpr">
<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/>
@ -32,7 +32,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="145"/>
<Option Name="WTXSimLaunchSim" Val="176"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -133,6 +133,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="System"/>
@ -246,6 +252,7 @@
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
</Config>
</FileSet>
</FileSets>
@ -276,7 +283,7 @@
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
@ -289,6 +296,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>

161
vivado.jou
View file

@ -2,159 +2,12 @@
# Vivado v2016.4 (64-bit)
# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
# Start of session at: Mon Apr 19 10:14:33 2021
# Process ID: 6416
# Current directory: C:/Users/Hp/Documents/Processeur
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16404 C:\Users\Hp\Documents\Processeur\Processeur.xpr
# Log file: C:/Users/Hp/Documents/Processeur/vivado.log
# Journal file: C:/Users/Hp/Documents/Processeur\vivado.jou
# Start of session at: Mon May 03 15:56:37 2021
# Process ID: 5172
# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15260 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Users/Hp/Documents/Processeur/Processeur.xpr
launch_simulation
source Test_LC.tcl
close_sim
launch_simulation
source Test_LC.tcl
add_bp {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} 44
remove_bps -file {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} -line 44
close_sim
launch_simulation
launch_simulation
source Test_LC.tcl
close_sim
launch_simulation
source Test_LC.tcl
close_sim
launch_simulation
source Test_LC.tcl
close_sim
launch_simulation
source Test_LC.tcl
close_sim
launch_simulation
source Test_LC.tcl
close_sim
launch_simulation
source Test_LC.tcl
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd w ]
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd
set_property top Test_Etage3_Calcul [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
launch_simulation
launch_simulation
launch_simulation
launch_simulation
source Test_Etage3_Calcul.tcl
close_sim
launch_simulation
source Test_Etage3_Calcul.tcl
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd w ]
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
set_property top Test_Etage4_Memoire [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
launch_simulation
launch_simulation
source Test_Etage4_Memoire.tcl
set_property top Test_Etage3_Calcul [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
current_sim simulation_10
close_sim
launch_simulation
source Test_Etage3_Calcul.tcl
set_property top Test_Etage4_Memoire [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
current_sim simulation_11
close_sim
launch_simulation
source Test_Etage4_Memoire.tcl
close_sim
launch_simulation
source Test_Etage4_Memoire.tcl
close_sim
launch_simulation
source Test_Etage4_Memoire.tcl
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd w ]
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd
set_property top Test_Etage2_5_Registres [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
launch_simulation
source Test_Etage2_5_Registres.tcl
close_sim
launch_simulation
source Test_Etage2_5_Registres.tcl
close_sim
launch_simulation
source Test_Etage2_5_Registres.tcl
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd w ]
add_files C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd w ]
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd
set_property top Test_Pipeline [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
launch_simulation
launch_simulation
launch_simulation
launch_simulation
source Test_Pipeline.tcl
add_wave {{/Test_Pipeline/instance/Instruction_1_to_2}} {{/Test_Pipeline/instance/Instruction_2_to_3}} {{/Test_Pipeline/instance/Instruction_3_to_4}} {{/Test_Pipeline/instance/Instruction_4_to_5}}
run all
run 10 us
run 10 us
restart
run 10 us
restart
run 10 us
close_sim
launch_simulation
source Test_Pipeline.tcl
restart
run 10 us
close_sim
launch_simulation
current_sim simulation_18
launch_simulation
launch_simulation
launch_simulation
source Test_Pipeline.tcl
restart
run 10 us
close_sim
launch_simulation
source Test_Pipeline.tcl
restart
run 10 us
save_wave_config {C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg}
add_files -fileset sim_1 -norecurse C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
set_property xsim.view C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg [get_filesets sim_1]
close_sim
launch_simulation
source Test_Pipeline.tcl
restart
run 10 us
restart
run 10 us
restart
run 10 us
close_sim
launch_simulation
current_sim simulation_18
launch_simulation
launch_simulation
source Test_Pipeline.tcl
restart
run 10 us
close_sim
launch_simulation
source Test_Pipeline.tcl
restart
run 10 us
close_sim
launch_simulation
source Test_Pipeline.tcl
restart
run 10 us
open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr

4085
vivado.log
View file

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