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Processeur 16 Instructions : NOP, ADD, SUB, MUL, DIV, INF, SUP, EQU, AFC, CPY, LOAD, JMP, JMZ, STORE, CALL, RET (ordre non garanti)

Paul Faure 2 years ago
parent
commit
24bb67c7e3
29 changed files with 7321 additions and 216 deletions
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      Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
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      Processeur.srcs/sim_1/new/TestALU.vhd
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      Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd
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      Processeur.srcs/sources_1/new/ALU.vhd
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      Processeur.srcs/sources_1/new/MUX.vhd
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      Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
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      Processeur.srcs/sources_1/new/MemoireDonnees.vhd
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      Processeur.srcs/sources_1/new/MemoireInstructions.vhd
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      Processeur.srcs/sources_1/new/Pipeline.vhd
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  29. 4072
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Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc View File

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+## This file is a general .xdc for the Basys3 rev B board
2
+## To use it in a project:
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+## - uncomment the lines corresponding to used pins
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+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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+
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+## Clock signal
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+#set_property PACKAGE_PIN W5 [get_ports clk]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports clk]
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+	#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
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+
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+## Switches
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+set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
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+set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
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+set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
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+set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
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+set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
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+set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
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+set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
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+set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
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+set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
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+set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
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+set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
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+set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
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+set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
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+set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
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+set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
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+set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
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+
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+
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+## LEDs
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+set_property PACKAGE_PIN U16 [get_ports {led[0]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
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+set_property PACKAGE_PIN E19 [get_ports {led[1]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
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+set_property PACKAGE_PIN U19 [get_ports {led[2]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
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+set_property PACKAGE_PIN V19 [get_ports {led[3]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
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+set_property PACKAGE_PIN W18 [get_ports {led[4]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
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+set_property PACKAGE_PIN U15 [get_ports {led[5]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
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+set_property PACKAGE_PIN U14 [get_ports {led[6]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
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+set_property PACKAGE_PIN V14 [get_ports {led[7]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
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+#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
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+#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
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+#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
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+#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
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+set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {flag[0]}]
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+set_property PACKAGE_PIN N3 [get_ports {flag[1]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {flag[1]}]
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+set_property PACKAGE_PIN P1 [get_ports {flag[2]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {flag[2]}]
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+set_property PACKAGE_PIN L1 [get_ports {flag[3]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {flag[3]}]
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+
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+
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+##7 segment display
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+#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
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+#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
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+#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
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+#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
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+#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
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+#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
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+#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
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+
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+#set_property PACKAGE_PIN V7 [get_ports dp]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports dp]
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+
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+#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
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+#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
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+#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
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+#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
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+
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+
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+##Buttons
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+set_property PACKAGE_PIN U18 [get_ports btnC]
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+	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
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+#set_property PACKAGE_PIN T18 [get_ports btnU]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
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+set_property PACKAGE_PIN W19 [get_ports btnL]
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+	set_property IOSTANDARD LVCMOS33 [get_ports btnL]
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+set_property PACKAGE_PIN T17 [get_ports btnR]
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+	set_property IOSTANDARD LVCMOS33 [get_ports btnR]
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+#set_property PACKAGE_PIN U17 [get_ports btnD]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
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+
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+
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+
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+##Pmod Header JA
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+##Sch name = JA1
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+#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
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+##Sch name = JA2
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+#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
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+##Sch name = JA3
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+#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
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+##Sch name = JA4
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+#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
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+##Sch name = JA7
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+#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
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+##Sch name = JA8
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+#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
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+##Sch name = JA9
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+#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
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+##Sch name = JA10
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+#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
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+
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+
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+
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+##Pmod Header JB
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+##Sch name = JB1
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+#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
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+##Sch name = JB2
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+#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
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+##Sch name = JB3
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+#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
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+##Sch name = JB4
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+#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
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+##Sch name = JB7
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+#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
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+##Sch name = JB8
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+#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
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+##Sch name = JB9
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+#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
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+##Sch name = JB10
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+#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
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+
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+
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+
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+##Pmod Header JC
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+##Sch name = JC1
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+#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
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+##Sch name = JC2
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+#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
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+##Sch name = JC3
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+#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
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+##Sch name = JC4
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+#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
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+##Sch name = JC7
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+#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
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+##Sch name = JC8
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+#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
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+##Sch name = JC9
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+#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
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+##Sch name = JC10
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+#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
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+
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+
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+##Pmod Header JXADC
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+##Sch name = XA1_P
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+#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
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+##Sch name = XA2_P
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+#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
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+##Sch name = XA3_P
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+#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
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+##Sch name = XA4_P
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+#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
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+##Sch name = XA1_N
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+#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
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+##Sch name = XA2_N
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+#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
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+##Sch name = XA3_N
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+#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
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+##Sch name = XA4_N
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+#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
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+
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+
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+
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+##VGA Connector
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+#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
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+#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
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+#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
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+#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
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+#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
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+#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
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+#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
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+#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
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+#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
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+#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
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+#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
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+#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
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+#set_property PACKAGE_PIN P19 [get_ports Hsync]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
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+#set_property PACKAGE_PIN R19 [get_ports Vsync]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
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+
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+
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+##USB-RS232 Interface
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+#set_property PACKAGE_PIN B18 [get_ports RsRx]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
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+#set_property PACKAGE_PIN A18 [get_ports RsTx]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
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+
272
+
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+##USB HID (PS/2)
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+#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
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+	#set_property PULLUP true [get_ports PS2Clk]
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+#set_property PACKAGE_PIN B17 [get_ports PS2Data]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
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+	#set_property PULLUP true [get_ports PS2Data]
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+
281
+
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+##Quad SPI Flash
283
+##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
284
+##STARTUPE2 primitive.
285
+#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
286
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
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+#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
288
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
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+#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
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+#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
292
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
293
+#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
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+	#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
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+
296
+
297
+## Configuration options, can be used for all designs
298
+set_property CONFIG_VOLTAGE 3.3 [current_design]
299
+set_property CFGBVS VCCO [current_design]

+ 84
- 0
Processeur.srcs/sim_1/new/TestALU.vhd View File

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1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 21:25:53
6
+-- Design Name: 
7
+-- Module Name: TestALU - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity TestALU is
35
+--  Port ( );
36
+end TestALU;
37
+
38
+architecture Behavioral of TestALU is
39
+    component   ALU is
40
+        Generic (Nb_bits : Natural);
41
+        Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
42
+              B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
43
+              OP : in STD_LOGIC_VECTOR (1 downto 0);
44
+              S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
45
+              N : out STD_LOGIC;
46
+              O : out STD_LOGIC;
47
+              Z : out STD_LOGIC;
48
+              C : out STD_LOGIC);
49
+    end component;
50
+    
51
+    signal my_A : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
52
+    signal my_B : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
53
+    signal my_OP : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
54
+    signal my_S : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
55
+    signal my_N : STD_LOGIC := '0';
56
+    signal my_O : STD_LOGIC := '0';
57
+    signal my_Z : STD_LOGIC := '0';
58
+    signal my_C : STD_LOGIC := '0';
59
+    
60
+begin
61
+
62
+    instance : ALU
63
+    generic map (Nb_bits => 16)
64
+    port map (
65
+        A => my_A,
66
+        B => my_B,
67
+        OP => my_OP,
68
+        S => my_S,
69
+        N => my_N,
70
+        O => my_O,
71
+        Z => my_Z,
72
+        C => my_C
73
+    );
74
+    
75
+    process 
76
+    begin
77
+        my_A <= x"0007" after 10 ns, x"00ff" after 100 ns;
78
+        my_B <= x"0008" after 10 ns, x"ff01" after 100 ns;
79
+        my_OP <= "01" after 10 ns, "10" after 30 ns, "11" after 50 ns, "01" after 67 ns, "00" after 100 ns;
80
+        
81
+        wait;
82
+    end process;    
83
+end Behavioral;
84
+

+ 104
- 0
Processeur.srcs/sim_1/new/TestBancRegistres.vhd View File

@@ -0,0 +1,104 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 12:58:02
6
+-- Design Name: 
7
+-- Module Name: TestBancRegistres - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity TestBancRegistres is
35
+--  Port ( );
36
+end TestBancRegistres;
37
+
38
+architecture Behavioral of TestBancRegistres is
39
+    component BancRegistres
40
+        Generic (Nb_bits : Natural;
41
+                 Addr_size : Natural;
42
+                 Nb_regs : Natural);
43
+        Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
44
+               AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
45
+               AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
46
+               W : in STD_LOGIC;
47
+               DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
48
+               RST : in STD_LOGIC;
49
+               CLK : in STD_LOGIC;
50
+               QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
51
+               QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
52
+    end component;
53
+    
54
+    signal my_AddrA : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
55
+    signal my_AddrB : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
56
+    signal my_AddrW : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
57
+    signal my_W : STD_LOGIC := '0';
58
+    signal my_DATA : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
59
+    signal my_RST : STD_LOGIC := '0';
60
+    signal my_CLK : STD_LOGIC := '0';
61
+    signal my_QA : STD_LOGIC_VECTOR (7 downto 0);
62
+    signal my_QB : STD_LOGIC_VECTOR (7 downto 0);
63
+    
64
+    constant CLK_period : time := 10 ns;
65
+    
66
+begin
67
+
68
+    instance : BancRegistres
69
+    generic map (Nb_bits => 8,
70
+                 Addr_size => 2,
71
+                 Nb_regs => 4
72
+    )
73
+    port map (
74
+        AddrA => my_AddrA,
75
+        AddrB => my_AddrB,
76
+        AddrW => my_AddrW,
77
+        W => my_W,
78
+        DATA => my_DATA,
79
+        RST => my_RST,
80
+        CLK => my_CLK,
81
+        QA => my_QA,
82
+        QB => my_QB
83
+    );
84
+			
85
+    CLK_process :process
86
+    begin
87
+        my_CLK <= '0';
88
+        wait for CLK_period/2;
89
+        my_CLK <= '1';
90
+        wait for CLK_period/2;
91
+    end process;
92
+    
93
+    process 
94
+    begin
95
+        my_RST <= '1' after 0 ns, '0' after 100 ns;
96
+        my_AddrA <= "11" after 20 ns, "00" after 50 ns;
97
+        my_AddrB <= "11" after 30 ns;
98
+        my_AddrW <= "11" after 10 ns, "00" after 50 ns;
99
+        my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 60 ns, '1' after 110 ns;
100
+        my_DATA <= "01010101" after 10 ns, "11111111" after 50 ns;
101
+        
102
+        wait;
103
+    end process;    
104
+end Behavioral;

+ 99
- 0
Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd View File

@@ -0,0 +1,99 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 12:58:02
6
+-- Design Name: 
7
+-- Module Name: TestMemoireAdressesRetour - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity TestMemoireAdressesRetour is
35
+--  Port ( );
36
+end TestMemoireAdressesRetour;
37
+
38
+architecture Behavioral of TestMemoireAdressesRetour is
39
+    component MemoireAdressesRetour is
40
+    Generic (Nb_bits : Natural;
41
+             Addr_size : Natural;
42
+             Mem_size : Natural);
43
+    Port ( R : in STD_LOGIC;
44
+           W : in STD_LOGIC;
45
+           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
46
+           RST : in STD_LOGIC;
47
+           CLK : in STD_LOGIC;
48
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
49
+           E : out STD_LOGIC;
50
+           F : out STD_LOGIC);
51
+    end component;
52
+    
53
+    signal my_R : STD_LOGIC := '0';
54
+    signal my_W : STD_LOGIC := '0';
55
+    signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
56
+    signal my_RST : STD_LOGIC := '0';
57
+    signal my_CLK : STD_LOGIC := '0';
58
+    signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
59
+    signal my_E : STD_LOGIC;
60
+    signal my_F : STD_LOGIC;
61
+    
62
+    constant CLK_period : time := 10 ns;
63
+    
64
+begin
65
+
66
+    instance : MemoireAdressesRetour
67
+    generic map (Nb_bits => 8,
68
+                 Addr_size => 2,
69
+                 Mem_size => 4
70
+    )
71
+    port map (
72
+        R => my_R,
73
+        W => my_W,
74
+        D_IN => my_D_IN,
75
+        RST => my_RST,
76
+        CLK => my_CLK,
77
+        D_OUT => my_D_OUT,
78
+        E => my_E,
79
+        F => my_F
80
+    );
81
+			
82
+    CLK_process :process
83
+    begin
84
+        my_CLK <= '0';
85
+        wait for CLK_period/2;
86
+        my_CLK <= '1';
87
+        wait for CLK_period/2;
88
+    end process;
89
+    
90
+    process 
91
+    begin
92
+        my_RST <= '1' after 0 ns, '0' after 100 ns;
93
+        my_R <= '1' after 20 ns, '0' after 30 ns;
94
+        my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 90 ns, '0' after 110 ns;
95
+        my_D_IN <= "01010101" after 10 ns, "11100111" after 30 ns, "11111111" after 50 ns, "11111110" after 60 ns, "11111101" after 70 ns, "11111100" after 80 ns;
96
+        
97
+        wait;
98
+    end process;    
99
+end Behavioral;

+ 93
- 0
Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd View File

@@ -0,0 +1,93 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 12:58:02
6
+-- Design Name: 
7
+-- Module Name: TestMemoireDonnees - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity TestMemoireDonnees is
35
+--  Port ( );
36
+end TestMemoireDonnees;
37
+
38
+architecture Behavioral of TestMemoireDonnees is
39
+    component  MemoireDonnees is
40
+       Generic (Nb_bits : Natural;
41
+                Addr_size : Natural;
42
+                Mem_size : Natural);
43
+       Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
44
+              RW : in STD_LOGIC;
45
+              D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
46
+              RST : in STD_LOGIC;
47
+              CLK : in STD_LOGIC;
48
+              D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
49
+    end component;
50
+    
51
+    signal my_Addr : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
52
+    signal my_RW : STD_LOGIC := '1';
53
+    signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
54
+    signal my_RST : STD_LOGIC := '0';
55
+    signal my_CLK : STD_LOGIC := '0';
56
+    signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
57
+    
58
+    constant CLK_period : time := 10 ns;
59
+    
60
+begin
61
+
62
+    instance : MemoireDonnees
63
+    generic map (Nb_bits => 8,
64
+                 Addr_size => 2,
65
+                 Mem_size => 4
66
+    )
67
+    port map (
68
+        Addr => my_Addr,
69
+        RW => my_RW,
70
+        D_IN => my_D_IN,
71
+        RST => my_RST,
72
+        CLK => my_CLK,
73
+        D_OUT => my_D_OUT
74
+    );
75
+			
76
+    CLK_process :process
77
+    begin
78
+        my_CLK <= '0';
79
+        wait for CLK_period/2;
80
+        my_CLK <= '1';
81
+        wait for CLK_period/2;
82
+    end process;
83
+    
84
+    process 
85
+    begin
86
+        my_RST <= '1' after 0 ns, '0' after 100 ns;
87
+        my_RW <= '1' after 0 ns, '0' after 10 ns, '1' after 30 ns;
88
+        my_Addr <= "01" after 10 ns, "10" after 20 ns, "11" after 40 ns, "01" after 70 ns;
89
+        my_D_IN <= "01010101" after 10 ns, "11100111" after 20 ns, "11111111" after 50 ns;
90
+        
91
+        wait;
92
+    end process;    
93
+end Behavioral;

+ 67
- 0
Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd View File

@@ -0,0 +1,67 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 12:58:02
6
+-- Design Name: 
7
+-- Module Name: TestMemoireInstructions - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity TestMemoireInstructions is
35
+--  Port ( );
36
+end TestMemoireInstructions;
37
+
38
+architecture Behavioral of TestMemoireInstructions is
39
+    component MemoireInstructions is
40
+    Generic (Nb_bits : Natural;
41
+             Addr_size : Natural;
42
+             Mem_size : Natural);
43
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
44
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
45
+    end component;
46
+    
47
+    signal my_Addr : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
48
+    signal my_D_OUT : STD_LOGIC_VECTOR (27 downto 0);
49
+    
50
+begin
51
+
52
+    instance : MemoireInstructions
53
+    generic map (Nb_bits => 28,
54
+                 Addr_size => 4,
55
+                 Mem_size => 16
56
+    )
57
+    port map (
58
+        Addr => my_Addr,
59
+        D_OUT => my_D_OUT
60
+    );
61
+    
62
+    process 
63
+    begin
64
+        my_Addr <= "0001" after 10 ns, "0010" after 20 ns, "0011" after 30 ns;        
65
+        wait;
66
+    end process;    
67
+end Behavioral;

+ 121
- 0
Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd View File

@@ -0,0 +1,121 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 19.04.2021 14:31:37
6
+-- Design Name: 
7
+-- Module Name: Test_Etage2_5_Registres - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Etage2_5_Registres is
35
+--  Port ( );
36
+end Test_Etage2_5_Registres;
37
+
38
+architecture Behavioral of Test_Etage2_5_Registres is
39
+    component Etage2_5_Registres is
40
+    Generic ( Nb_bits : Natural;
41
+              Nb_registres : Natural;
42
+              Instruction_bus_size : Natural;
43
+              Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
44
+              Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
45
+    Port ( CLK : in STD_LOGIC;
46
+           RST : in STD_LOGIC;
47
+           IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
48
+           IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
49
+           IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
50
+           IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
51
+           OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
52
+           OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
53
+           OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
54
+           OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
55
+           IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
56
+           IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
57
+           IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
58
+    end component;
59
+    
60
+    signal my_CLK : STD_LOGIC := '0';
61
+    signal my_RST : STD_LOGIC := '1';
62
+    signal my_IN_2_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
63
+    signal my_IN_2_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
64
+    signal my_IN_2_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
65
+    signal my_IN_2_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
66
+    signal my_OUT_2_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
67
+    signal my_OUT_2_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
68
+    signal my_OUT_2_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
69
+    signal my_OUT_2_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
70
+    signal my_IN_5_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
71
+    signal my_IN_5_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
72
+    signal my_IN_5_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
73
+    
74
+    constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (7 downto 0) := "01111110";
75
+    constant Bits_Controle_MUX_2 : STD_LOGIC_VECTOR (7 downto 0) := "01100001";
76
+    
77
+    constant CLK_period : time := 10 ns;
78
+    
79
+begin
80
+
81
+    instance : Etage2_5_Registres
82
+    generic map( Nb_bits => 8,
83
+                 Nb_Registres => 16,
84
+                 Instruction_bus_size => 3,
85
+                 Bits_Controle_LC_5 => Bits_Controle_LC_5,
86
+                 Bits_Controle_MUX_2 => Bits_Controle_MUX_2)
87
+    port map(    CLK => my_CLK,
88
+                 RST => my_RST,
89
+                 IN_2_A => my_IN_2_A,
90
+                 IN_2_B => my_IN_2_B,
91
+                 IN_2_C => my_IN_2_C,
92
+                 IN_2_Instruction => my_IN_2_Instruction,
93
+                 OUT_2_A => my_OUT_2_A,
94
+                 OUT_2_B => my_OUT_2_B,
95
+                 OUT_2_C => my_OUT_2_C,
96
+                 OUT_2_Instruction => my_OUT_2_Instruction,
97
+                 IN_5_A => my_IN_5_A,
98
+                 IN_5_B => my_IN_5_B,
99
+                 IN_5_Instruction => my_IN_5_Instruction);
100
+    
101
+    CLK_process :process
102
+    begin
103
+        my_CLK <= '1';
104
+        wait for CLK_period/2;
105
+        my_CLK <= '0';
106
+        wait for CLK_period/2;
107
+    end process;
108
+    
109
+    process 
110
+    begin     
111
+        my_RST <= '0' after 33 ns;
112
+        my_IN_2_A <= "01011111" after 0 ns;
113
+        my_IN_2_B <= "00000011" after 0 ns, "00000100" after 40 ns;
114
+        my_IN_2_C <= "00000001" after 0 ns, "00000000" after 40 ns;
115
+        my_IN_2_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
116
+        my_IN_5_A <= "00000010" after 0 ns, "00000000" after 10 ns, "00000011" after 20 ns, "00000010" after 30 ns;
117
+        my_IN_5_B <= "11111111" after 0 ns, "11111110" after 10 ns, "11111101" after 20 ns, "11111100" after 30 ns;
118
+        my_IN_5_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
119
+        wait;
120
+    end process;    
121
+end Behavioral;

+ 105
- 0
Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd View File

@@ -0,0 +1,105 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 19.04.2021 11:26:48
6
+-- Design Name: 
7
+-- Module Name: Test_Etage3_Calcul - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Etage3_Calcul is
35
+--  Port ( );
36
+end Test_Etage3_Calcul;
37
+
38
+architecture Behavioral of Test_Etage3_Calcul is
39
+    component Etage3_Calcul is
40
+        Generic ( Nb_bits : Natural;
41
+                  OP_vector_size : Natural;
42
+                  Instruction_bus_size : Natural;
43
+                  Bits_Controle_LC : STD_LOGIC_VECTOR;
44
+                  Bits_Controle_MUX : STD_LOGIC_VECTOR);
45
+        Port ( RST : STD_LOGIC;
46
+               IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
47
+               IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
48
+               IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
49
+               IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
50
+               OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
51
+               OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
52
+               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
53
+               N : out STD_LOGIC;
54
+               O : out STD_LOGIC;
55
+               Z : out STD_LOGIC;
56
+               C : out STD_LOGIC);
57
+    end component;
58
+    
59
+    signal my_RST : STD_LOGIC := '1';
60
+    signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
61
+    signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
62
+    signal my_IN_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
63
+    signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
64
+    signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
65
+    signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
66
+    signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
67
+    signal my_N : STD_LOGIC;
68
+    signal my_O : STD_LOGIC;
69
+    signal my_Z : STD_LOGIC;
70
+    signal my_C : STD_LOGIC;
71
+    
72
+    constant Bits_Controle_LC : STD_LOGIC_VECTOR (15 downto 0) := x"00b4";
73
+    constant Bits_Controle_MUX : STD_LOGIC_VECTOR (7 downto 0) := "11110001";
74
+    
75
+begin
76
+
77
+    instance : Etage3_Calcul
78
+    generic map( Nb_bits => 8,
79
+                 OP_vector_size => 2,
80
+                 Instruction_bus_size => 3,
81
+                 Bits_Controle_LC => Bits_Controle_LC,
82
+                 Bits_Controle_MUX => Bits_Controle_MUX)
83
+    port map(    RST => my_RST,
84
+                 IN_A => my_IN_A,
85
+                 IN_B => my_IN_B,
86
+                 IN_C => my_IN_C,
87
+                 IN_Instruction => my_IN_Instruction,
88
+                 OUT_A => my_OUT_A,
89
+                 OUT_B => my_OUT_B,
90
+                 OUT_Instruction => my_OUT_Instruction,
91
+                 N => my_N,
92
+                 O => my_O,
93
+                 Z => my_Z,
94
+                 C => my_C);
95
+    
96
+    process 
97
+    begin     
98
+        my_IN_A <= "01011111";
99
+        my_IN_B <= "10100110";
100
+        my_IN_C <= "01101101";
101
+        my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
102
+        my_RST <= '0' after 45 ns;
103
+        wait;
104
+    end process;    
105
+end Behavioral;

+ 105
- 0
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd View File

@@ -0,0 +1,105 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 19.04.2021 13:37:04
6
+-- Design Name: 
7
+-- Module Name: Test_Etage4_Memoire - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Etage4_Memoire is
35
+--  Port ( );
36
+end Test_Etage4_Memoire;
37
+
38
+architecture Behavioral of Test_Etage4_Memoire is
39
+    component Etage4_Memoire is
40
+    Generic ( Nb_bits : Natural;
41
+              Mem_size : Natural;
42
+              Instruction_bus_size : Natural;
43
+              Bits_Controle_LC : STD_LOGIC_VECTOR;
44
+              Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
45
+              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
46
+        Port ( CLK : in STD_LOGIC;
47
+               RST : in STD_LOGIC;
48
+               IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
49
+               IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
50
+               IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
51
+               OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
52
+               OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
53
+               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
54
+    end component;
55
+    
56
+    signal my_CLK : STD_LOGIC := '0';
57
+    signal my_RST : STD_LOGIC := '1';
58
+    signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
59
+    signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
60
+    signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
61
+    signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
62
+    signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
63
+    signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
64
+    
65
+    constant Bits_Controle_LC : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
66
+    constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (7 downto 0) := "10111111";
67
+    constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
68
+    
69
+    constant CLK_period : time := 10 ns;
70
+    
71
+begin
72
+
73
+    instance : Etage4_Memoire
74
+    generic map( Nb_bits => 8,
75
+                 Mem_size => 256,
76
+                 Instruction_bus_size => 3,
77
+                 Bits_Controle_LC => Bits_Controle_LC,
78
+                 Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
79
+                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT)
80
+    port map(    CLK => my_CLK,
81
+                 RST => my_RST,
82
+                 IN_A => my_IN_A,
83
+                 IN_B => my_IN_B,
84
+                 IN_Instruction => my_IN_Instruction,
85
+                 OUT_A => my_OUT_A,
86
+                 OUT_B => my_OUT_B,
87
+                 OUT_Instruction => my_OUT_Instruction);
88
+    
89
+    CLK_process :process
90
+    begin
91
+        my_CLK <= '0';
92
+        wait for CLK_period/2;
93
+        my_CLK <= '1';
94
+        wait for CLK_period/2;
95
+    end process;
96
+    
97
+    process 
98
+    begin     
99
+        my_IN_A <= "01011111" after 0 ns, "11111111" after 124 ns;
100
+        my_IN_B <= "10100110" after 0 ns, "01011111" after 124 ns;
101
+        my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns, "110" after 100 ns, "111" after 110 ns, "110" after 120 ns;
102
+        my_RST <= '0' after 125 ns;
103
+        wait;
104
+    end process;    
105
+end Behavioral;

+ 118
- 0
Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd View File

@@ -0,0 +1,118 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 18.04.2021 22:28:40
6
+-- Design Name: 
7
+-- Module Name: Test_Etape1_LectureInstruction - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Etape1_LectureInstruction is
35
+--  Port ( );
36
+end Test_Etape1_LectureInstruction;
37
+
38
+architecture Behavioral of Test_Etape1_LectureInstruction is
39
+    component Etage1_LectureInstruction is
40
+    Generic (Instruction_size_in_memory : Natural;
41
+             Addr_size_mem_instruction : Natural;
42
+             Mem_instruction_size : Natural;
43
+             Nb_bits : Natural;
44
+             Instruction_bus_size : Natural;
45
+             Nb_registres : Natural;
46
+             Mem_adresse_retour_size : Natural;
47
+             Adresse_size_mem_adresse_retour : Natural;
48
+             Instructions_critiques_lecture : STD_LOGIC_VECTOR;
49
+             Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
50
+             Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
51
+             Code_Instruction_JMP : STD_LOGIC_VECTOR;
52
+             Code_Instruction_JMZ : STD_LOGIC_VECTOR;
53
+             Code_Instruction_CALL : STD_LOGIC_VECTOR;
54
+             Code_Instruction_RET : STD_LOGIC_VECTOR);
55
+    Port ( CLK : in STD_LOGIC;
56
+           RST : in STD_LOGIC;
57
+           Z : in STD_LOGIC;
58
+           A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
59
+           B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
60
+           C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
61
+           Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
62
+    end component;
63
+    
64
+    signal my_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
65
+    signal my_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
66
+    signal my_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
67
+    signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
68
+    signal my_CLK : STD_LOGIC := '0';
69
+    signal my_RST : STD_LOGIC := '1';
70
+    signal my_Z : STD_LOGIC := '1';
71
+    
72
+    constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (15 downto 0) := "0000100111111110";
73
+    constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (15 downto 0) := "0000000011111110";
74
+    constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (15 downto 0) := "0000011111111110";
75
+    
76
+    constant CLK_period : time := 10 ns;
77
+    
78
+begin
79
+    instance : Etage1_LectureInstruction
80
+    generic map (Instruction_size_in_memory => 28,
81
+                 Addr_size_mem_instruction => 4,
82
+                 Mem_instruction_size => 16,
83
+                 Nb_bits => 8,
84
+                 Instruction_bus_size => 4,
85
+                 Nb_registres => 16,
86
+                 Mem_adresse_retour_size => 4,
87
+                 Adresse_size_mem_adresse_retour => 2,
88
+                 Instructions_critiques_lecture => Instructions_critiques_lecture,
89
+                 Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
90
+                 Instructions_critiques_ecriture => Instructions_critiques_ecriture,
91
+                 Code_Instruction_JMP => "1100",
92
+                 Code_Instruction_JMZ => "1101",
93
+                 Code_Instruction_CALL => "1110",
94
+                 Code_Instruction_RET => "1111"
95
+    )
96
+    port map (
97
+        CLK => my_CLK,
98
+        RST => my_RST,
99
+        z => my_Z,
100
+        A => my_A,
101
+        B => my_B,
102
+        C => my_C,
103
+        Instruction => my_Instruction
104
+    );
105
+			
106
+    CLK_process :process
107
+    begin
108
+        my_CLK <= '0';
109
+        wait for CLK_period/2;
110
+        my_CLK <= '1';
111
+        wait for CLK_period/2;
112
+    end process;
113
+    
114
+    process 
115
+    begin   
116
+        wait;
117
+    end process;    
118
+end Behavioral;

+ 66
- 0
Processeur.srcs/sim_1/new/Test_LC.vhd View File

@@ -0,0 +1,66 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 17.04.2021 22:43:43
6
+-- Design Name: 
7
+-- Module Name: Test_LC - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_LC is
35
+--  Port ( );
36
+end Test_LC;
37
+
38
+architecture Behavioral of Test_LC is
39
+component LC is
40
+    Generic (Instruction_Vector_Size : Natural;
41
+            Command_size : Natural;
42
+            Bits_Controle : STD_LOGIC_VECTOR);
43
+    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
44
+           Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
45
+end component;
46
+    
47
+    signal my_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
48
+    signal my_Commande : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
49
+    constant Bits_Controle : STD_LOGIC_VECTOR (15 downto 0) := x"c138";
50
+begin
51
+
52
+    instance : LC
53
+    generic map (Instruction_Vector_Size => 3,
54
+                 Command_size => 2,
55
+                 Bits_Controle => Bits_Controle)
56
+    port map (
57
+        Instruction => my_Instruction,
58
+        Commande => my_Commande
59
+    );
60
+    
61
+    process 
62
+    begin
63
+        my_Instruction <= "000" after 1 ns, "001" after 2 ns, "010" after 3 ns, "011" after 4 ns, "100" after 5 ns, "101" after 6 ns, "110" after 7 ns, "111" after 8 ns;
64
+        wait;
65
+    end process;    
66
+end Behavioral;

+ 74
- 0
Processeur.srcs/sim_1/new/Test_MUX.vhd View File

@@ -0,0 +1,74 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 17.04.2021 22:43:43
6
+-- Design Name: 
7
+-- Module Name: Test_MUX - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_MUX is
35
+--  Port ( );
36
+end Test_MUX;
37
+
38
+architecture Behavioral of Test_MUX is
39
+component MUX is
40
+    Generic (Nb_bits : Natural;
41
+            Instruction_Vector_Size : Natural;
42
+            Bits_Controle : STD_LOGIC_VECTOR);
43
+    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
44
+           IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
45
+           IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
46
+           OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
47
+end component;
48
+    
49
+    signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
50
+    signal my_IN1 : STD_LOGIC_VECTOR (15 downto 0);
51
+    signal my_IN2 : STD_LOGIC_VECTOR (15 downto 0);
52
+    signal my_OUTPUT : STD_LOGIC_VECTOR (15 downto 0);
53
+    
54
+begin
55
+
56
+    instance : MUX
57
+    generic map (Nb_bits => 16,
58
+                 Instruction_Vector_Size => 4,
59
+                 Bits_Controle => x"aaaa")
60
+    port map (
61
+        Instruction => my_Instruction,
62
+        IN1 => my_IN1,
63
+        IN2 => my_IN2,
64
+        OUTPUT => my_OUTPUT
65
+    );
66
+    
67
+    process 
68
+    begin
69
+        my_IN1 <= x"abcd";
70
+        my_IN2 <= x"1234";
71
+        my_Instruction <= "0000" after 1 ns, "0001" after 2 ns, "0010" after 3 ns, "0011" after 4 ns, "0100" after 5 ns, "0101" after 6 ns, "0110" after 7 ns, "0111" after 8 ns;
72
+        wait;
73
+    end process;    
74
+end Behavioral;

+ 80
- 0
Processeur.srcs/sim_1/new/Test_Pipeline.vhd View File

@@ -0,0 +1,80 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 19.04.2021 17:35:57
6
+-- Design Name: 
7
+-- Module Name: Test_Pipeline - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Pipeline is
35
+--  Port ( );
36
+end Test_Pipeline;
37
+
38
+architecture Behavioral of Test_Pipeline is
39
+    
40
+    component Pipeline is
41
+    Generic (Nb_bits : Natural := 8;
42
+             Instruction_En_Memoire_Size : Natural := 28;
43
+             Addr_Memoire_Instruction_Size : Natural := 3;
44
+             Memoire_Instruction_Size : Natural := 8;
45
+             Instruction_Bus_Size : Natural := 4;
46
+             Nb_Instructions : Natural := 16;
47
+             Nb_Registres : Natural := 16;
48
+             Memoire_Size : Natural := 8;
49
+             Memoire_Adresses_Retour_Size : Natural := 16;
50
+             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
51
+    Port (CLK : STD_LOGIC;
52
+          RST : STD_LOGIC);
53
+    end component;
54
+    
55
+    signal my_CLK : STD_LOGIC := '0';
56
+    signal my_RST : STD_LOGIC := '1';
57
+    
58
+    constant CLK_period : time := 10 ns;
59
+    
60
+begin
61
+    instance : Pipeline
62
+    generic map (Addr_Memoire_Instruction_Size => 4,
63
+                 Memoire_Instruction_Size => 16)
64
+    port map (CLK => my_CLK,
65
+              RST => my_RST);
66
+              
67
+    CLK_process :process
68
+    begin
69
+        my_CLK <= '1';
70
+        wait for CLK_period/2;
71
+        my_CLK <= '0';
72
+        wait for CLK_period/2;
73
+    end process;
74
+    
75
+    process 
76
+    begin
77
+        my_RST <= '0' after 34 ns, '1' after 57 ns;
78
+        wait;
79
+    end process;
80
+end Behavioral;

+ 85
- 0
Processeur.srcs/sources_1/new/ALU.vhd View File

@@ -0,0 +1,85 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 13.04.2021 10:07:41
6
+-- Design Name: 
7
+-- Module Name: ALU - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+
26
+-- Uncomment the following library declaration if using
27
+-- arithmetic functions with Signed or Unsigned values
28
+use IEEE.NUMERIC_STD.ALL;
29
+
30
+-- Uncomment the following library declaration if instantiating
31
+-- any Xilinx leaf cells in this code.
32
+--library UNISIM;
33
+--use UNISIM.VComponents.all;
34
+
35
+entity ALU is
36
+    Generic (Nb_bits : Natural);
37
+    Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
38
+           B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
39
+           OP : in STD_LOGIC_VECTOR (2 downto 0);
40
+           S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
41
+           N : out STD_LOGIC;
42
+           O : out STD_LOGIC;
43
+           Z : out STD_LOGIC;
44
+           C : out STD_LOGIC);
45
+end ALU;
46
+
47
+architecture Behavioral of ALU is
48
+    signal A9 :  STD_LOGIC_VECTOR (Nb_bits downto 0);
49
+    signal B9 :  STD_LOGIC_VECTOR (Nb_bits downto 0);
50
+    signal ADD :  STD_LOGIC_VECTOR (Nb_bits downto 0);
51
+    signal SUB :  STD_LOGIC_VECTOR (Nb_bits downto 0);
52
+    signal MUL :  STD_LOGIC_VECTOR ((2*Nb_bits)-1 downto 0);
53
+    signal intern_N : STD_LOGIC;
54
+    signal intern_Z : STD_LOGIC;
55
+    constant ZERO_N : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
56
+    constant ZERO_N1 : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
57
+    
58
+    
59
+begin
60
+    A9 <= '0' & A;
61
+    B9 <= '0' & B;
62
+    ADD <= A9 + B9;
63
+    SUB <= A9 - B9;
64
+    MUL <= A * B;    
65
+    
66
+    S <= ADD (Nb_bits-1 downto 0) when OP = "001" else 
67
+         SUB (Nb_bits-1 downto 0) when OP = "010" else 
68
+         MUL (Nb_bits-1 downto 0) when OP = "011" else
69
+         -- Add division
70
+         (0 => intern_N, others => '0') when OP = "101" else
71
+         (0 => '1', others => '0') when OP = "110" and intern_Z = '0' and intern_N = '0' else
72
+         (0 => intern_Z, others => '0') when OP = "111" else
73
+         (others => '0');
74
+         
75
+         
76
+    intern_N <= SUB (Nb_bits);
77
+    intern_Z <= '1' when (SUB = ZERO_N1) else 
78
+         '0';
79
+         
80
+    N <= intern_N;
81
+    O <= '0' when (MUL ((2*Nb_bits)-1 downto Nb_bits) = ZERO_N) else
82
+         '1';
83
+    Z <= intern_Z;
84
+    C <= ADD (Nb_bits);
85
+end Behavioral;

+ 68
- 0
Processeur.srcs/sources_1/new/BancRegistres.vhd View File

@@ -0,0 +1,68 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 15.04.2021 08:23:48
6
+-- Design Name: 
7
+-- Module Name: BancRegistres - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+--use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+--use IEEE.STD_LOGIC_ARITH.ALL;
26
+
27
+-- Uncomment the following library declaration if using
28
+-- arithmetic functions with Signed or Unsigned values
29
+use IEEE.NUMERIC_STD.ALL;
30
+
31
+-- Uncomment the following library declaration if instantiating
32
+-- any Xilinx leaf cells in this code.
33
+--library UNISIM;
34
+--use UNISIM.VComponents.all;
35
+
36
+entity BancRegistres is
37
+    Generic (Nb_bits : Natural;
38
+             Addr_size : Natural;
39
+             Nb_regs : Natural);
40
+    Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
41
+           AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
42
+           AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
43
+           W : in STD_LOGIC;
44
+           DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
45
+           RST : in STD_LOGIC;
46
+           CLK : in STD_LOGIC;
47
+           QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
48
+           QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
49
+end BancRegistres;
50
+
51
+-- ASK MEILLEURE IDEE UN TABLEAU
52
+architecture Behavioral of BancRegistres is
53
+    signal REGISTRES : STD_LOGIC_VECTOR ((Nb_regs * Nb_bits)-1 downto 0) := (others => '0');
54
+begin
55
+    process
56
+    begin
57
+        wait until CLK'event and CLK = '1';
58
+        if (RST = '0') then
59
+            REGISTRES <= (others => '0');
60
+        else 
61
+            if (W = '1') then
62
+                REGISTRES (((to_integer(unsigned(AddrW)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(AddrW))) <= DATA;
63
+            end if;
64
+        end if;
65
+    end process;
66
+    QA <= REGISTRES (((to_integer(unsigned(AddrA)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrA)));
67
+    QB <= REGISTRES (((to_integer(unsigned(AddrB)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrB)));
68
+end Behavioral;

+ 196
- 0
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd View File

@@ -0,0 +1,196 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 18.04.2021 21:19:41
6
+-- Design Name: 
7
+-- Module Name: Etage1_LectureInstruction - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+
26
+-- Uncomment the following library declaration if using
27
+-- arithmetic functions with Signed or Unsigned values
28
+use IEEE.NUMERIC_STD.ALL;
29
+
30
+-- Uncomment the following library declaration if instantiating
31
+-- any Xilinx leaf cells in this code.
32
+--library UNISIM;
33
+--use UNISIM.VComponents.all;
34
+
35
+entity Etage1_LectureInstruction is
36
+    Generic (Instruction_size_in_memory : Natural;
37
+             Addr_size_mem_instruction : Natural;
38
+             Mem_instruction_size : Natural;
39
+             Nb_bits : Natural;
40
+             Instruction_bus_size : Natural;
41
+             Nb_registres : Natural;
42
+             Mem_adresse_retour_size : Natural;
43
+             Adresse_size_mem_adresse_retour : Natural;
44
+             Instructions_critiques_lecture : STD_LOGIC_VECTOR;
45
+             Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
46
+             Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
47
+             Code_Instruction_JMP : STD_LOGIC_VECTOR;
48
+             Code_Instruction_JMZ : STD_LOGIC_VECTOR;
49
+             Code_Instruction_CALL : STD_LOGIC_VECTOR;
50
+             Code_Instruction_RET : STD_LOGIC_VECTOR);
51
+    Port ( CLK : in STD_LOGIC;
52
+           RST : in STD_LOGIC;
53
+           Z : in STD_LOGIC;
54
+           A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
55
+           B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
56
+           C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
57
+           Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
58
+end Etage1_LectureInstruction;
59
+
60
+architecture Behavioral of Etage1_LectureInstruction is
61
+    component MemoireInstructions is
62
+    Generic (Nb_bits : Natural;
63
+             Addr_size : Natural;
64
+             Mem_size : Natural);
65
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
66
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
67
+    end component;
68
+    
69
+    component MemoireAdressesRetour is
70
+        Generic (Nb_bits : Natural;
71
+                 Addr_size : Natural;
72
+                 Mem_size : Natural);
73
+        Port ( R : in STD_LOGIC;
74
+               W : in STD_LOGIC;
75
+               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
76
+               RST : in STD_LOGIC;
77
+               CLK : in STD_LOGIC;
78
+               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
79
+               E : out STD_LOGIC;
80
+               F : out STD_LOGIC);
81
+    end component;
82
+    
83
+    signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
84
+    signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0');
85
+    signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
86
+    
87
+    subtype Registre is integer range -1 to Nb_registres - 1;
88
+    type Tab_registres is array (1 to 4) of Registre;
89
+    signal Tableau : Tab_registres := (others => - 1);
90
+    
91
+    signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
92
+    signal Nul : STD_LOGIC := '0';
93
+    signal R_Aux : STD_LOGIC := '0';
94
+    signal W_Aux : STD_LOGIC := '0';
95
+
96
+    constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0');
97
+    constant Argument_nul : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
98
+    
99
+    signal bulles : boolean := false;
100
+    
101
+    signal compteur : integer := 0;
102
+    
103
+begin
104
+    instance : MemoireInstructions
105
+    generic map (Nb_bits => Instruction_size_in_memory,
106
+                 Addr_size => Addr_size_mem_instruction,
107
+                 Mem_size => Mem_instruction_size)
108
+    port map (Addr => Pointeur_Instruction,
109
+              D_OUT => Instruction_courante);
110
+              
111
+    instance_MemoireAdressesRetour : MemoireAdressesRetour
112
+    generic map (Nb_bits => Addr_size_mem_instruction,
113
+                 Addr_size => Adresse_size_mem_adresse_retour,
114
+                 Mem_size => Mem_adresse_retour_size
115
+    )
116
+    port map ( R => R_Aux,
117
+               W => W_Aux,
118
+               D_IN => Pointeur_instruction_next,
119
+               RST => RST,
120
+               CLK => CLK,
121
+               D_OUT => Adresse_Retour,
122
+               E => Nul,
123
+               F => Nul
124
+    );
125
+
126
+              
127
+    process 
128
+    begin
129
+        wait until CLK'event and CLK = '1';
130
+        if (RST = '0') then
131
+            Tableau <= (others => -1);
132
+            Pointeur_Instruction <= (others => '0');
133
+            C <= Argument_nul;
134
+            B <= Argument_nul;
135
+            A <= Argument_nul;
136
+            Instruction <= Instruction_nulle;
137
+        else
138
+            Tableau(4) <= Tableau(3);
139
+            Tableau(3) <= Tableau(2);
140
+            Tableau(2) <= Tableau(1);
141
+            Tableau(1) <= -1;
142
+            if (not bulles) then
143
+                if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
144
+                    C <= Argument_nul;
145
+                    B <= Argument_nul;
146
+                    A <= Argument_nul;
147
+                    Instruction <= Instruction_nulle;
148
+                    Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
149
+                elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
150
+                    C <= Argument_nul;
151
+                    B <= Argument_nul;
152
+                    A <= Argument_nul;
153
+                    Instruction <= Instruction_nulle;
154
+                    Pointeur_Instruction <= Adresse_Retour;
155
+                elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
156
+                    compteur <= compteur + 1;
157
+                    C <= Argument_nul;
158
+                    B <= Argument_nul;
159
+                    A <= Argument_nul;
160
+                    Instruction <= Instruction_nulle;
161
+                    if (compteur = 2) then
162
+                        if (Z = '1') then
163
+                            Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
164
+                        else 
165
+                            Pointeur_Instruction <= Pointeur_Instruction + 1;
166
+                        end if;
167
+                        compteur <= 0;
168
+                    end if;
169
+                else
170
+                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
171
+                    B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
172
+                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
173
+                    Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
174
+                    if (Instructions_critiques_ecriture(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') then
175
+                        Tableau(1) <= to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)));
176
+                    end if;
177
+                    Pointeur_Instruction <= Pointeur_Instruction + 1;
178
+                end if;
179
+            else 
180
+                C <= Argument_nul;
181
+                B <= Argument_nul;
182
+                A <= Argument_nul;
183
+                Instruction <= Instruction_nulle;
184
+            end if;
185
+        end if;
186
+    end process;
187
+    
188
+    
189
+    -- Condition degueu -> Instruction qui lit dans B et B dans tableau ou instruction qui lit dans C et C dans tableau 
190
+    bulles <= ((Instructions_critiques_lecture(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') and ((to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(1)) or (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(2)) or (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(3)))) or ((Instructions_critiques_lecture_double(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') and ((to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(1)) or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(2)) or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))));
191
+    R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
192
+             '0';
193
+    W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else
194
+             '0';
195
+    Pointeur_instruction_next <= Pointeur_instruction + 1;
196
+end Behavioral;

+ 134
- 0
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd View File

@@ -0,0 +1,134 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 18.04.2021 21:19:41
6
+-- Design Name: 
7
+-- Module Name: Etage2_5_Registres - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Etage2_5_Registres is
35
+    Generic ( Nb_bits : Natural;
36
+              Nb_registres : Natural;
37
+              Instruction_bus_size : Natural;
38
+              Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
39
+              Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
40
+    Port ( CLK : in STD_LOGIC;
41
+           RST : in STD_LOGIC;
42
+           IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
43
+           IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
44
+           IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
45
+           IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
46
+           OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
47
+           OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
48
+           OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
49
+           OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
50
+           IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
51
+           IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
52
+           IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
53
+end Etage2_5_Registres;
54
+
55
+architecture Behavioral of Etage2_5_Registres is
56
+    component BancRegistres is
57
+    Generic (Nb_bits : Natural;
58
+             Addr_size : Natural;
59
+             Nb_regs : Natural);
60
+    Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
61
+           AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
62
+           AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
63
+           W : in STD_LOGIC;
64
+           DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
65
+           RST : in STD_LOGIC;
66
+           CLK : in STD_LOGIC;
67
+           QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
68
+           QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
69
+    end component;
70
+    
71
+    component LC is
72
+        Generic (Instruction_Vector_Size : Natural;
73
+                Command_size : Natural;
74
+                Bits_Controle : STD_LOGIC_VECTOR);
75
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
76
+               Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
77
+    end component;
78
+    
79
+    component MUX is
80
+        Generic (Nb_bits : Natural;
81
+                Instruction_Vector_Size : Natural;
82
+                Bits_Controle : STD_LOGIC_VECTOR);
83
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
84
+               IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
85
+               IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
86
+               OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
87
+    end component;
88
+    
89
+    signal Commande_BancRegistres : STD_LOGIC_VECTOR (0 downto 0) := "0";
90
+    signal Sortie_BancRegistres : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
91
+    signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
92
+    signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
93
+    
94
+begin
95
+    instance_LC : LC
96
+    generic map (Instruction_Vector_Size => Instruction_bus_size,
97
+                 Command_size => 1,
98
+                 Bits_Controle => Bits_Controle_LC_5)
99
+    port map (   Instruction => IN_5_Instruction,
100
+                 Commande => Commande_BancRegistres);
101
+                 
102
+    instance_MUX : MUX
103
+    generic map (Nb_bits => Nb_bits,
104
+                 Instruction_Vector_Size => Instruction_bus_size,
105
+                 Bits_Controle => Bits_Controle_MUX_2)
106
+    port map (   Instruction => IN_2_Instruction,
107
+                 IN1 => IN_2_B,
108
+                 IN2 => Sortie_BancRegistres,
109
+                 OUTPUT => intern_OUT_2_B);
110
+
111
+    instance_BancRegistres : BancRegistres
112
+    generic map (Nb_bits => Nb_bits,
113
+                 Addr_size => Nb_bits,
114
+                 Nb_regs => Nb_registres)
115
+    port map ( AddrA => IN_2_B,
116
+               AddrB => IN_2_C,
117
+               AddrW => IN_5_A,
118
+               W => Commande_BancRegistres(0),
119
+               DATA => IN_5_B,
120
+               RST => RST,
121
+               CLK => CLK,
122
+               QA => Sortie_BancRegistres,
123
+               QB => intern_OUT_2_C);                 
124
+                 
125
+    OUT_2_A <= (others => '0') when RST = '0' else
126
+               IN_2_A;
127
+    OUT_2_B <= (others => '0') when RST = '0' else
128
+               intern_OUT_2_B;
129
+    OUT_2_C <= (others => '0') when RST = '0' else
130
+               intern_OUT_2_C;
131
+    OUT_2_Instruction <= (others => '0') when RST = '0' else
132
+               IN_2_Instruction;    
133
+    
134
+end Behavioral;

+ 136
- 0
Processeur.srcs/sources_1/new/Etage3_Calcul.vhd View File

@@ -0,0 +1,136 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 18.04.2021 21:19:41
6
+-- Design Name: 
7
+-- Module Name: Etage3_Calcul - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Etage3_Calcul is
35
+    Generic ( Nb_bits : Natural;
36
+              Instruction_bus_size : Natural;
37
+              Bits_Controle_LC : STD_LOGIC_VECTOR;
38
+              Bits_Controle_MUX : STD_LOGIC_VECTOR);
39
+    Port ( RST : in STD_LOGIC;
40
+           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
41
+           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
42
+           IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
43
+           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
44
+           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
45
+           OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
46
+           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
47
+           N : out STD_LOGIC;
48
+           O : out STD_LOGIC;
49
+           Z : out STD_LOGIC;
50
+           C : out STD_LOGIC);
51
+end Etage3_Calcul;
52
+
53
+architecture Structural of Etage3_Calcul is
54
+    component ALU is
55
+    Generic (Nb_bits : Natural);
56
+    Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
57
+           B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
58
+           OP : in STD_LOGIC_VECTOR (2 downto 0);
59
+           S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
60
+           N : out STD_LOGIC;
61
+           O : out STD_LOGIC;
62
+           Z : out STD_LOGIC;
63
+           C : out STD_LOGIC);
64
+    end component;
65
+    
66
+    component LC is
67
+        Generic (Instruction_Vector_Size : Natural;
68
+                Command_size : Natural;
69
+                Bits_Controle : STD_LOGIC_VECTOR);
70
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
71
+               Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
72
+    end component;
73
+    
74
+    component MUX is
75
+        Generic (Nb_bits : Natural;
76
+                Instruction_Vector_Size : Natural;
77
+                Bits_Controle : STD_LOGIC_VECTOR);
78
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
79
+               IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
80
+               IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
81
+               OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
82
+    end component;
83
+    
84
+    signal OP_ALU : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
85
+    signal Sortie_ALU : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
86
+    
87
+    signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
88
+    signal intern_N : STD_LOGIC := '0';
89
+    signal intern_O : STD_LOGIC := '0';
90
+    signal intern_Z : STD_LOGIC := '0';
91
+    signal intern_C : STD_LOGIC := '0';
92
+    
93
+    
94
+begin
95
+    instance_LC : LC
96
+    generic map (Instruction_Vector_Size => Instruction_bus_size,
97
+                 Command_size => 3,
98
+                 Bits_Controle => Bits_Controle_LC)
99
+    port map (   Instruction => IN_Instruction,
100
+                 Commande => OP_ALU);
101
+                 
102
+    instance_MUX : MUX
103
+    generic map (Nb_bits => Nb_bits,
104
+                 Instruction_Vector_Size => Instruction_bus_size,
105
+                 Bits_Controle => Bits_Controle_MUX)
106
+    port map (   Instruction => IN_Instruction,
107
+                 IN1 => IN_B,
108
+                 IN2 => Sortie_ALU,
109
+                 OUTPUT => intern_OUT_B);
110
+
111
+    instance_ALU : ALU
112
+    generic map (Nb_bits => Nb_bits)
113
+    port map    (A => IN_B,
114
+                 B => IN_C,
115
+                 OP => OP_ALU,
116
+                 S => Sortie_ALU,
117
+                 N => intern_N,
118
+                 O => intern_O,
119
+                 Z => intern_Z,
120
+                 C => intern_C);
121
+    
122
+    OUT_A <= (others => '0') when RST = '0' else
123
+             IN_A;
124
+    OUT_B <= (others => '0') when RST = '0' else
125
+             intern_OUT_B;
126
+    OUT_Instruction <= (others => '0') when RST = '0' else
127
+             IN_Instruction;
128
+    N <= '0' when RST = '0' else
129
+             intern_N;
130
+    O <= '0' when RST = '0' else
131
+             intern_O;
132
+    Z <= '0' when RST = '0' else
133
+             intern_Z;
134
+    C <= '0' when RST = '0' else
135
+             intern_C;
136
+end Structural;

+ 131
- 0
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd View File

@@ -0,0 +1,131 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 18.04.2021 21:19:41
6
+-- Design Name: 
7
+-- Module Name: Etage4_Memoire - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Etage4_Memoire is
35
+    Generic ( Nb_bits : Natural;
36
+              Mem_size : Natural;
37
+              Instruction_bus_size : Natural;
38
+              Bits_Controle_LC : STD_LOGIC_VECTOR;
39
+              Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
40
+              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
41
+    Port ( CLK : in STD_LOGIC;
42
+           RST : in STD_LOGIC;
43
+           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
44
+           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
45
+           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
46
+           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
47
+           OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
48
+           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
49
+end Etage4_Memoire;
50
+
51
+architecture Structural of Etage4_Memoire is
52
+    component MemoireDonnees is
53
+    Generic (Nb_bits : Natural;
54
+             Addr_size : Natural;
55
+             Mem_size : Natural);
56
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
57
+           RW : in STD_LOGIC;
58
+           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
59
+           RST : in STD_LOGIC;
60
+           CLK : in STD_LOGIC;
61
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
62
+    end component;
63
+    
64
+    component LC is
65
+        Generic (Instruction_Vector_Size : Natural;
66
+                Command_size : Natural;
67
+                Bits_Controle : STD_LOGIC_VECTOR);
68
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
69
+               Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
70
+    end component;
71
+    
72
+    component MUX is
73
+        Generic (Nb_bits : Natural;
74
+                Instruction_Vector_Size : Natural;
75
+                Bits_Controle : STD_LOGIC_VECTOR);
76
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
77
+               IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
78
+               IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
79
+               OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
80
+    end component;
81
+    
82
+    signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
83
+    signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0";
84
+    signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
85
+    signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
86
+    
87
+begin
88
+    instance_LC : LC
89
+    generic map (Instruction_Vector_Size => Instruction_bus_size,
90
+                 Command_size => 1,
91
+                 Bits_Controle => Bits_Controle_LC)
92
+    port map (   Instruction => IN_Instruction,
93
+                 Commande => Commande_MemoireDonnees);
94
+                 
95
+    instance_MUX_IN : MUX
96
+    generic map (Nb_bits => Nb_bits,
97
+                 Instruction_Vector_Size => Instruction_bus_size,
98
+                 Bits_Controle => Bits_Controle_MUX_IN)
99
+    port map (   Instruction => IN_Instruction,
100
+                 IN1 => IN_A,
101
+                 IN2 => IN_B,
102
+                 OUTPUT => Addr_MemoireDonnees);
103
+                 
104
+    instance_MUX_OUT : MUX
105
+    generic map (Nb_bits => Nb_bits,
106
+                 Instruction_Vector_Size => Instruction_bus_size,
107
+                 Bits_Controle => Bits_Controle_MUX_OUT)
108
+    port map (   Instruction => IN_Instruction,
109
+                 IN1 => Sortie_MemoireDonnees,
110
+                 IN2 => IN_B,
111
+                 OUTPUT => intern_OUT_B);
112
+
113
+    instance_MemoireDonnees : MemoireDonnees
114
+    generic map (Nb_bits => Nb_bits,
115
+                 Addr_size => Nb_bits,
116
+                 Mem_size => Mem_size)
117
+    port map ( Addr => Addr_MemoireDonnees,
118
+               RW => Commande_MemoireDonnees(0),
119
+               D_IN => IN_B,
120
+               RST => RST,
121
+               CLK => CLK,
122
+               D_OUT => Sortie_MemoireDonnees);
123
+                 
124
+    OUT_A <= (others => '0') when RST = '0' else
125
+             IN_A;
126
+    OUT_B <= (others => '0') when RST = '0' else
127
+             intern_OUT_B;
128
+    OUT_Instruction <= (others => '0') when RST = '0' else
129
+             IN_Instruction;
130
+
131
+end Structural;

+ 45
- 0
Processeur.srcs/sources_1/new/LC.vhd View File

@@ -0,0 +1,45 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 17.04.2021 21:49:57
6
+-- Design Name: 
7
+-- Module Name: LC - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity LC is
35
+    Generic (Instruction_Vector_Size : Natural;
36
+            Command_size : Natural;
37
+            Bits_Controle : STD_LOGIC_VECTOR);
38
+    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
39
+           Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
40
+end LC;
41
+
42
+architecture Behavioral of LC is
43
+begin
44
+    Commande <= Bits_Controle (((1 + to_integer(unsigned(Instruction))) * Command_size - 1) downto (Command_size * to_integer(unsigned(Instruction))));
45
+end Behavioral;

+ 48
- 0
Processeur.srcs/sources_1/new/MUX.vhd View File

@@ -0,0 +1,48 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 17.04.2021 21:49:57
6
+-- Design Name: 
7
+-- Module Name: MUX - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity MUX is
35
+    Generic (Nb_bits : Natural;
36
+            Instruction_Vector_Size : Natural;
37
+            Bits_Controle : STD_LOGIC_VECTOR);
38
+    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
39
+           IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
40
+           IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
41
+           OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
42
+end MUX;
43
+
44
+architecture Behavioral of MUX is
45
+begin
46
+    OUTPUT <= IN1 when (Bits_Controle(to_integer(unsigned(Instruction))) = '1') else 
47
+              IN2;
48
+end Behavioral;

+ 77
- 0
Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd View File

@@ -0,0 +1,77 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 14:35:04
6
+-- Design Name: 
7
+-- Module Name: MemoireAdressesRetour - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+
26
+-- Uncomment the following library declaration if using
27
+-- arithmetic functions with Signed or Unsigned values
28
+use IEEE.NUMERIC_STD.ALL;
29
+
30
+-- Uncomment the following library declaration if instantiating
31
+-- any Xilinx leaf cells in this code.
32
+--library UNISIM;
33
+--use UNISIM.VComponents.all;
34
+
35
+entity MemoireAdressesRetour is
36
+    Generic (Nb_bits : Natural;
37
+             Addr_size : Natural;
38
+             Mem_size : Natural);
39
+    Port ( R : in STD_LOGIC;
40
+           W : in STD_LOGIC;
41
+           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
42
+           RST : in STD_LOGIC;
43
+           CLK : in STD_LOGIC;
44
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
45
+           E : out STD_LOGIC;
46
+           F : out STD_LOGIC);
47
+end MemoireAdressesRetour;
48
+
49
+architecture Behavioral of MemoireAdressesRetour is
50
+    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
51
+    signal Addr : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0');
52
+    constant EMPTY : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0');
53
+    constant FULL : STD_LOGIC_VECTOR (Addr_size downto 0) := (Addr_size => '1', others => '0');
54
+begin
55
+    process
56
+    begin
57
+        wait until CLK'event and CLK = '1';
58
+        if (RST = '0' ) then
59
+            MEMORY <= (others => '0');
60
+            Addr <= (others => '0');
61
+        else
62
+            if (W = '1') then
63
+                MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
64
+                Addr <= Addr + 1;
65
+            elsif (R = '1') then 
66
+                Addr <= Addr - 1;
67
+            end if;
68
+        end if;
69
+    end process;
70
+    E <= '1' when Addr = EMPTY else
71
+         '0';
72
+    F <= '1' when Addr = FULL else
73
+         '0';
74
+         
75
+    D_OUT <= (others => '0') when Addr = EMPTY else
76
+             MEMORY (to_integer(unsigned(Addr)) * Nb_bits - 1 downto Nb_bits * (to_integer(unsigned(Addr)) - 1));
77
+end Behavioral;

+ 62
- 0
Processeur.srcs/sources_1/new/MemoireDonnees.vhd View File

@@ -0,0 +1,62 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 14:35:04
6
+-- Design Name: 
7
+-- Module Name: MemoireDonnees - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity MemoireDonnees is
35
+    Generic (Nb_bits : Natural;
36
+             Addr_size : Natural;
37
+             Mem_size : Natural);
38
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
39
+           RW : in STD_LOGIC;
40
+           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
41
+           RST : in STD_LOGIC;
42
+           CLK : in STD_LOGIC;
43
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
44
+end MemoireDonnees;
45
+
46
+architecture Behavioral of MemoireDonnees is
47
+    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
48
+begin
49
+    process
50
+    begin
51
+        wait until CLK'event and CLK = '1';
52
+        if (RST = '0') then
53
+            MEMORY <= (others => '0');
54
+        else 
55
+            if (RW = '0') then
56
+                MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
57
+            else 
58
+                D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
59
+            end if;
60
+        end if;
61
+    end process;
62
+end Behavioral;

+ 46
- 0
Processeur.srcs/sources_1/new/MemoireInstructions.vhd View File

@@ -0,0 +1,46 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 14:35:04
6
+-- Design Name: 
7
+-- Module Name: MemoireInstructions - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity MemoireInstructions is
35
+    Generic (Nb_bits : Natural;
36
+             Addr_size : Natural;
37
+             Mem_size : Natural);
38
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
39
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
40
+end MemoireInstructions;
41
+
42
+architecture Behavioral of MemoireInstructions is
43
+    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"f000000"&x"7040001"&x"6030001"&x"5020001"&x"9010500"&x"9000300"&x"d010000"&x"2000000"&x"e030000";
44
+begin
45
+    D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
46
+end Behavioral;

+ 290
- 0
Processeur.srcs/sources_1/new/Pipeline.vhd View File

@@ -0,0 +1,290 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 19.04.2021 16:57:41
6
+-- Design Name: 
7
+-- Module Name: Pipeline - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Pipeline is
35
+    Generic (Nb_bits : Natural := 8;
36
+             Instruction_En_Memoire_Size : Natural := 28;
37
+             Addr_Memoire_Instruction_Size : Natural := 3;
38
+             Memoire_Instruction_Size : Natural := 8;
39
+             Instruction_Bus_Size : Natural := 4;
40
+             Nb_Instructions : Natural := 16;
41
+             Nb_Registres : Natural := 16;
42
+             Memoire_Size : Natural := 8;
43
+             Memoire_Adresses_Retour_Size : Natural := 16;
44
+             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
45
+    Port (CLK : STD_LOGIC;
46
+          RST : STD_LOGIC);
47
+end Pipeline;
48
+
49
+architecture Behavioral of Pipeline is
50
+    
51
+    component Etage1_LectureInstruction is
52
+    Generic (Instruction_size_in_memory : Natural;
53
+             Addr_size_mem_instruction : Natural;
54
+             Mem_instruction_size : Natural;
55
+             Nb_bits : Natural;
56
+             Instruction_bus_size : Natural;
57
+             Nb_registres : Natural;
58
+             Mem_adresse_retour_size : Natural;
59
+             Adresse_size_mem_adresse_retour : Natural;
60
+             Instructions_critiques_lecture : STD_LOGIC_VECTOR;
61
+             Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
62
+             Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
63
+             Code_Instruction_JMP : STD_LOGIC_VECTOR;
64
+             Code_Instruction_JMZ : STD_LOGIC_VECTOR;
65
+             Code_Instruction_CALL : STD_LOGIC_VECTOR;
66
+             Code_Instruction_RET : STD_LOGIC_VECTOR);
67
+    Port ( CLK : in STD_LOGIC;
68
+           RST : in STD_LOGIC;
69
+           Z : in STD_LOGIC;
70
+           A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
71
+           B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
72
+           C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
73
+           Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
74
+    end component;
75
+    
76
+    component Etage2_5_Registres is
77
+    Generic ( Nb_bits : Natural;
78
+              Nb_registres : Natural;
79
+              Instruction_bus_size : Natural;
80
+              Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
81
+              Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
82
+    Port ( CLK : in STD_LOGIC;
83
+           RST : in STD_LOGIC;
84
+           IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
85
+           IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
86
+           IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
87
+           IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
88
+           OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
89
+           OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
90
+           OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
91
+           OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
92
+           IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
93
+           IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
94
+           IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
95
+    end component;
96
+    
97
+    component Etage3_Calcul is
98
+    Generic ( Nb_bits : Natural;
99
+              Instruction_bus_size : Natural;
100
+              Bits_Controle_LC : STD_LOGIC_VECTOR;
101
+              Bits_Controle_MUX : STD_LOGIC_VECTOR);
102
+    Port ( RST : in STD_LOGIC;
103
+           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
104
+           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
105
+           IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
106
+           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
107
+           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
108
+           OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
109
+           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
110
+           N : out STD_LOGIC;
111
+           O : out STD_LOGIC;
112
+           Z : out STD_LOGIC;
113
+           C : out STD_LOGIC);
114
+    end component;
115
+        
116
+    component Etage4_Memoire is
117
+        Generic ( Nb_bits : Natural;
118
+                  Mem_size : Natural;
119
+                  Instruction_bus_size : Natural;
120
+                  Bits_Controle_LC : STD_LOGIC_VECTOR;
121
+                  Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
122
+                  Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
123
+        Port ( CLK : in STD_LOGIC;
124
+               RST : in STD_LOGIC;
125
+               IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
126
+               IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
127
+               IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
128
+               OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
129
+               OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
130
+               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
131
+    end component;
132
+    
133
+    signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
134
+    signal A_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
135
+    signal A_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
136
+    signal A_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
137
+    signal A_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
138
+    signal A_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
139
+    signal A_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
140
+    signal A_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
141
+    signal B_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
142
+    signal B_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
143
+    signal B_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
144
+    signal B_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
145
+    signal B_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
146
+    signal B_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
147
+    signal B_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
148
+    signal B_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
149
+    signal C_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
150
+    signal C_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
151
+    signal C_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
152
+    signal C_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
153
+    signal Instruction_from_1 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
154
+    signal Instruction_from_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
155
+    signal Instruction_from_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
156
+    signal Instruction_from_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
157
+    signal Instruction_to_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
158
+    signal Instruction_to_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
159
+    signal Instruction_to_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
160
+    signal Instruction_to_5 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
161
+    signal N : STD_LOGIC := '0';
162
+    signal Z : STD_LOGIC := '0';
163
+    signal O : STD_LOGIC := '0';
164
+    signal C : STD_LOGIC := '0';
165
+    
166
+    constant Bits_Controle_MUX_2 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1101011000000001";
167
+    constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
168
+    constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111100000001";
169
+    constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111011111111111";
170
+    constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111101111111111";
171
+    constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000010000000000";
172
+    constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000011111111110";
173
+    constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1100";
174
+    constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1101";
175
+    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1110";
176
+    constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1111";
177
+    
178
+    constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000100111111110";
179
+    constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000000011111110";
180
+    constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000011111111110";
181
+begin
182
+    instance_Etage1 : Etage1_LectureInstruction
183
+    generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
184
+                 Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
185
+                 Mem_instruction_size => Memoire_Instruction_Size,
186
+                 Nb_bits => Nb_bits,
187
+                 Instruction_bus_size => Instruction_Bus_Size,
188
+                 Nb_registres => Nb_Registres,
189
+                 Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
190
+                 Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
191
+                 Instructions_critiques_lecture => Instructions_critiques_lecture,
192
+                 Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
193
+                 Instructions_critiques_ecriture => Instructions_critiques_ecriture,
194
+                 Code_Instruction_JMP => Code_Instruction_JMP,
195
+                 Code_Instruction_JMZ => Code_Instruction_JMZ,
196
+                 Code_Instruction_CALL => Code_Instruction_CALL,
197
+                 Code_Instruction_RET => Code_Instruction_RET
198
+    )
199
+    port map (
200
+        CLK => CLK,
201
+        RST => RST,
202
+        Z => Z,
203
+        A => A_from_1,
204
+        B => B_from_1,
205
+        C => C_from_1,
206
+        Instruction => Instruction_from_1
207
+    );
208
+    
209
+    instance_Etage2_5 : Etage2_5_Registres
210
+    generic map( Nb_bits => Nb_bits,
211
+                 Nb_Registres => Nb_Registres,
212
+                 Instruction_bus_size => Instruction_Bus_Size,
213
+                 Bits_Controle_LC_5 => Bits_Controle_LC_5,
214
+                 Bits_Controle_MUX_2 => Bits_Controle_MUX_2
215
+    )
216
+    port map(    CLK => CLK,
217
+                 RST => RST,
218
+                 IN_2_A => A_to_2,
219
+                 IN_2_B => B_to_2,
220
+                 IN_2_C => C_to_2,
221
+                 IN_2_Instruction => Instruction_to_2,
222
+                 OUT_2_A => A_from_2,
223
+                 OUT_2_B => B_from_2,
224
+                 OUT_2_C => C_from_2,
225
+                 OUT_2_Instruction => Instruction_from_2,
226
+                 IN_5_A => A_to_5,
227
+                 IN_5_B => B_to_5,
228
+                 IN_5_Instruction => Instruction_to_5
229
+    );
230
+    
231
+    instance_Etage3 : Etage3_Calcul
232
+    generic map( Nb_bits => Nb_bits,
233
+                 Instruction_bus_size => Instruction_Bus_Size,
234
+                 Bits_Controle_LC => Bits_Controle_LC_3,
235
+                 Bits_Controle_MUX => Bits_Controle_MUX_3
236
+    )
237
+    port map(    RST => RST,
238
+                 IN_A => A_to_3,
239
+                 IN_B => B_to_3,
240
+                 IN_C => C_to_3,
241
+                 IN_Instruction => Instruction_to_3,
242
+                 OUT_A => A_from_3,
243
+                 OUT_B => B_from_3,
244
+                 OUT_Instruction => Instruction_from_3,
245
+                 N => N,
246
+                 O => O,
247
+                 Z => Z,
248
+                 C => C
249
+    );
250
+    
251
+    instance_Etage4 : Etage4_Memoire
252
+    generic map( Nb_bits => Nb_bits,
253
+                 Mem_size => Memoire_Size,
254
+                 Instruction_bus_size => Instruction_Bus_Size,
255
+                 Bits_Controle_LC => Bits_Controle_LC_4,
256
+                 Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
257
+                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT
258
+    )
259
+    port map(    CLK => CLK,
260
+                 RST => RST,
261
+                 IN_A => A_to_4,
262
+                 IN_B => B_to_4,
263
+                 IN_Instruction => Instruction_to_4,
264
+                 OUT_A => A_from_4,
265
+                 OUT_B => B_from_4,
266
+                 OUT_Instruction => Instruction_from_4
267
+    );
268
+
269
+    process
270
+    begin
271
+        wait until CLK'event and CLK = '1';
272
+        A_to_2 <= A_from_1;
273
+        B_to_2 <= B_from_1;
274
+        C_to_2 <= C_from_1;
275
+        Instruction_to_2 <= Instruction_from_1;
276
+        
277
+        A_to_3 <= A_from_2;
278
+        B_to_3 <= B_from_2;
279
+        C_to_3 <= C_from_2;
280
+        Instruction_to_3 <= Instruction_from_2;
281
+
282
+        A_to_4 <= A_from_3;
283
+        B_to_4 <= B_from_3;
284
+        Instruction_to_4 <= Instruction_from_3;
285
+
286
+        A_to_5 <= A_from_4;
287
+        B_to_5 <= B_from_4;
288
+        Instruction_to_5 <= Instruction_from_4;
289
+    end process;        
290
+end Behavioral;

+ 67
- 0
Processeur.srcs/sources_1/new/System.vhd View File

@@ -0,0 +1,67 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 13.04.2021 10:19:15
6
+-- Design Name: 
7
+-- Module Name: System - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity System is
35
+    Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
36
+           flag : out STD_LOGIC_VECTOR (3 downto 0);
37
+           sw : in STD_LOGIC_VECTOR (15 downto 0);
38
+           btnC : in STD_LOGIC;
39
+           btnL : in STD_LOGIC;
40
+           btnR : in STD_LOGIC);
41
+end System;
42
+
43
+architecture Structural of System is
44
+    component ALU
45
+        Generic (Nb_bits : Natural);
46
+        Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
47
+               B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
48
+               OP : in STD_LOGIC_VECTOR (1 downto 0);
49
+               S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
50
+               N : out STD_LOGIC;
51
+               O : out STD_LOGIC;
52
+               Z : out STD_LOGIC;
53
+               C : out STD_LOGIC);
54
+    end component;
55
+    signal aux: STD_LOGIC_VECTOR (1 downto 0);
56
+    signal aux4: STD_LOGIC;
57
+    signal aux5: STD_LOGIC;
58
+    signal aux6: STD_LOGIC;
59
+    signal aux7: STD_LOGIC;
60
+begin
61
+    aux <= "01" when btnC = '1' else
62
+           "10" when btnR = '1' else
63
+           "11" when btnL = '1' else
64
+           "00";
65
+    flag <= aux4 & aux5 & aux6 & aux7;
66
+    My_ALU: ALU generic map (Nb_bits => 8) port map(sw (15 downto 8), sw (7 downto 0), aux, led, aux4, aux5, aux6, aux7);
67
+end Structural;

+ 295
- 0
Processeur.xpr View File

@@ -0,0 +1,295 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<!-- Product Version: Vivado v2016.4 (64-bit)              -->
3
+<!--                                                         -->
4
+<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.   -->
5
+
6
+<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Processeur/Processeur.xpr">
7
+  <DefaultLaunch Dir="$PRUNDIR"/>
8
+  <Configuration>
9
+    <Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/>
10
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
11
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
12
+    <Option Name="CompiledLibDirXSim" Val=""/>
13
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
14
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
15
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
16
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
17
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
18
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
19
+    <Option Name="TargetLanguage" Val="VHDL"/>
20
+    <Option Name="SimulatorLanguage" Val="VHDL"/>
21
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
22
+    <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
23
+    <Option Name="ActiveSimSet" Val="sim_1"/>
24
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
25
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
26
+    <Option Name="IPCachePermission" Val="read"/>
27
+    <Option Name="IPCachePermission" Val="write"/>
28
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
29
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
30
+    <Option Name="IPUserFilesDir" Val="$PPRDIR/Processeur.ip_user_files"/>
31
+    <Option Name="IPStaticSourceDir" Val="$PPRDIR/Processeur.ip_user_files/ipstatic"/>
32
+    <Option Name="EnableBDX" Val="FALSE"/>
33
+    <Option Name="DSABoardId" Val="basys3"/>
34
+    <Option Name="DSANumComputeUnits" Val="16"/>
35
+    <Option Name="WTXSimLaunchSim" Val="145"/>
36
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
37
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
38
+    <Option Name="WTIesLaunchSim" Val="0"/>
39
+    <Option Name="WTVcsLaunchSim" Val="0"/>
40
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
41
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
42
+    <Option Name="WTXSimExportSim" Val="0"/>
43
+    <Option Name="WTModelSimExportSim" Val="0"/>
44
+    <Option Name="WTQuestaExportSim" Val="0"/>
45
+    <Option Name="WTIesExportSim" Val="0"/>
46
+    <Option Name="WTVcsExportSim" Val="0"/>
47
+    <Option Name="WTRivieraExportSim" Val="0"/>
48
+    <Option Name="WTActivehdlExportSim" Val="0"/>
49
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
50
+    <Option Name="XSimRadix" Val="hex"/>
51
+    <Option Name="XSimTimeUnit" Val="ns"/>
52
+    <Option Name="XSimArrayDisplayLimit" Val="64"/>
53
+    <Option Name="XSimTraceLimit" Val="65536"/>
54
+  </Configuration>
55
+  <FileSets Version="1" Minor="31">
56
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
57
+      <Filter Type="Srcs"/>
58
+      <File Path="$PSRCDIR/sources_1/new/ALU.vhd">
59
+        <FileInfo>
60
+          <Attr Name="UsedIn" Val="synthesis"/>
61
+          <Attr Name="UsedIn" Val="simulation"/>
62
+        </FileInfo>
63
+      </File>
64
+      <File Path="$PSRCDIR/sources_1/new/System.vhd">
65
+        <FileInfo>
66
+          <Attr Name="UsedIn" Val="synthesis"/>
67
+          <Attr Name="UsedIn" Val="simulation"/>
68
+        </FileInfo>
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+      </File>
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+      <File Path="$PSRCDIR/sources_1/new/BancRegistres.vhd">
71
+        <FileInfo>
72
+          <Attr Name="UsedIn" Val="synthesis"/>
73
+          <Attr Name="UsedIn" Val="simulation"/>
74
+        </FileInfo>
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+      </File>
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+      <File Path="$PSRCDIR/sources_1/new/MemoireAdressesRetour.vhd">
77
+        <FileInfo>
78
+          <Attr Name="UsedIn" Val="synthesis"/>
79
+          <Attr Name="UsedIn" Val="simulation"/>
80
+        </FileInfo>
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+      </File>
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+      <File Path="$PSRCDIR/sources_1/new/MemoireInstructions.vhd">
83
+        <FileInfo>
84
+          <Attr Name="UsedIn" Val="synthesis"/>
85
+          <Attr Name="UsedIn" Val="simulation"/>
86
+        </FileInfo>
87
+      </File>
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+      <File Path="$PSRCDIR/sources_1/new/MemoireDonnees.vhd">
89
+        <FileInfo>
90
+          <Attr Name="UsedIn" Val="synthesis"/>
91
+          <Attr Name="UsedIn" Val="simulation"/>
92
+        </FileInfo>
93
+      </File>
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+      <File Path="$PSRCDIR/sources_1/new/MUX.vhd">
95
+        <FileInfo>
96
+          <Attr Name="UsedIn" Val="synthesis"/>
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+          <Attr Name="UsedIn" Val="simulation"/>
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+        </FileInfo>
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+      </File>
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+      <File Path="$PSRCDIR/sources_1/new/LC.vhd">
101
+        <FileInfo>
102
+          <Attr Name="UsedIn" Val="synthesis"/>
103
+          <Attr Name="UsedIn" Val="simulation"/>
104
+        </FileInfo>
105
+      </File>
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+      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
107
+        <FileInfo>
108
+          <Attr Name="UsedIn" Val="synthesis"/>
109
+          <Attr Name="UsedIn" Val="simulation"/>
110
+        </FileInfo>
111
+      </File>
112
+      <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
113
+        <FileInfo>
114
+          <Attr Name="UsedIn" Val="synthesis"/>
115
+          <Attr Name="UsedIn" Val="simulation"/>
116
+        </FileInfo>
117
+      </File>
118
+      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
119
+        <FileInfo>
120
+          <Attr Name="UsedIn" Val="synthesis"/>
121
+          <Attr Name="UsedIn" Val="simulation"/>
122
+        </FileInfo>
123
+      </File>
124
+      <File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
125
+        <FileInfo>
126
+          <Attr Name="UsedIn" Val="synthesis"/>
127
+          <Attr Name="UsedIn" Val="simulation"/>
128
+        </FileInfo>
129
+      </File>
130
+      <File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
131
+        <FileInfo>
132
+          <Attr Name="UsedIn" Val="synthesis"/>
133
+          <Attr Name="UsedIn" Val="simulation"/>
134
+        </FileInfo>
135
+      </File>
136
+      <Config>
137
+        <Option Name="DesignMode" Val="RTL"/>
138
+        <Option Name="TopModule" Val="System"/>
139
+        <Option Name="TopAutoSet" Val="TRUE"/>
140
+      </Config>
141
+    </FileSet>
142
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
143
+      <Filter Type="Constrs"/>
144
+      <File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc">
145
+        <FileInfo>
146
+          <Attr Name="ImportPath" Val="$PPRDIR/../../../../Xilinx/digilent-xdc-master/Basys-3-Master.xdc"/>
147
+          <Attr Name="ImportTime" Val="1614979917"/>
148
+          <Attr Name="UsedIn" Val="synthesis"/>
149
+          <Attr Name="UsedIn" Val="implementation"/>
150
+        </FileInfo>
151
+      </File>
152
+      <Config>
153
+        <Option Name="ConstrsType" Val="XDC"/>
154
+      </Config>
155
+    </FileSet>
156
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
157
+      <Filter Type="Srcs"/>
158
+      <File Path="$PSRCDIR/sim_1/new/TestMemoireDonnees.vhd">
159
+        <FileInfo>
160
+          <Attr Name="UsedIn" Val="synthesis"/>
161
+          <Attr Name="UsedIn" Val="simulation"/>
162
+        </FileInfo>
163
+      </File>
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+      <File Path="$PSRCDIR/sim_1/new/TestMemoireAdressesRetour.vhd">
165
+        <FileInfo>
166
+          <Attr Name="UsedIn" Val="synthesis"/>
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+          <Attr Name="UsedIn" Val="simulation"/>
168
+        </FileInfo>
169
+      </File>
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+      <File Path="$PSRCDIR/sim_1/new/TestBancRegistres.vhd">
171
+        <FileInfo>
172
+          <Attr Name="UsedIn" Val="synthesis"/>
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+          <Attr Name="UsedIn" Val="simulation"/>
174
+        </FileInfo>
175
+      </File>
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+      <File Path="$PSRCDIR/sim_1/new/TestALU.vhd">
177
+        <FileInfo>
178
+          <Attr Name="UsedIn" Val="synthesis"/>
179
+          <Attr Name="UsedIn" Val="simulation"/>
180
+        </FileInfo>
181
+      </File>
182
+      <File Path="$PSRCDIR/sim_1/new/TestMemoireInstructions.vhd">
183
+        <FileInfo>
184
+          <Attr Name="UsedIn" Val="synthesis"/>
185
+          <Attr Name="UsedIn" Val="simulation"/>
186
+        </FileInfo>
187
+      </File>
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+      <File Path="$PSRCDIR/sim_1/new/Test_LC.vhd">
189
+        <FileInfo>
190
+          <Attr Name="UsedIn" Val="synthesis"/>
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+          <Attr Name="UsedIn" Val="simulation"/>
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+        </FileInfo>
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+      </File>
194
+      <File Path="$PSRCDIR/sim_1/new/Test_MUX.vhd">
195
+        <FileInfo>
196
+          <Attr Name="UsedIn" Val="synthesis"/>
197
+          <Attr Name="UsedIn" Val="simulation"/>
198
+        </FileInfo>
199
+      </File>
200
+      <File Path="$PSRCDIR/sim_1/new/Test_Etape1_LectureInstruction.vhd">
201
+        <FileInfo>
202
+          <Attr Name="UsedIn" Val="synthesis"/>
203
+          <Attr Name="UsedIn" Val="simulation"/>
204
+        </FileInfo>
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+      </File>
206
+      <File Path="$PSRCDIR/sim_1/new/Test_Etage3_Calcul.vhd">
207
+        <FileInfo>
208
+          <Attr Name="UsedIn" Val="synthesis"/>
209
+          <Attr Name="UsedIn" Val="simulation"/>
210
+        </FileInfo>
211
+      </File>
212
+      <File Path="$PSRCDIR/sim_1/new/Test_Etage4_Memoire.vhd">
213
+        <FileInfo>
214
+          <Attr Name="UsedIn" Val="synthesis"/>
215
+          <Attr Name="UsedIn" Val="simulation"/>
216
+        </FileInfo>
217
+      </File>
218
+      <File Path="$PSRCDIR/sim_1/new/Test_Etage2_5_Registres.vhd">
219
+        <FileInfo>
220
+          <Attr Name="UsedIn" Val="synthesis"/>
221
+          <Attr Name="UsedIn" Val="simulation"/>
222
+        </FileInfo>
223
+      </File>
224
+      <File Path="$PSRCDIR/sim_1/new/Test_Pipeline.vhd">
225
+        <FileInfo>
226
+          <Attr Name="UsedIn" Val="synthesis"/>
227
+          <Attr Name="UsedIn" Val="simulation"/>
228
+        </FileInfo>
229
+      </File>
230
+      <File Path="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg">
231
+        <FileInfo>
232
+          <Attr Name="UsedIn" Val="simulation"/>
233
+        </FileInfo>
234
+      </File>
235
+      <File Path="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg">
236
+        <FileInfo>
237
+          <Attr Name="UsedIn" Val="simulation"/>
238
+        </FileInfo>
239
+      </File>
240
+      <Config>
241
+        <Option Name="DesignMode" Val="RTL"/>
242
+        <Option Name="TopModule" Val="Test_Pipeline"/>
243
+        <Option Name="TopLib" Val="xil_defaultlib"/>
244
+        <Option Name="TransportPathDelay" Val="0"/>
245
+        <Option Name="TransportIntDelay" Val="0"/>
246
+        <Option Name="SrcSet" Val="sources_1"/>
247
+        <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
248
+        <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
249
+      </Config>
250
+    </FileSet>
251
+  </FileSets>
252
+  <Simulators>
253
+    <Simulator Name="XSim">
254
+      <Option Name="Description" Val="Vivado Simulator"/>
255
+      <Option Name="CompiledLib" Val="0"/>
256
+    </Simulator>
257
+    <Simulator Name="ModelSim">
258
+      <Option Name="Description" Val="ModelSim Simulator"/>
259
+    </Simulator>
260
+    <Simulator Name="Questa">
261
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
262
+    </Simulator>
263
+    <Simulator Name="Riviera">
264
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
265
+    </Simulator>
266
+    <Simulator Name="ActiveHDL">
267
+      <Option Name="Description" Val="Active-HDL Simulator"/>
268
+    </Simulator>
269
+  </Simulators>
270
+  <Runs Version="1" Minor="10">
271
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
272
+      <Strategy Version="1" Minor="2">
273
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
274
+        <Step Id="synth_design"/>
275
+      </Strategy>
276
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
277
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
278
+    </Run>
279
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
280
+      <Strategy Version="1" Minor="2">
281
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
282
+        <Step Id="init_design"/>
283
+        <Step Id="opt_design"/>
284
+        <Step Id="power_opt_design"/>
285
+        <Step Id="place_design"/>
286
+        <Step Id="post_place_power_opt_design"/>
287
+        <Step Id="phys_opt_design"/>
288
+        <Step Id="route_design"/>
289
+        <Step Id="post_route_phys_opt_design"/>
290
+        <Step Id="write_bitstream"/>
291
+      </Strategy>
292
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
293
+    </Run>
294
+  </Runs>
295
+</Project>

+ 154
- 68
vivado.jou View File

@@ -2,73 +2,159 @@
2 2
 # Vivado v2016.4 (64-bit)
3 3
 # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4 4
 # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Wed Apr 14 08:09:08 2021
6
-# Process ID: 4032
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
8
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6828 C:\Users\Hp\Documents\Compteur8BitsBasys3\Compteur8BitsBasys3.xpr
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-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
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-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
5
+# Start of session at: Mon Apr 19 10:14:33 2021
6
+# Process ID: 6416
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+# Current directory: C:/Users/Hp/Documents/Processeur
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+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16404 C:\Users\Hp\Documents\Processeur\Processeur.xpr
9
+# Log file: C:/Users/Hp/Documents/Processeur/vivado.log
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+# Journal file: C:/Users/Hp/Documents/Processeur\vivado.jou
11 11
 #-----------------------------------------------------------
12 12
 start_gui
13
-open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr
14
-launch_runs synth_1 -jobs 2
15
-wait_on_run synth_1
16
-launch_runs impl_1 -jobs 2
17
-wait_on_run impl_1
18
-remove_files  -fileset sim_1 C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
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-file delete -force C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
20
-reset_run impl_1
21
-launch_runs impl_1 -jobs 2
22
-wait_on_run impl_1
23
-launch_runs impl_1 -to_step write_bitstream -jobs 2
24
-wait_on_run impl_1
25
-open_hw
26
-connect_hw_server
27
-open_hw_target
28
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
29
-current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
30
-refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
31
-set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
32
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
33
-program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
34
-refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
35
-reset_run synth_1
36
-launch_runs synth_1 -jobs 2
37
-wait_on_run synth_1
38
-reset_run synth_1
39
-launch_runs synth_1 -jobs 2
40
-wait_on_run synth_1
41
-launch_runs impl_1 -jobs 2
42
-wait_on_run impl_1
43
-reset_run synth_1
44
-launch_runs synth_1 -jobs 2
45
-wait_on_run synth_1
46
-launch_runs impl_1 -jobs 2
47
-wait_on_run impl_1
48
-reset_run synth_1
49
-launch_runs synth_1 -jobs 2
50
-wait_on_run synth_1
51
-launch_runs impl_1 -jobs 2
52
-wait_on_run impl_1
53
-reset_run synth_1
54
-launch_runs synth_1 -jobs 2
55
-wait_on_run synth_1
56
-launch_runs impl_1 -jobs 2
57
-wait_on_run impl_1
58
-launch_runs impl_1 -to_step write_bitstream -jobs 2
59
-wait_on_run impl_1
60
-set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
61
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
62
-program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
63
-refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
64
-reset_run synth_1
65
-launch_runs synth_1 -jobs 2
66
-wait_on_run synth_1
67
-launch_runs impl_1 -jobs 2
68
-wait_on_run impl_1
69
-launch_runs impl_1 -to_step write_bitstream -jobs 2
70
-wait_on_run impl_1
71
-set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
72
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
73
-program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
74
-refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
13
+open_project C:/Users/Hp/Documents/Processeur/Processeur.xpr
14
+launch_simulation
15
+source Test_LC.tcl
16
+close_sim
17
+launch_simulation
18
+source Test_LC.tcl
19
+add_bp {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} 44
20
+remove_bps -file {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} -line 44
21
+close_sim
22
+launch_simulation
23
+launch_simulation
24
+source Test_LC.tcl
25
+close_sim
26
+launch_simulation
27
+source Test_LC.tcl
28
+close_sim
29
+launch_simulation
30
+source Test_LC.tcl
31
+close_sim
32
+launch_simulation
33
+source Test_LC.tcl
34
+close_sim
35
+launch_simulation
36
+source Test_LC.tcl
37
+close_sim
38
+launch_simulation
39
+source Test_LC.tcl
40
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
41
+close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd w ]
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+add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd
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+set_property top Test_Etage3_Calcul [get_filesets sim_1]
44
+set_property top_lib xil_defaultlib [get_filesets sim_1]
45
+launch_simulation
46
+launch_simulation
47
+launch_simulation
48
+launch_simulation
49
+source Test_Etage3_Calcul.tcl
50
+close_sim
51
+launch_simulation
52
+source Test_Etage3_Calcul.tcl
53
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
54
+close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd w ]
55
+add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
56
+set_property top Test_Etage4_Memoire [get_filesets sim_1]
57
+set_property top_lib xil_defaultlib [get_filesets sim_1]
58
+launch_simulation
59
+launch_simulation
60
+source Test_Etage4_Memoire.tcl
61
+set_property top Test_Etage3_Calcul [get_filesets sim_1]
62
+set_property top_lib xil_defaultlib [get_filesets sim_1]
63
+current_sim simulation_10
64
+close_sim
65
+launch_simulation
66
+source Test_Etage3_Calcul.tcl
67
+set_property top Test_Etage4_Memoire [get_filesets sim_1]
68
+set_property top_lib xil_defaultlib [get_filesets sim_1]
69
+current_sim simulation_11
70
+close_sim
71
+launch_simulation
72
+source Test_Etage4_Memoire.tcl
73
+close_sim
74
+launch_simulation
75
+source Test_Etage4_Memoire.tcl
76
+close_sim
77
+launch_simulation
78
+source Test_Etage4_Memoire.tcl
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+set_property SOURCE_SET sources_1 [get_filesets sim_1]
80
+close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd w ]
81
+add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd
82
+set_property top Test_Etage2_5_Registres [get_filesets sim_1]
83
+set_property top_lib xil_defaultlib [get_filesets sim_1]
84
+launch_simulation
85
+source Test_Etage2_5_Registres.tcl
86
+close_sim
87
+launch_simulation
88
+source Test_Etage2_5_Registres.tcl
89
+close_sim
90
+launch_simulation
91
+source Test_Etage2_5_Registres.tcl
92
+close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd w ]
93
+add_files C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd
94
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
95
+close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd w ]
96
+add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd
97
+set_property top Test_Pipeline [get_filesets sim_1]
98
+set_property top_lib xil_defaultlib [get_filesets sim_1]
99
+launch_simulation
100
+launch_simulation
101
+launch_simulation
102
+launch_simulation
103
+source Test_Pipeline.tcl
104
+add_wave {{/Test_Pipeline/instance/Instruction_1_to_2}} {{/Test_Pipeline/instance/Instruction_2_to_3}} {{/Test_Pipeline/instance/Instruction_3_to_4}} {{/Test_Pipeline/instance/Instruction_4_to_5}} 
105
+run all
106
+run 10 us
107
+run 10 us
108
+restart
109
+run 10 us
110
+restart
111
+run 10 us
112
+close_sim
113
+launch_simulation
114
+source Test_Pipeline.tcl
115
+restart
116
+run 10 us
117
+close_sim
118
+launch_simulation
119
+current_sim simulation_18
120
+launch_simulation
121
+launch_simulation
122
+launch_simulation
123
+source Test_Pipeline.tcl
124
+restart
125
+run 10 us
126
+close_sim
127
+launch_simulation
128
+source Test_Pipeline.tcl
129
+restart
130
+run 10 us
131
+save_wave_config {C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg}
132
+add_files -fileset sim_1 -norecurse C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
133
+set_property xsim.view C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg [get_filesets sim_1]
134
+close_sim
135
+launch_simulation
136
+source Test_Pipeline.tcl
137
+restart
138
+run 10 us
139
+restart
140
+run 10 us
141
+restart
142
+run 10 us
143
+close_sim
144
+launch_simulation
145
+current_sim simulation_18
146
+launch_simulation
147
+launch_simulation
148
+source Test_Pipeline.tcl
149
+restart
150
+run 10 us
151
+close_sim
152
+launch_simulation
153
+source Test_Pipeline.tcl
154
+restart
155
+run 10 us
156
+close_sim
157
+launch_simulation
158
+source Test_Pipeline.tcl
159
+restart
160
+run 10 us

+ 4072
- 148
vivado.log
File diff suppressed because it is too large
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