4083 lines
330 KiB
Text
4083 lines
330 KiB
Text
#-----------------------------------------------------------
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# Vivado v2016.4 (64-bit)
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# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
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# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
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# Start of session at: Mon Apr 19 10:14:33 2021
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# Process ID: 6416
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# Current directory: C:/Users/Hp/Documents/Processeur
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16404 C:\Users\Hp\Documents\Processeur\Processeur.xpr
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# Log file: C:/Users/Hp/Documents/Processeur/vivado.log
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# Journal file: C:/Users/Hp/Documents/Processeur\vivado.jou
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#-----------------------------------------------------------
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start_gui
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open_project C:/Users/Hp/Documents/Processeur/Processeur.xpr
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
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open_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 847.191 ; gain = 172.910
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launch_simulation
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-37] Inspecting design source files for 'Test_LC' in fileset 'sim_1'...
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
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"xvhdl -m64 --relax -prj Test_LC_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity ALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity System
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity BancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestBancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
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INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
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Vivado Simulator 2016.4
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Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_LC_behav xil_defaultlib.Test_LC -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling package std.standard
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Compiling package std.textio
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Compiling package ieee.std_logic_1164
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Compiling package ieee.numeric_std
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
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Compiling architecture behavioral of entity xil_defaultlib.test_lc
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Built simulation snapshot Test_LC_behav
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****** Webtalk v2016.4 (64-bit)
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**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
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**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
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** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_LC_behav/webtalk/xsim_webtalk.tcl -notrace
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INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 10:15:26 2021...
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INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
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INFO: [USF-XSim-4] XSim::Simulate design
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
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INFO: [USF-XSim-98] *** Running xsim
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with args "Test_LC_behav -key {Behavioral:sim_1:Functional:Test_LC} -tclbatch {Test_LC.tcl} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
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Vivado Simulator 2016.4
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Time resolution is 1 ps
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source Test_LC.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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ERROR: Slice range direction "downto" does not match prefix slice direction "to"
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Time: 0 ps Iteration: 0 Process: /Test_LC/instance/line__44
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File: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd
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HDL Line: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd:44
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_LC_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 856.492 ; gain = 6.063
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close_sim
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INFO: [Simtcl 6-16] Simulation closed
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launch_simulation
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-37] Inspecting design source files for 'Test_LC' in fileset 'sim_1'...
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
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"xvhdl -m64 --relax -prj Test_LC_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity ALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity System
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity BancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestBancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
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INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
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Vivado Simulator 2016.4
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Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_LC_behav xil_defaultlib.Test_LC -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling package std.standard
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Compiling package std.textio
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Compiling package ieee.std_logic_1164
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Compiling package ieee.numeric_std
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
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Compiling architecture behavioral of entity xil_defaultlib.test_lc
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Built simulation snapshot Test_LC_behav
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****** Webtalk v2016.4 (64-bit)
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**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
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**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
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** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_LC_behav/webtalk/xsim_webtalk.tcl -notrace
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INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 10:18:06 2021...
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INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
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INFO: [USF-XSim-4] XSim::Simulate design
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
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INFO: [USF-XSim-98] *** Running xsim
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with args "Test_LC_behav -key {Behavioral:sim_1:Functional:Test_LC} -tclbatch {Test_LC.tcl} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
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Vivado Simulator 2016.4
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Time resolution is 1 ps
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source Test_LC.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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ERROR: Slice range direction "downto" does not match prefix slice direction "to"
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Time: 0 ps Iteration: 0 Process: /Test_LC/instance/line__44
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File: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd
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HDL Line: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd:44
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_LC_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 886.191 ; gain = 0.000
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add_bp {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} 44
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remove_bps -file {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} -line 44
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close_sim
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INFO: [Simtcl 6-16] Simulation closed
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launch_simulation
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-37] Inspecting design source files for 'Test_LC' in fileset 'sim_1'...
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
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"xvhdl -m64 --relax -prj Test_LC_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity ALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity System
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_LC_behav xil_defaultlib.Test_LC -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
ERROR: [VRFC 10-1378] slice direction differs from its index type range [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd:44]
|
|
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit test_lc in library work failed.
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log'
|
|
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_LC' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_LC_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_LC_behav xil_defaultlib.Test_LC -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_lc
|
|
Built simulation snapshot Test_LC_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_LC_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 10:28:56 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_LC_behav -key {Behavioral:sim_1:Functional:Test_LC} -tclbatch {Test_LC.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_LC.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_LC_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 908.410 ; gain = 6.398
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_LC' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_LC_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_LC_behav xil_defaultlib.Test_LC -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_lc
|
|
Built simulation snapshot Test_LC_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_LC_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 10:29:55 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_LC_behav -key {Behavioral:sim_1:Functional:Test_LC} -tclbatch {Test_LC.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_LC.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_LC_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 908.410 ; gain = 0.000
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_LC' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_LC_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_LC_behav xil_defaultlib.Test_LC -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_lc
|
|
Built simulation snapshot Test_LC_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_LC_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 10:30:41 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_LC_behav -key {Behavioral:sim_1:Functional:Test_LC} -tclbatch {Test_LC.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_LC.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
ERROR: Array sizes do not match, left array has 2 elements, right array has 0 elements
|
|
Time: 0 ps Iteration: 0 Process: /Test_LC/instance/line__44
|
|
File: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd
|
|
|
|
HDL Line: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd:44
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_LC_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 908.410 ; gain = 0.000
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_LC' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_LC_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_LC_behav xil_defaultlib.Test_LC -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_lc
|
|
Built simulation snapshot Test_LC_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_LC_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 10:32:21 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_LC_behav -key {Behavioral:sim_1:Functional:Test_LC} -tclbatch {Test_LC.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_LC.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_LC_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 909.184 ; gain = 0.773
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_LC' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_LC_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_LC_behav xil_defaultlib.Test_LC -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_lc
|
|
Built simulation snapshot Test_LC_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_LC_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 10:44:06 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_LC_behav -key {Behavioral:sim_1:Functional:Test_LC} -tclbatch {Test_LC.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_LC.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
ERROR: Slice range direction "to" does not match prefix slice direction "downto"
|
|
Time: 0 ps Iteration: 0 Process: /Test_LC/instance/line__44
|
|
File: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd
|
|
|
|
HDL Line: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd:44
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_LC_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 916.578 ; gain = 0.000
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_LC' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_LC_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_LC_behav xil_defaultlib.Test_LC -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_lc
|
|
Built simulation snapshot Test_LC_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_LC_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 10:44:45 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_LC_behav -key {Behavioral:sim_1:Functional:Test_LC} -tclbatch {Test_LC.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_LC.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_LC_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 916.578 ; gain = 0.000
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
|
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd w ]
|
|
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd
|
|
set_property top Test_Etage3_Calcul [get_filesets sim_1]
|
|
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage3_Calcul' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage3_Calcul_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
ERROR: [VRFC 10-1412] syntax error near signal [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd:57]
|
|
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd:38]
|
|
INFO: [VRFC 10-240] VHDL file C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd ignored due to errors
|
|
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xvhdl.log'
|
|
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xvhdl.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage3_Calcul' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage3_Calcul_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage3_Calcul_behav xil_defaultlib.Test_Etage3_Calcul -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
ERROR: [VRFC 10-665] expression has 3 elements ; formal commande expects 2 [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd:93]
|
|
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit test_etage3_calcul in library work failed.
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log'
|
|
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage3_Calcul' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage3_Calcul_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage3_Calcul_behav xil_defaultlib.Test_Etage3_Calcul -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
ERROR: [VRFC 10-664] expression has 7 elements ; expected 8 [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd:95]
|
|
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit test_etage3_calcul in library work failed.
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log'
|
|
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage3_Calcul' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage3_Calcul_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage3_Calcul_behav xil_defaultlib.Test_Etage3_Calcul -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_etage3_calcul
|
|
Built simulation snapshot Test_Etage3_Calcul_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Etage3_Calcul_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 11:50:05 2021...
|
|
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 922.711 ; gain = 0.000
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Etage3_Calcul_behav -key {Behavioral:sim_1:Functional:Test_Etage3_Calcul} -tclbatch {Test_Etage3_Calcul.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Etage3_Calcul.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Etage3_Calcul_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 922.711 ; gain = 0.000
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage3_Calcul' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage3_Calcul_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage3_Calcul_behav xil_defaultlib.Test_Etage3_Calcul -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_etage3_calcul
|
|
Built simulation snapshot Test_Etage3_Calcul_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Etage3_Calcul_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 11:51:24 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Etage3_Calcul_behav -key {Behavioral:sim_1:Functional:Test_Etage3_Calcul} -tclbatch {Test_Etage3_Calcul.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Etage3_Calcul.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Etage3_Calcul_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 922.711 ; gain = 0.000
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
|
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd w ]
|
|
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
|
|
set_property top Test_Etage4_Memoire [get_filesets sim_1]
|
|
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage4_Memoire' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage4_Memoire_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage4_Memoire_behav xil_defaultlib.Test_Etage4_Memoire -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
ERROR: [VRFC 10-664] expression has 32 elements ; expected 8 [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd:65]
|
|
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit test_etage4_memoire in library work failed.
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log'
|
|
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage4_Memoire' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage4_Memoire_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage4_Memoire_behav xil_defaultlib.Test_Etage4_Memoire -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_etage4_memoire
|
|
Built simulation snapshot Test_Etage4_Memoire_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Etage4_Memoire_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 13:51:00 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Etage4_Memoire_behav -key {Behavioral:sim_1:Functional:Test_Etage4_Memoire} -tclbatch {Test_Etage4_Memoire.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Etage4_Memoire.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
ERROR: Index 2047 out of bound 2039 downto 0
|
|
Time: 115 ns Iteration: 1 Process: /Test_Etage4_Memoire/instance/instance_MemoireDonnees/line__49
|
|
File: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd
|
|
|
|
HDL Line: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd:58
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Etage4_Memoire_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 938.863 ; gain = 0.000
|
|
set_property top Test_Etage3_Calcul [get_filesets sim_1]
|
|
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
|
current_sim simulation_10
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage3_Calcul' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage3_Calcul_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage3_Calcul_behav xil_defaultlib.Test_Etage3_Calcul -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_etage3_calcul
|
|
Built simulation snapshot Test_Etage3_Calcul_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Etage3_Calcul_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 13:54:55 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Etage3_Calcul_behav -key {Behavioral:sim_1:Functional:Test_Etage3_Calcul} -tclbatch {Test_Etage3_Calcul.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Etage3_Calcul.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Etage3_Calcul_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 956.324 ; gain = 0.000
|
|
set_property top Test_Etage4_Memoire [get_filesets sim_1]
|
|
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
|
current_sim simulation_11
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage4_Memoire' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage4_Memoire_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage4_Memoire_behav xil_defaultlib.Test_Etage4_Memoire -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_etage4_memoire
|
|
Built simulation snapshot Test_Etage4_Memoire_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Etage4_Memoire_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 13:57:03 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Etage4_Memoire_behav -key {Behavioral:sim_1:Functional:Test_Etage4_Memoire} -tclbatch {Test_Etage4_Memoire.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Etage4_Memoire.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
ERROR: Index 2047 out of bound 2039 downto 0
|
|
Time: 115 ns Iteration: 1 Process: /Test_Etage4_Memoire/instance/instance_MemoireDonnees/line__49
|
|
File: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd
|
|
|
|
HDL Line: C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd:56
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Etage4_Memoire_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 980.992 ; gain = 24.668
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage4_Memoire' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage4_Memoire_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage4_Memoire_behav xil_defaultlib.Test_Etage4_Memoire -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_etage4_memoire
|
|
Built simulation snapshot Test_Etage4_Memoire_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Etage4_Memoire_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 14:02:06 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Etage4_Memoire_behav -key {Behavioral:sim_1:Functional:Test_Etage4_Memoire} -tclbatch {Test_Etage4_Memoire.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Etage4_Memoire.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Etage4_Memoire_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 980.992 ; gain = 0.000
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage4_Memoire' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage4_Memoire_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage4_Memoire_behav xil_defaultlib.Test_Etage4_Memoire -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_etage4_memoire
|
|
Built simulation snapshot Test_Etage4_Memoire_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Etage4_Memoire_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 14:05:10 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Etage4_Memoire_behav -key {Behavioral:sim_1:Functional:Test_Etage4_Memoire} -tclbatch {Test_Etage4_Memoire.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Etage4_Memoire.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Etage4_Memoire_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 980.992 ; gain = 0.000
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
|
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd w ]
|
|
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd
|
|
set_property top Test_Etage2_5_Registres [get_filesets sim_1]
|
|
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage2_5_Registres' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage2_5_Registres_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage2_5_Registres_behav xil_defaultlib.Test_Etage2_5_Registres -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_etage2_5_registres
|
|
Built simulation snapshot Test_Etage2_5_Registres_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Etage2_5_Registres_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 16:45:49 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Etage2_5_Registres_behav -key {Behavioral:sim_1:Functional:Test_Etage2_5_Registres} -tclbatch {Test_Etage2_5_Registres.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Etage2_5_Registres.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Etage2_5_Registres_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 980.992 ; gain = 0.000
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage2_5_Registres' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage2_5_Registres_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage2_5_Registres_behav xil_defaultlib.Test_Etage2_5_Registres -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_etage2_5_registres
|
|
Built simulation snapshot Test_Etage2_5_Registres_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Etage2_5_Registres_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 16:49:11 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Etage2_5_Registres_behav -key {Behavioral:sim_1:Functional:Test_Etage2_5_Registres} -tclbatch {Test_Etage2_5_Registres.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Etage2_5_Registres.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Etage2_5_Registres_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 980.992 ; gain = 0.000
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Etage2_5_Registres' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Etage2_5_Registres_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Etage2_5_Registres_behav xil_defaultlib.Test_Etage2_5_Registres -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_etage2_5_registres
|
|
Built simulation snapshot Test_Etage2_5_Registres_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Etage2_5_Registres_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 16:51:09 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Etage2_5_Registres_behav -key {Behavioral:sim_1:Functional:Test_Etage2_5_Registres} -tclbatch {Test_Etage2_5_Registres.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Etage2_5_Registres.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Etage2_5_Registres_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 980.992 ; gain = 0.000
|
|
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd w ]
|
|
add_files C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
|
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd w ]
|
|
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd
|
|
set_property top Test_Pipeline [get_filesets sim_1]
|
|
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
ERROR: [VRFC 10-91] clk_period is not declared [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd:65]
|
|
ERROR: [VRFC 10-2123] 0 definitions of operator "/" match here [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd:65]
|
|
ERROR: [VRFC 10-91] clk_period is not declared [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd:67]
|
|
ERROR: [VRFC 10-2123] 0 definitions of operator "/" match here [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd:67]
|
|
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd:38]
|
|
INFO: [VRFC 10-240] VHDL file C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd ignored due to errors
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xvhdl.log'
|
|
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xvhdl.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
ERROR: [VRFC 10-665] expression has 8 elements ; formal instruction expects 3 [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd:161]
|
|
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit test_pipeline in library work failed.
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log'
|
|
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
ERROR: [VRFC 10-664] expression has 160 elements ; expected 224 [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd:44]
|
|
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit test_pipeline in library work failed.
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log'
|
|
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=28,...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [pipeline_default]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
|
Built simulation snapshot Test_Pipeline_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 17:44:51 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Pipeline.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 980.992 ; gain = 0.000
|
|
add_wave {{/Test_Pipeline/instance/Instruction_1_to_2}} {{/Test_Pipeline/instance/Instruction_2_to_3}} {{/Test_Pipeline/instance/Instruction_3_to_4}} {{/Test_Pipeline/instance/Instruction_4_to_5}}
|
|
run all
|
|
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
|
|
run: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1024.051 ; gain = 0.000
|
|
INFO: [Common 17-344] 'run' was cancelled
|
|
run 10 us
|
|
run 10 us
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=28,...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [pipeline_default]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
|
Built simulation snapshot Test_Pipeline_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 18:07:18 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Pipeline.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1024.051 ; gain = 0.000
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
ERROR: [VRFC 10-664] expression has 8 elements ; expected 16 [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd:153]
|
|
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit test_pipeline in library work failed.
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log'
|
|
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
current_sim simulation_18
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
ERROR: [VRFC 10-664] expression has 64 elements ; expected 16 [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd:154]
|
|
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit test_pipeline in library work failed.
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log'
|
|
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
ERROR: [VRFC 10-664] expression has 444 elements ; expected 448 [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd:44]
|
|
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit test_pipeline in library work failed.
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log'
|
|
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=28,...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
|
Built simulation snapshot Test_Pipeline_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 19 18:43:16 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Pipeline.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1024.051 ; gain = 0.000
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1024.051 ; gain = 0.000
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=28,...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
|
Built simulation snapshot Test_Pipeline_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Wed Apr 21 19:08:34 2021...
|
|
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:09 . Memory (MB): peak = 1024.051 ; gain = 0.000
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Pipeline.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:17 . Memory (MB): peak = 1024.051 ; gain = 0.000
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|
|
save_wave_config {C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg}
|
|
add_files -fileset sim_1 -norecurse C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
|
|
set_property xsim.view C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg [get_filesets sim_1]
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1055.410 ; gain = 0.000
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=28,...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
|
Built simulation snapshot Test_Pipeline_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Wed Apr 21 19:19:29 2021...
|
|
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1055.410 ; gain = 0.000
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
|
|
WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Pipeline.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 1055.410 ; gain = 0.000
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
ERROR: [VRFC 10-704] formal instructions_critiques_lecture_double has no actual or default value [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd:43]
|
|
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit test_pipeline in library work failed.
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log'
|
|
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/elaborate.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
current_sim simulation_18
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
ERROR: [VRFC 10-704] formal instructions_critiques_lecture_double has no actual or default value [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd:170]
|
|
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd:48]
|
|
INFO: [VRFC 10-240] VHDL file C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd ignored due to errors
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xvhdl.log'
|
|
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xvhdl.log' file for more information.
|
|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
|
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=28,...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
|
Built simulation snapshot Test_Pipeline_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Thu Apr 22 11:58:15 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
|
|
WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Pipeline.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1055.410 ; gain = 0.000
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=28,...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
|
Built simulation snapshot Test_Pipeline_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Thu Apr 22 12:08:52 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
|
|
WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Pipeline.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1071.086 ; gain = 0.000
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|
|
close_sim
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/simulate.log
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage2_5_Registres_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage3_Calcul_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Etage4_Memoire_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_LC_behav.wdb
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xelab.pb
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity System
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_MUX
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
Vivado Simulator 2016.4
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
Using 2 slave threads.
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling package std.standard
|
|
Compiling package std.textio
|
|
Compiling package ieee.std_logic_1164
|
|
Compiling package ieee.std_logic_arith
|
|
Compiling package ieee.std_logic_unsigned
|
|
Compiling package ieee.numeric_std
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=28,...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,op_vect...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=3,co...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
|
Built simulation snapshot Test_Pipeline_behav
|
|
|
|
****** Webtalk v2016.4 (64-bit)
|
|
**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
|
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
|
|
INFO: [Common 17-206] Exiting Webtalk at Thu Apr 22 12:18:32 2021...
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
|
|
WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Vivado Simulator 2016.4
|
|
Time resolution is 1 ps
|
|
source Test_Pipeline.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1071.086 ; gain = 0.000
|
|
restart
|
|
INFO: [Simtcl 6-17] Simulation restarted
|
|
run 10 us
|