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Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
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Lacroix Raphael 576b41da4d fixed data path and aleas
2023-05-30 13:38:05 +02:00
..
xsim.dir fixed data path and aleas 2023-05-30 13:38:05 +02:00
compile.log fixed data path and aleas 2023-05-30 13:38:05 +02:00
compile.sh fixed data path and aleas 2023-05-30 13:38:05 +02:00
elaborate.log fixed data path and aleas 2023-05-30 13:38:05 +02:00
elaborate.sh fixed data path and aleas 2023-05-30 13:38:05 +02:00
Pipeline.tcl fixed data path and aleas 2023-05-30 13:38:05 +02:00
Pipeline_behav.wdb fixed data path and aleas 2023-05-30 13:38:05 +02:00
Pipeline_vhdl.prj fixed data path and aleas 2023-05-30 13:38:05 +02:00
simulate.log fixed data path and aleas 2023-05-30 13:38:05 +02:00
simulate.sh fixed data path and aleas 2023-05-30 13:38:05 +02:00
Test_Alu.tcl Added VHDL part of the project 2023-05-29 13:58:26 +02:00
Test_Alu_behav.wdb WIP tried stuff 2023-05-29 21:57:46 +02:00
Test_Alu_vhdl.prj WIP tried stuff 2023-05-29 21:57:46 +02:00
Test_total.tcl fixed data path and aleas 2023-05-30 13:38:05 +02:00
Test_total_behav.wdb fixed data path and aleas 2023-05-30 13:38:05 +02:00
Test_total_vhdl.prj fixed data path and aleas 2023-05-30 13:38:05 +02:00
webtalk.jou fixed data path and aleas 2023-05-30 13:38:05 +02:00
webtalk.log fixed data path and aleas 2023-05-30 13:38:05 +02:00
webtalk_5794.backup.jou fixed data path and aleas 2023-05-30 13:38:05 +02:00
webtalk_5794.backup.log fixed data path and aleas 2023-05-30 13:38:05 +02:00
webtalk_31637.backup.jou Added VHDL part of the project 2023-05-29 13:58:26 +02:00
webtalk_31637.backup.log Added VHDL part of the project 2023-05-29 13:58:26 +02:00
webtalk_32017.backup.jou Added VHDL part of the project 2023-05-29 13:58:26 +02:00
webtalk_32017.backup.log Added VHDL part of the project 2023-05-29 13:58:26 +02:00
webtalk_507565.backup.jou started preparing tests 2023-05-30 00:49:56 +02:00
webtalk_507565.backup.log started preparing tests 2023-05-30 00:49:56 +02:00
webtalk_509586.backup.jou fixed data path and aleas 2023-05-30 13:38:05 +02:00
webtalk_509586.backup.log fixed data path and aleas 2023-05-30 13:38:05 +02:00
xelab.pb fixed data path and aleas 2023-05-30 13:38:05 +02:00
xsim.ini Added VHDL part of the project 2023-05-29 13:58:26 +02:00
xvhdl.log started preparing tests 2023-05-30 00:49:56 +02:00
xvhdl.pb started preparing tests 2023-05-30 00:49:56 +02:00