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added jmp, jmf support, speculative execution of LI DI then flushing, boolean conditions

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This commit is contained in:
Lacroix Raphael 2023-05-30 16:29:31 +02:00
parent 576b41da4d
commit 834c2b01df
33 changed files with 172 additions and 70 deletions
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2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl
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@ -8,4 +8,4 @@ if { [string length $curr_wave] == 0 } {
} }
} }
run 50us run 100us

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb
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54
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
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@ -336,3 +336,57 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Pro
INFO: [VRFC 10-307] analyzing entity DataMemory INFO: [VRFC 10-307] analyzing entity DataMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity DataMemory INFO: [VRFC 10-307] analyzing entity DataMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_total
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
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@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator # Simulator : Xilinx Vivado Simulator
# Description : Script for compiling the simulation design source files # Description : Script for compiling the simulation design source files
# #
# Generated by Vivado on Tue May 30 13:26:07 CEST 2023 # Generated by Vivado on Tue May 30 16:24:18 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# #
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
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@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator # Simulator : Xilinx Vivado Simulator
# Description : Script for elaborating the compiled design # Description : Script for elaborating the compiled design
# #
# Generated by Vivado on Tue May 30 13:26:09 CEST 2023 # Generated by Vivado on Tue May 30 16:24:19 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# #
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
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@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator # Simulator : Xilinx Vivado Simulator
# Description : Script for simulating the design by launching the simulator # Description : Script for simulating the design by launching the simulator
# #
# Generated by Vivado on Tue May 30 13:26:10 CEST 2023 # Generated by Vivado on Tue May 30 16:24:20 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# #
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o
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29
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c
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@ -43,16 +43,18 @@
#define alloca _alloca #define alloca _alloca
#endif #endif
typedef void (*funcp)(char *, char *); typedef void (*funcp)(char *, char *);
extern void execute_89(char*, char *); extern void execute_93(char*, char *);
extern void execute_90(char*, char *);
extern void execute_79(char*, char *);
extern void execute_80(char*, char *); extern void execute_80(char*, char *);
extern void execute_81(char*, char *); extern void execute_81(char*, char *);
extern void execute_82(char*, char *); extern void execute_82(char*, char *);
extern void execute_83(char*, char *); extern void execute_83(char*, char *);
extern void execute_84(char*, char *); extern void execute_84(char*, char *);
extern void execute_85(char*, char *); extern void execute_85(char*, char *);
extern void execute_88(char*, char *); extern void execute_86(char*, char *);
extern void execute_89(char*, char *);
extern void execute_90(char*, char *);
extern void execute_91(char*, char *);
extern void execute_92(char*, char *);
extern void execute_53(char*, char *); extern void execute_53(char*, char *);
extern void execute_54(char*, char *); extern void execute_54(char*, char *);
extern void execute_60(char*, char *); extern void execute_60(char*, char *);
@ -63,21 +65,22 @@ extern void execute_66(char*, char *);
extern void execute_68(char*, char *); extern void execute_68(char*, char *);
extern void execute_70(char*, char *); extern void execute_70(char*, char *);
extern void execute_71(char*, char *); extern void execute_71(char*, char *);
extern void execute_73(char*, char *); extern void execute_72(char*, char *);
extern void execute_75(char*, char *); extern void execute_74(char*, char *);
extern void execute_76(char*, char *); extern void execute_76(char*, char *);
extern void execute_78(char*, char *); extern void execute_77(char*, char *);
extern void execute_87(char*, char *); extern void execute_79(char*, char *);
extern void execute_88(char*, char *);
extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[27] = {(funcp)execute_89, (funcp)execute_90, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_88, (funcp)execute_53, (funcp)execute_54, (funcp)execute_60, (funcp)execute_62, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_68, (funcp)execute_70, (funcp)execute_71, (funcp)execute_73, (funcp)execute_75, (funcp)execute_76, (funcp)execute_78, (funcp)execute_87, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; funcp funcTab[30] = {(funcp)execute_93, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_53, (funcp)execute_54, (funcp)execute_60, (funcp)execute_62, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_68, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_74, (funcp)execute_76, (funcp)execute_77, (funcp)execute_79, (funcp)execute_88, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 27; const int NumRelocateId= 30;
void relocate(char *dp) void relocate(char *dp)
{ {
iki_relocate(dp, "xsim.dir/Test_total_behav/xsim.reloc", (void **)funcTab, 27); iki_relocate(dp, "xsim.dir/Test_total_behav/xsim.reloc", (void **)funcTab, 30);
iki_vhdl_file_variable_register(dp + 23784); iki_vhdl_file_variable_register(dp + 24448);
iki_vhdl_file_variable_register(dp + 23840); iki_vhdl_file_variable_register(dp + 24504);
/*Populate the transaction function pointer field in the whole net structure */ /*Populate the transaction function pointer field in the whole net structure */

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o
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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info
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@ -1,5 +1,5 @@
1685389741 1685389741
1685390103 1685390103
104 147
1 1
aef36ef3a0d94dac9e6058b656907afd aef36ef3a0d94dac9e6058b656907afd

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl
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@ -1,6 +1,6 @@
webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/ webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/
webtalk_register_client -client project webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Tue May 30 13:19:40 2023" -context "software_version_and_target_device" webtalk_add_data -client project -key date_generated -value "Tue May 30 16:24:18 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
@ -14,19 +14,19 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "103" -context "software_version_and_target_device" webtalk_add_data -client project -key project_iteration -value "146" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "2757.340 MHz" -context "user_environment" webtalk_add_data -client project -key cpu_speed -value "2576.095 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment" webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment"
webtalk_register_client -client xsim webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "50 us" -context "xsim\\usage" webtalk_add_data -client xsim -key runtime -value "50 us" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "5" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Time -value "0.02_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "122660_KB" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Memory -value "122664_KB" -context "xsim\\usage"
webtalk_transmit -clientid 653659988 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>" webtalk_transmit -clientid 2613593652 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate webtalk_terminate

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx
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@ -1,6 +1,6 @@
{ {
crc : 5669434041321685966 , crc : 4961576604248800900 ,
ccp_crc : 0 , ccp_crc : 0 ,
cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total" , cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total" ,
buildDate : "Jun 14 2018" , buildDate : "Jun 14 2018" ,

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@ -1,4 +1,4 @@
Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb -simrunnum 0 -socket 58539 Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb -simrunnum 0 -socket 42291
Design successfully loaded Design successfully loaded
Design Loading Memory Usage: 32724 KB (Peak: 32776 KB) Design Loading Memory Usage: 32728 KB (Peak: 32780 KB)
Design Loading CPU Usage: 10 ms Design Loading CPU Usage: 20 ms

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@ -2,13 +2,13 @@
2018.2 2018.2
Jun 14 2018 Jun 14 2018
20:07:38 20:07:38
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685437044,vhdl,,,,test_total,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685451235,vhdl,,,,test_total,,,,,,,,
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685389246,vhdl,,,,alu,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685454749,vhdl,,,,alu,,,,,,,,
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd,1685444515,vhdl,,,,aleacontroler,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd,1685451016,vhdl,,,,aleacontroler,,,,,,,,
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685436168,vhdl,,,,ip,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685436168,vhdl,,,,ip,,,,,,,,
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685439807,vhdl,,,,instructionmemory,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685456575,vhdl,,,,instructionmemory,,,,,,,,
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685445542,vhdl,,,,datamemory,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685445542,vhdl,,,,datamemory,,,,,,,,
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685443285,vhdl,,,,pipeline,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685455519,vhdl,,,,pipeline,,,,,,,,
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685435532,vhdl,,,,registers,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685435532,vhdl,,,,registers,,,,,,,,
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,,
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,,

6
VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd
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@ -39,17 +39,15 @@ architecture Behavioral of test_total is
component Pipeline component Pipeline
Port ( rst : in STD_LOGIC; Clk : in STD_LOGIC); Port (Clk : in STD_LOGIC);
end component; end component;
constant clock_period : time := 10 ns; constant clock_period : time := 10 ns;
signal clock : Std_logic := '0'; signal clock : Std_logic := '0';
signal rst : Std_logic := '1';
begin begin
-- instantiate -- instantiate
Pl : Pipeline PORT MAP ( Pl : Pipeline PORT MAP (
Rst => rst,
Clk => clock Clk => clock
); );
@ -59,6 +57,4 @@ begin
wait for 100ns; wait for 100ns;
end process; end process;
rst <= '0' after 50ns;
end Behavioral; end Behavioral;

22
VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd
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@ -41,7 +41,9 @@ entity ALU is
N : out STD_LOGIC; N : out STD_LOGIC;
O : out STD_LOGIC; O : out STD_LOGIC;
Z : out STD_LOGIC; Z : out STD_LOGIC;
C : out STD_LOGIC); C : out STD_LOGIC;
JumpFlag : inout STD_LOGIC -- 0 false 1 true
);
end ALU; end ALU;
-- Instruction code -- Instruction code
@ -60,7 +62,7 @@ end ALU;
architecture Behavioral of ALU is architecture Behavioral of ALU is
signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000"; signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000";
signal flag : STD_LOGIC := '0';
begin begin
process(A, B, Ctrl_Alu) process(A, B, Ctrl_Alu)
begin begin
@ -68,20 +70,22 @@ begin
O <= '0'; O <= '0';
Z <= '0'; Z <= '0';
C <= '0'; C <= '0';
flag <= JumpFlag;
case Ctrl_Alu is case Ctrl_Alu is
when x"01" => res <= (x"00" & A) + (x"00" & B) ; if (((x"00" & A) + (x"00" & B)) > 255) then C <= '1'; elsif (A+B = 0) then Z <= '1'; end if; -- ADD when x"01" => res <= (x"00" & A) + (x"00" & B) ; if (((x"00" & A) + (x"00" & B)) > 255) then C <= '1'; elsif (A+B = 0) then Z <= '1'; end if; -- ADD
when x"02" => res <= A * B; if (A * B > 255) then O <= '1'; elsif A * B = 0 then Z <= '1'; end if; -- MUL when x"02" => res <= A * B; if (A * B > 255) then O <= '1'; elsif A * B = 0 then Z <= '1'; end if; -- MUL
when x"03" => res <= (x"00" & A) - (x"00" & B) ; if (B > A) then N <= '1'; elsif (B = A) then Z <= '1'; end if; -- SUB when x"03" => res <= (x"00" & A) - (x"00" & B) ; if (B > A) then N <= '1'; elsif (B = A) then Z <= '1'; end if; -- SUB
when x"04" => if (B /= 0) then res <= (x"00" & std_logic_vector(to_unsigned(to_integer(unsigned(A)) / to_integer(unsigned(B)),8))); else res <= x"0000"; end if; -- DIV when x"04" => if (B /= 0) then res <= (x"00" & std_logic_vector(to_unsigned(to_integer(unsigned(A)) / to_integer(unsigned(B)),8))); else res <= x"0000"; end if; -- DIV
when x"09" => if A < B then res <= x"0001"; else res <= x"0000"; end if; when x"09" => if A < B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if;
when x"0A" => if A > B then res <= x"0001"; else res <= x"0000"; end if; when x"0A" => if A > B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if;
when x"0B" => if A = B then res <= x"0001"; else res <= x"0000"; end if; when x"0B" => if A = B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if;
when x"0C" => if A > 0 then res <= x"0000"; else res <= x"0001"; end if; when x"0C" => if A > 0 then res <= x"0000"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if;
when x"0D" => if (A > 0 and B > 0) then res <= x"0001" ; else res <= x"0000"; end if; when x"0D" => if (A > 0 and B > 0) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if;
when x"0E" => if (A > 0 or B > 0) then res <= x"0001" ; else res <= x"0000"; end if; when x"0E" => if (A > 0 or B > 0) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if;
when x"0F" => if ((A > 0 and B = 0) or (A = 0 and B >0)) then res <= x"0001" ; else res <= x"0000"; end if; when x"0F" => if ((A > 0 and B = 0) or (A = 0 and B >0)) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if;
when others => res <= x"0000"; when others => res <= x"0000";
end case; end case;
end process; end process;
JumpFlag <= flag;
S <= res(7 downto 0); S <= res(7 downto 0);
end Behavioral; end Behavioral;

6
VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd
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@ -68,6 +68,10 @@ begin
-- check Registers are the same -- check Registers are the same
((A_Re = B_DI) or (A_Re = C_DI)) ((A_Re = B_DI) or (A_Re = C_DI))
) )
or
(
Op_EX = x"10" or Op_Mem = x"10" or Op_Re = x"10"
)
else '0'; else '0';
end Behavioral; end Behavioral;

7
VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd
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@ -41,7 +41,12 @@ end InstructionMemory;
architecture Behavioral of InstructionMemory is architecture Behavioral of InstructionMemory is
type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0); type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0);
-- signal Mem : Mem_array := ((x"06000200"),(x"08020000"),(x"07000200"),(x"08000000"),(x"06000200"),(x"08020000"),(x"07000000"),(x"07010200"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08010000"),others => (x"ff000000")); -- signal Mem : Mem_array := ((x"06000200"),(x"08020000"),(x"07000200"),(x"08000000"),(x"06000200"),(x"08020000"),(x"07000000"),(x"07010200"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08010000"),others => (x"ff000000"));
signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000600"),(x"08030000"),(x"07000000"),(x"07010300"),(x"02000001"),(x"08040000"),(x"07000400"),(x"08010000"),(x"06000200"),(x"08030000"),(x"07000100"),(x"07010300"),(x"04000001"),(x"08040000"),(x"07000400"),(x"07010000"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000")); -- signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000600"),(x"08030000"),(x"07000000"),(x"07010300"),(x"02000001"),(x"08040000"),(x"07000400"),(x"08010000"),(x"06000200"),(x"08030000"),(x"07000100"),(x"07010300"),(x"04000001"),(x"08040000"),(x"07000400"),(x"07010000"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000"));
-- test JMP signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08030000"),(x"07000300"),(x"08010000"),(x"0F0D0000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08020000"),(x"06000900"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000"));
-- test JMF signal Mem : Mem_array := ((x"06000500"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"100F0000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08000000"),(x"FF000000"),others => (x"ff000000"));
-- test if else signal Mem : Mem_array := ((x"06000200"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"10021000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08000000"),(x"0F140000"),(x"06000C00"),(x"08020000"),(x"07000200"),(x"08000000"),(x"FF000000"),others => (x"ff000000"));
-- test boucle while
signal Mem : Mem_array := ((x"06000500"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"10001B00"),(x"06001400"),(x"08030000"),(x"07000000"),(x"07010300"),(x"09020001"),(x"08040200"),(x"10041B00"),(x"06000200"),(x"08010000"),(x"07000000"),(x"07010100"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08000000"),(x"0F0B0000"),(x"FF000000"),others => (x"ff000000"));
-- signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000")); -- signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000"));
begin begin
Inst_out <= Mem(to_integer(unsigned(Addr))); Inst_out <= Mem(to_integer(unsigned(Addr)));

36
VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
View file

@ -32,7 +32,7 @@ use IEEE.STD_LOGIC_1164.ALL;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity Pipeline is entity Pipeline is
Port (RST : in STD_LOGIC; Clk : in STD_LOGIC); Port (Clk : in STD_LOGIC);
end Pipeline; end Pipeline;
architecture Behavioral of Pipeline is architecture Behavioral of Pipeline is
@ -47,6 +47,7 @@ architecture Behavioral of Pipeline is
end component; end component;
signal IP_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal IP_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal rst : STD_LOGIC := '0';
component InstructionMemory component InstructionMemory
Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
@ -108,12 +109,13 @@ architecture Behavioral of Pipeline is
N : out STD_LOGIC; N : out STD_LOGIC;
O : out STD_LOGIC; O : out STD_LOGIC;
Z : out STD_LOGIC; Z : out STD_LOGIC;
C : out STD_LOGIC C : out STD_LOGIC;
JumpFlag : inout STD_LOGIC
); );
end component; end component;
signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag : STD_LOGIC; signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag, Jump_Flag : STD_LOGIC;
component Stage_Ex_Mem component Stage_Ex_Mem
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
@ -163,11 +165,12 @@ architecture Behavioral of Pipeline is
signal Re_W : STD_LOGIC; signal Re_W : STD_LOGIC;
-- to control jumping and where to jump -- to control jumping and where to jump
signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal jump : STD_LOGIC; signal jump : STD_LOGIC := '0';
signal nop_Cntrl : STD_LOGIC; signal nop_Cntrl : STD_LOGIC;
signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal Di_Op_Final : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
begin begin
-- instructionPointer -- instructionPointer
@ -215,7 +218,7 @@ Stage2 : Stage_Di_Ex PORT MAP (
In_A => Di_A, In_A => Di_A,
In_B => Di_FinalB, In_B => Di_FinalB,
In_C => Di_C2, In_C => Di_C2,
In_Op => Di_Op, In_Op => Di_Op_Final,
Clk => Clk, Clk => Clk,
Out_A => Ex_A, Out_A => Ex_A,
Out_B => Ex_B, Out_B => Ex_B,
@ -231,7 +234,8 @@ Ual : ALU PORT MAP (
N => S_NFlag, N => S_NFlag,
O => S_OFlag, O => S_OFlag,
Z => S_ZFlag, Z => S_ZFlag,
C => S_CFlag); C => S_CFlag,
JumpFlag => Jump_Flag);
-- Stage Ex/Mem -- Stage Ex/Mem
Stage3 : Stage_Ex_Mem PORT MAP ( Stage3 : Stage_Ex_Mem PORT MAP (
@ -332,6 +336,22 @@ CU : AleaControler port map (
CNTRL => nop_Cntrl); CNTRL => nop_Cntrl);
-- in case of alea : replace li(31 downto 24) by NOP -- in case of alea : replace li(31 downto 24) by NOP
OP_LI_DI <= X"ff" when nop_Cntrl='1' else Li(31 downto 24); OP_LI_DI <= X"ff" when (nop_Cntrl='1' or
(Di_Op = x"10" and Jump_Flag = '1')) -- to prevent JMF
else Li(31 downto 24);
-- jump JMP
addr_to_jump <= DI_A when (DI_OP = x"0F") -- JMP
else Di_B when (Di_Op = x"10" and Jump_Flag = '0') -- JMF
else (others => '0');
jump <= '1' when DI_OP = x"0F" -- JMP
or (Di_Op = x"10" and Jump_Flag = '0') -- JMF
else '0';
-- case of JMF not triggering
Di_Op_Final <= x"ff" when (Di_Op = x"10" and Jump_Flag = '1')
else Di_Op;
end Behavioral; end Behavioral;

12
VHDL/ALU/ALU.xpr
View file

@ -33,7 +33,7 @@
<Option Name="DSAVendor" Val="xilinx"/> <Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="basys3"/> <Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="60"/> <Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="136"/> <Option Name="WTXSimLaunchSim" Val="160"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
@ -174,7 +174,7 @@
<Option Name="TransportIntDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/Test_Alu_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/Test_Alu_behav.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="50us"/> <Option Name="xsim.simulate.runtime" Val="100us"/>
</Config> </Config>
</FileSet> </FileSet>
</FileSets> </FileSets>
@ -205,7 +205,9 @@
<Runs Version="1" Minor="10"> <Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -214,7 +216,9 @@
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>

28
VHDL/ALU/Test_Alu_behav.wcfg
View file

@ -10,18 +10,18 @@
</db_ref> </db_ref>
</db_ref_list> </db_ref_list>
<zoom_setting> <zoom_setting>
<ZoomStartTime time="1004500000fs"></ZoomStartTime> <ZoomStartTime time="96855000000fs"></ZoomStartTime>
<ZoomEndTime time="2604500001fs"></ZoomEndTime> <ZoomEndTime time="100020169604fs"></ZoomEndTime>
<Cursor1Time time="1597500000fs"></Cursor1Time> <Cursor1Time time="85411828000fs"></Cursor1Time>
</zoom_setting> </zoom_setting>
<column_width_setting> <column_width_setting>
<NameColumnWidth column_width="171"></NameColumnWidth> <NameColumnWidth column_width="171"></NameColumnWidth>
<ValueColumnWidth column_width="105"></ValueColumnWidth> <ValueColumnWidth column_width="85"></ValueColumnWidth>
</column_width_setting> </column_width_setting>
<WVObjectSize size="9" /> <WVObjectSize size="9" />
<wave_markers> <wave_markers>
<marker label="" time="0" /> <marker label="" time="0" />
<marker label="" time="84000000" /> <marker label="" time="328000000" />
</wave_markers> </wave_markers>
<wvobject type="logic" fp_name="/Test_total/clock"> <wvobject type="logic" fp_name="/Test_total/clock">
<obj_property name="ElementShortName">clock</obj_property> <obj_property name="ElementShortName">clock</obj_property>
@ -39,9 +39,13 @@
<obj_property name="ElementShortName">nop_Cntrl</obj_property> <obj_property name="ElementShortName">nop_Cntrl</obj_property>
<obj_property name="ObjectShortName">nop_Cntrl</obj_property> <obj_property name="ObjectShortName">nop_Cntrl</obj_property>
</wvobject> </wvobject>
<wvobject type="logic" fp_name="/Test_total/Pl/RST"> <wvobject type="logic" fp_name="/Test_total/Pl/rst">
<obj_property name="ElementShortName">RST</obj_property> <obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">RST</obj_property> <obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_total/Pl/Ual/JumpFlag">
<obj_property name="ElementShortName">JumpFlag</obj_property>
<obj_property name="ObjectShortName">JumpFlag</obj_property>
</wvobject> </wvobject>
</wvobject> </wvobject>
<wvobject type="group" fp_name="group459"> <wvobject type="group" fp_name="group459">
@ -168,6 +172,7 @@
<wvobject type="array" fp_name="/Test_total/Pl/Mem_Data_Out"> <wvobject type="array" fp_name="/Test_total/Pl/Mem_Data_Out">
<obj_property name="ElementShortName">Mem_Data_Out[7:0]</obj_property> <obj_property name="ElementShortName">Mem_Data_Out[7:0]</obj_property>
<obj_property name="ObjectShortName">Mem_Data_Out[7:0]</obj_property> <obj_property name="ObjectShortName">Mem_Data_Out[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject type="array" fp_name="/Test_total/Pl/Mem_FinalB"> <wvobject type="array" fp_name="/Test_total/Pl/Mem_FinalB">
<obj_property name="ElementShortName">Mem_FinalB[7:0]</obj_property> <obj_property name="ElementShortName">Mem_FinalB[7:0]</obj_property>
@ -177,6 +182,7 @@
<wvobject type="group" fp_name="group463"> <wvobject type="group" fp_name="group463">
<obj_property name="label">Re</obj_property> <obj_property name="label">Re</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="array" fp_name="/Test_total/Pl/Re_A"> <wvobject type="array" fp_name="/Test_total/Pl/Re_A">
<obj_property name="ElementShortName">Re_A[7:0]</obj_property> <obj_property name="ElementShortName">Re_A[7:0]</obj_property>
<obj_property name="ObjectShortName">Re_A[7:0]</obj_property> <obj_property name="ObjectShortName">Re_A[7:0]</obj_property>
@ -242,6 +248,7 @@
<wvobject type="array" fp_name="/Test_total/Pl/DataMem/Mem[0]"> <wvobject type="array" fp_name="/Test_total/Pl/DataMem/Mem[0]">
<obj_property name="ElementShortName">[0][7:0]</obj_property> <obj_property name="ElementShortName">[0][7:0]</obj_property>
<obj_property name="ObjectShortName">[0][7:0]</obj_property> <obj_property name="ObjectShortName">[0][7:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject type="array" fp_name="/Test_total/Pl/DataMem/Mem[1]"> <wvobject type="array" fp_name="/Test_total/Pl/DataMem/Mem[1]">
<obj_property name="ElementShortName">[1][7:0]</obj_property> <obj_property name="ElementShortName">[1][7:0]</obj_property>
@ -254,6 +261,11 @@
<wvobject type="array" fp_name="/Test_total/Pl/DataMem/Mem[3]"> <wvobject type="array" fp_name="/Test_total/Pl/DataMem/Mem[3]">
<obj_property name="ElementShortName">[3][7:0]</obj_property> <obj_property name="ElementShortName">[3][7:0]</obj_property>
<obj_property name="ObjectShortName">[3][7:0]</obj_property> <obj_property name="ObjectShortName">[3][7:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_total/Pl/DataMem/Mem[4]">
<obj_property name="ElementShortName">[4][7:0]</obj_property>
<obj_property name="ObjectShortName">[4][7:0]</obj_property>
</wvobject> </wvobject>
</wvobject> </wvobject>
</wave_config> </wave_config>