77 lines
2.8 KiB
VHDL
77 lines
2.8 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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-- Instruction coEX
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-- ADD 00000001
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-- MUL 00000010
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-- SUB 00000011
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-- DIV 00000100
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-- COP 00000101
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-- AFC 00000110
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-- LOAD 00000111
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-- STORE 00001000
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-- INF 00001001
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-- SUP 00001010
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-- EQ 00001011
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-- NOT 00001100
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-- AND 00001101
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-- OR 00001110
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-- NOP 11111111
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-- when the just entered instruction causes a problem with an instruction already in the EX or Mem stage (a write-Back stage would not cause any harm) we:
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-- we freeze IP on the current instruction
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-- we insert NOPs in the LI_DI OP while there is a conflict in order to let the problematic instruction finish
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entity AleaControler is
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Port (
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-- get the current op and variables from the 3 pipelines stages that can interract
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Op_DI, Op_EX, Op_Mem, Op_Re : in STD_LOGIC_VECTOR (7 downto 0);
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A_EX, A_Mem, A_Re : in STD_LOGIC_VECTOR (7 downto 0);
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B_DI : in STD_LOGIC_VECTOR (7 downto 0);
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C_DI : in STD_LOGIC_VECTOR (7 downto 0);
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CNTRL : out STD_LOGIC);
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end AleaControler;
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architecture Behavioral of AleaControler is
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signal alea_DI_EX, alea_DI_MEM: STD_LOGIC;
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signal is_LI_arithmetic, is_DI_arithmetic: STD_LOGIC;
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begin
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CNTRL <= -- either a problem between the 1st and 2nd or 1st and 3rd
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'1' when
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-- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read)
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(
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-- check Op1 & Op2
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((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_EX /= x"08" and Op_EX /= x"ff")) and
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-- check Registers are the same
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((A_Ex = B_DI) or (A_EX = C_DI))
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) or
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-- read after write : Op1 other than STORE/NOP, op3 other than AFC/NOP, R(write) = R(read)
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(
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-- check Op1 & Op2
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((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_Mem /= x"08" and Op_Mem /= x"ff")) and
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-- check Registers are the same
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((A_Mem = B_DI) or (A_Mem = C_DI))
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) or
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-- read after write : Op1 other than STORE/NOP, op4 other than AFC/NOP, R(write) = R(read)
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(
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-- check Op1 & Op2
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((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_Re /= x"08" and Op_Re /= x"ff")) and
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-- check Registers are the same
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((A_Re = B_DI) or (A_Re = C_DI))
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)
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or
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(
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Op_EX = x"10" or Op_Mem = x"10" or Op_Re = x"10"
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)
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else '0';
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end Behavioral;
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