diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl index 74e0959..bcdbdc2 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl @@ -8,4 +8,4 @@ if { [string length $curr_wave] == 0 } { } } -run 50us +run 100us diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb index 7f76002..69e344e 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log index 018949d..8b4909e 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log @@ -336,3 +336,57 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Pro INFO: [VRFC 10-307] analyzing entity DataMemory INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity DataMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_total +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh index f6b7d78..e677e93 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for compiling the simulation design source files # -# Generated by Vivado on Tue May 30 13:26:07 CEST 2023 +# Generated by Vivado on Tue May 30 16:24:18 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh index d9fe5f4..62a1c82 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for elaborating the compiled design # -# Generated by Vivado on Tue May 30 13:26:09 CEST 2023 +# Generated by Vivado on Tue May 30 16:24:19 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh index 5640af2..3243763 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for simulating the design by launching the simulator # -# Generated by Vivado on Tue May 30 13:26:10 CEST 2023 +# Generated by Vivado on Tue May 30 16:24:20 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o index cbdbd00..5b1f105 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c index ac2ef8a..c0f17e4 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c @@ -43,16 +43,18 @@ #define alloca _alloca #endif typedef void (*funcp)(char *, char *); -extern void execute_89(char*, char *); -extern void execute_90(char*, char *); -extern void execute_79(char*, char *); +extern void execute_93(char*, char *); extern void execute_80(char*, char *); extern void execute_81(char*, char *); extern void execute_82(char*, char *); extern void execute_83(char*, char *); extern void execute_84(char*, char *); extern void execute_85(char*, char *); -extern void execute_88(char*, char *); +extern void execute_86(char*, char *); +extern void execute_89(char*, char *); +extern void execute_90(char*, char *); +extern void execute_91(char*, char *); +extern void execute_92(char*, char *); extern void execute_53(char*, char *); extern void execute_54(char*, char *); extern void execute_60(char*, char *); @@ -63,21 +65,22 @@ extern void execute_66(char*, char *); extern void execute_68(char*, char *); extern void execute_70(char*, char *); extern void execute_71(char*, char *); -extern void execute_73(char*, char *); -extern void execute_75(char*, char *); +extern void execute_72(char*, char *); +extern void execute_74(char*, char *); extern void execute_76(char*, char *); -extern void execute_78(char*, char *); -extern void execute_87(char*, char *); +extern void execute_77(char*, char *); +extern void execute_79(char*, char *); +extern void execute_88(char*, char *); extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -funcp funcTab[27] = {(funcp)execute_89, (funcp)execute_90, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_88, (funcp)execute_53, (funcp)execute_54, (funcp)execute_60, (funcp)execute_62, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_68, (funcp)execute_70, (funcp)execute_71, (funcp)execute_73, (funcp)execute_75, (funcp)execute_76, (funcp)execute_78, (funcp)execute_87, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; -const int NumRelocateId= 27; +funcp funcTab[30] = {(funcp)execute_93, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_53, (funcp)execute_54, (funcp)execute_60, (funcp)execute_62, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_68, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_74, (funcp)execute_76, (funcp)execute_77, (funcp)execute_79, (funcp)execute_88, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 30; void relocate(char *dp) { - iki_relocate(dp, "xsim.dir/Test_total_behav/xsim.reloc", (void **)funcTab, 27); - iki_vhdl_file_variable_register(dp + 23784); - iki_vhdl_file_variable_register(dp + 23840); + iki_relocate(dp, "xsim.dir/Test_total_behav/xsim.reloc", (void **)funcTab, 30); + iki_vhdl_file_variable_register(dp + 24448); + iki_vhdl_file_variable_register(dp + 24504); /*Populate the transaction function pointer field in the whole net structure */ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o index baa7127..f7bfae3 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info index 219c3be..a8a0d21 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info @@ -1,5 +1,5 @@ 1685389741 1685390103 -104 +147 1 aef36ef3a0d94dac9e6058b656907afd diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl index 6c5c8cc..fe1417b 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Tue May 30 13:19:40 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Tue May 30 16:24:18 2023" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" @@ -14,19 +14,19 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "103" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "146" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "2757.340 MHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2576.095 MHz" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment" webtalk_register_client -client xsim webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key runtime -value "50 us" -context "xsim\\usage" -webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "122660_KB" -context "xsim\\usage" -webtalk_transmit -clientid 653659988 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key iteration -value "5" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.02_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "122664_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2613593652 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg index 666e6a6..fca23f8 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem index aba48d2..bd35d3a 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc index 1fa4560..ea4bf54 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx index 13e922b..06987bd 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx @@ -1,6 +1,6 @@ { - crc : 5669434041321685966 , + crc : 4961576604248800900 , ccp_crc : 0 , cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total" , buildDate : "Jun 14 2018" , diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti index e63d977..ebeb0fd 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type index 12574a8..b868556 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg index 3009140..02652b1 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk index 3f8ae17..01b13ee 100755 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log index a36c0c7..f6f65fc 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log @@ -1,4 +1,4 @@ -Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb -simrunnum 0 -socket 58539 +Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb -simrunnum 0 -socket 42291 Design successfully loaded -Design Loading Memory Usage: 32724 KB (Peak: 32776 KB) -Design Loading CPU Usage: 10 ms +Design Loading Memory Usage: 32728 KB (Peak: 32780 KB) +Design Loading CPU Usage: 20 ms diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb index 8106712..6f9dc20 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb index 6e25d8a..dbb642b 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb index e5ea2c5..bcda625 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb index 5dd2bf4..7438a48 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb index 4b2fd18..11fe39e 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx index c61659a..1535890 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -2,13 +2,13 @@ 2018.2 Jun 14 2018 20:07:38 -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685437044,vhdl,,,,test_total,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685389246,vhdl,,,,alu,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd,1685444515,vhdl,,,,aleacontroler,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685451235,vhdl,,,,test_total,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685454749,vhdl,,,,alu,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd,1685451016,vhdl,,,,aleacontroler,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685436168,vhdl,,,,ip,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685439807,vhdl,,,,instructionmemory,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685456575,vhdl,,,,instructionmemory,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685445542,vhdl,,,,datamemory,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685443285,vhdl,,,,pipeline,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685455519,vhdl,,,,pipeline,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685435532,vhdl,,,,registers,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,, diff --git a/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd b/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd index b5debf1..32ba8ab 100644 --- a/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd +++ b/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd @@ -39,17 +39,15 @@ architecture Behavioral of test_total is component Pipeline - Port ( rst : in STD_LOGIC; Clk : in STD_LOGIC); + Port (Clk : in STD_LOGIC); end component; constant clock_period : time := 10 ns; signal clock : Std_logic := '0'; - signal rst : Std_logic := '1'; begin -- instantiate Pl : Pipeline PORT MAP ( - Rst => rst, Clk => clock ); @@ -59,6 +57,4 @@ begin wait for 100ns; end process; - rst <= '0' after 50ns; - end Behavioral; \ No newline at end of file diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd index 1ef8568..6ce7ac6 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd @@ -41,7 +41,9 @@ entity ALU is N : out STD_LOGIC; O : out STD_LOGIC; Z : out STD_LOGIC; - C : out STD_LOGIC); + C : out STD_LOGIC; + JumpFlag : inout STD_LOGIC -- 0 false 1 true + ); end ALU; -- Instruction code @@ -60,7 +62,7 @@ end ALU; architecture Behavioral of ALU is signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000"; - + signal flag : STD_LOGIC := '0'; begin process(A, B, Ctrl_Alu) begin @@ -68,20 +70,22 @@ begin O <= '0'; Z <= '0'; C <= '0'; + flag <= JumpFlag; case Ctrl_Alu is when x"01" => res <= (x"00" & A) + (x"00" & B) ; if (((x"00" & A) + (x"00" & B)) > 255) then C <= '1'; elsif (A+B = 0) then Z <= '1'; end if; -- ADD when x"02" => res <= A * B; if (A * B > 255) then O <= '1'; elsif A * B = 0 then Z <= '1'; end if; -- MUL when x"03" => res <= (x"00" & A) - (x"00" & B) ; if (B > A) then N <= '1'; elsif (B = A) then Z <= '1'; end if; -- SUB when x"04" => if (B /= 0) then res <= (x"00" & std_logic_vector(to_unsigned(to_integer(unsigned(A)) / to_integer(unsigned(B)),8))); else res <= x"0000"; end if; -- DIV - when x"09" => if A < B then res <= x"0001"; else res <= x"0000"; end if; - when x"0A" => if A > B then res <= x"0001"; else res <= x"0000"; end if; - when x"0B" => if A = B then res <= x"0001"; else res <= x"0000"; end if; - when x"0C" => if A > 0 then res <= x"0000"; else res <= x"0001"; end if; - when x"0D" => if (A > 0 and B > 0) then res <= x"0001" ; else res <= x"0000"; end if; - when x"0E" => if (A > 0 or B > 0) then res <= x"0001" ; else res <= x"0000"; end if; - when x"0F" => if ((A > 0 and B = 0) or (A = 0 and B >0)) then res <= x"0001" ; else res <= x"0000"; end if; + when x"09" => if A < B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0A" => if A > B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0B" => if A = B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0C" => if A > 0 then res <= x"0000"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0D" => if (A > 0 and B > 0) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0E" => if (A > 0 or B > 0) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0F" => if ((A > 0 and B = 0) or (A = 0 and B >0)) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; when others => res <= x"0000"; end case; end process; + JumpFlag <= flag; S <= res(7 downto 0); end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd index 22d8155..4cb3f72 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd @@ -68,6 +68,10 @@ begin -- check Registers are the same ((A_Re = B_DI) or (A_Re = C_DI)) - ) + ) + or + ( + Op_EX = x"10" or Op_Mem = x"10" or Op_Re = x"10" + ) else '0'; end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd index eed9e61..7f4f048 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd @@ -41,7 +41,12 @@ end InstructionMemory; architecture Behavioral of InstructionMemory is type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0); -- signal Mem : Mem_array := ((x"06000200"),(x"08020000"),(x"07000200"),(x"08000000"),(x"06000200"),(x"08020000"),(x"07000000"),(x"07010200"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08010000"),others => (x"ff000000")); - signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000600"),(x"08030000"),(x"07000000"),(x"07010300"),(x"02000001"),(x"08040000"),(x"07000400"),(x"08010000"),(x"06000200"),(x"08030000"),(x"07000100"),(x"07010300"),(x"04000001"),(x"08040000"),(x"07000400"),(x"07010000"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000")); +-- signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000600"),(x"08030000"),(x"07000000"),(x"07010300"),(x"02000001"),(x"08040000"),(x"07000400"),(x"08010000"),(x"06000200"),(x"08030000"),(x"07000100"),(x"07010300"),(x"04000001"),(x"08040000"),(x"07000400"),(x"07010000"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000")); +-- test JMP signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08030000"),(x"07000300"),(x"08010000"),(x"0F0D0000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08020000"),(x"06000900"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000")); +-- test JMF signal Mem : Mem_array := ((x"06000500"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"100F0000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08000000"),(x"FF000000"),others => (x"ff000000")); +-- test if else signal Mem : Mem_array := ((x"06000200"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"10021000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08000000"),(x"0F140000"),(x"06000C00"),(x"08020000"),(x"07000200"),(x"08000000"),(x"FF000000"),others => (x"ff000000")); +-- test boucle while +signal Mem : Mem_array := ((x"06000500"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"10001B00"),(x"06001400"),(x"08030000"),(x"07000000"),(x"07010300"),(x"09020001"),(x"08040200"),(x"10041B00"),(x"06000200"),(x"08010000"),(x"07000000"),(x"07010100"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08000000"),(x"0F0B0000"),(x"FF000000"),others => (x"ff000000")); -- signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000")); begin Inst_out <= Mem(to_integer(unsigned(Addr))); diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd index b4233f7..e2e2c39 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd @@ -32,7 +32,7 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity Pipeline is - Port (RST : in STD_LOGIC; Clk : in STD_LOGIC); + Port (Clk : in STD_LOGIC); end Pipeline; architecture Behavioral of Pipeline is @@ -47,6 +47,7 @@ architecture Behavioral of Pipeline is end component; signal IP_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal rst : STD_LOGIC := '0'; component InstructionMemory Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); @@ -108,12 +109,13 @@ architecture Behavioral of Pipeline is N : out STD_LOGIC; O : out STD_LOGIC; Z : out STD_LOGIC; - C : out STD_LOGIC + C : out STD_LOGIC; + JumpFlag : inout STD_LOGIC ); end component; signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag : STD_LOGIC; + signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag, Jump_Flag : STD_LOGIC; component Stage_Ex_Mem Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); @@ -163,11 +165,12 @@ architecture Behavioral of Pipeline is signal Re_W : STD_LOGIC; -- to control jumping and where to jump - signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - signal jump : STD_LOGIC; + signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal jump : STD_LOGIC := '0'; signal nop_Cntrl : STD_LOGIC; signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); + signal Di_Op_Final : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); begin -- instructionPointer @@ -215,7 +218,7 @@ Stage2 : Stage_Di_Ex PORT MAP ( In_A => Di_A, In_B => Di_FinalB, In_C => Di_C2, - In_Op => Di_Op, + In_Op => Di_Op_Final, Clk => Clk, Out_A => Ex_A, Out_B => Ex_B, @@ -231,7 +234,8 @@ Ual : ALU PORT MAP ( N => S_NFlag, O => S_OFlag, Z => S_ZFlag, - C => S_CFlag); + C => S_CFlag, + JumpFlag => Jump_Flag); -- Stage Ex/Mem Stage3 : Stage_Ex_Mem PORT MAP ( @@ -332,6 +336,22 @@ CU : AleaControler port map ( CNTRL => nop_Cntrl); -- in case of alea : replace li(31 downto 24) by NOP - OP_LI_DI <= X"ff" when nop_Cntrl='1' else Li(31 downto 24); + OP_LI_DI <= X"ff" when (nop_Cntrl='1' or + (Di_Op = x"10" and Jump_Flag = '1')) -- to prevent JMF + else Li(31 downto 24); + +-- jump JMP + addr_to_jump <= DI_A when (DI_OP = x"0F") -- JMP + else Di_B when (Di_Op = x"10" and Jump_Flag = '0') -- JMF + else (others => '0'); + jump <= '1' when DI_OP = x"0F" -- JMP + or (Di_Op = x"10" and Jump_Flag = '0') -- JMF + else '0'; + +-- case of JMF not triggering + Di_Op_Final <= x"ff" when (Di_Op = x"10" and Jump_Flag = '1') + else Di_Op; + + end Behavioral; diff --git a/VHDL/ALU/ALU.xpr b/VHDL/ALU/ALU.xpr index 4b10f19..a429411 100644 --- a/VHDL/ALU/ALU.xpr +++ b/VHDL/ALU/ALU.xpr @@ -33,7 +33,7 @@