rlacroix/Projet-Systemes-Informatiques
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

fixed data path and aleas

Browse source
This commit is contained in:
Lacroix Raphael 2023-05-30 13:38:05 +02:00
parent 8a7685b049
commit 576b41da4d
101 changed files with 1435 additions and 787 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

97
VHDL/ALU/ALU.cache/wt/gui_handlers.wdf
View file

@ -1,33 +1,40 @@
version:1 version:1
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f6164645f656c656d656e74:3336:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f6164645f656c656d656e74:3336:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f72656d6f76655f73656c65637465645f656c656d656e7473:3133:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f72656d6f76655f73656c65637465645f656c656d656e7473:3133:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:616273747261637466696c65766965775f72656c6f6164:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3132:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3630:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6170706c79:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3137:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3834:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:3234:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:3235:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f70656e5f6d657373616765735f76696577:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f70656e5f6d657373616765735f76696577:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f6578697374696e675f6f725f6372656174655f6e65775f636f6e73747261696e7473:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f6578697374696e675f6f725f6372656174655f6e65775f636f6e73747261696e7473:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f66696c655f7461626c65:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f66696c655f7461626c65:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637265617465636f6e73747261696e747366696c6570616e656c5f66696c655f6e616d65:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637265617465636f6e73747261696e747366696c6570616e656c5f66696c655f6e616d65:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:3134:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746572756e7265706f72746469616c6f675f7265706f72745f6e616d65:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:3135:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f646566696e655f6d6f64756c65735f616e645f737065636966795f696f5f706f727473:313438:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f646566696e655f6d6f64756c65735f616e645f737065636966795f696f5f706f727473:313438:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f656e746974795f6e616d65:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f656e746974795f6e616d65:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6578707265706f72747472656570616e656c5f656469745f7265706f72745f6f7074696f6e73:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6578707265706f72747472656570616e656c5f6578705f7265706f72745f747265655f7461626c65:39:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:333039:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:343533:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f6d65737361676573:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f6d65737361676573:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:313036:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:313935:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f666974:36:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f666974:36:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:3439:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:313033:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:3630:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:313334:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636c6f7365:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636c6f7365:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:3136:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68696e70757468616e646c65725f746f67676c655f6c696e655f636f6d6d656e7473:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68706f7075707469746c655f636c6f7365:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68706f7075707469746c655f636c6f7365:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f6770616e656c5f636f7079:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f6770616e656c5f636f7079:31:00:00
@ -37,11 +44,11 @@ version:1
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:3138:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:3138:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:3136:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:3136:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:37:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:37:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3638:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3730:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f666c6f77:38:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f666c6f77:38:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6970:3132:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6970:3132:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6f70656e5f726563656e745f70726f6a656374:3235:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6f70656e5f726563656e745f70726f6a656374:3235:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3436:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3437:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:3130:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:3130:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73657474696e6773:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73657474696e6773:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73696d756c6174696f6e5f77617665666f726d:3134:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73696d756c6174696f6e5f77617665666f726d:3134:00:00
@ -51,55 +58,65 @@ version:1
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:36:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:36:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:37:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:37:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3231:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3235:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6f70656e66696c65616374696f6e5f63616e63656c:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6f70656e66696c65616374696f6e5f63616e63656c:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6f70656e66696c65616374696f6e5f6f70656e5f6469726563746f7279:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6f70656e66696c65616374696f6e5f6f70656e5f6469726563746f7279:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:3135:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:3138:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:37:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3136:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f676f746f5f696e7374616e74696174696f6e:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6f675f77696e646f77:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6f675f77696e646f77:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265706f7274735f77696e646f77:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265706f7274735f77696e646f77:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:36:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:35:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:3739:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f7265736574:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:313333:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f706f73745f73796e7468657369735f66756e6374696f6e616c:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f706f73745f73796e7468657369735f66756e6374696f6e616c:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f73657474696e6773:38:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:35:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:35:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3230:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3335:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706c616e61686561647461625f73686f775f666c6f775f6e6176696761746f72:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706c616e61686561647461625f73686f775f666c6f775f6e6176696761746f72:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7072696d617279636c6f636b7370616e656c5f7265636f6d6d656e6465645f636f6e73747261696e74735f7461626c65:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7072696d617279636c6f636b7370616e656c5f7265636f6d6d656e6465645f636f6e73747261696e74735f7461626c65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:3135:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e67736761646765745f656469745f70726f6a6563745f73657474696e6773:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e67736761646765745f656469745f70726f6a6563745f73657474696e6773:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e677373696d756c6174696f6e70616e656c5f73656c6563745f7465737462656e63685f746f705f6d6f64756c65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e677373696d756c6174696f6e70616e656c5f7461626265645f70616e65:35:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563747461625f72656c6f6164:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563747461625f72656c6f6164:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f6c696e655f636f6d6d656e74:39:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f736176655f66696c65:3130:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f736176655f66696c65:3130:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:313637:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:363238:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72746c6f7074696f6e7370616e656c5f73656c6563745f746f705f6d6f64756c655f6f665f796f75725f64657369676e:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72746c6f7074696f6e7370616e656c5f73656c6563745f746f705f6d6f64756c655f6f665f796f75725f64657369676e:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:39:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:39:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73656c656374746f706d6f64756c656469616c6f675f73656c6563745f746f705f6d6f64756c65:38:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73657474696e67736469616c6f675f70726f6a6563745f74726565:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73657474696e67736469616c6f675f70726f6a6563745f74726565:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6f626a6563747370616e656c5f73696d756c6174696f6e5f6f626a656374735f747265655f7461626c65:3130:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6f626a6563747370616e656c5f73696d756c6174696f6e5f6f626a656374735f747265655f7461626c65:3435:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e73636f70657370616e656c5f73696d756c6174655f73636f70655f7461626c65:3238:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e73636f70657370616e656c5f73696d756c6174655f73636f70655f7461626c65:3734:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f6f725f6372656174655f736f757263655f66696c65:3138:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f6f725f6372656174655f736f757263655f66696c65:3231:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:3133:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:3135:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:36:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f7365727461626c655f7372635f63686f6f7365725f7461626c65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3136:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73746174656d6f6e69746f725f72657365745f72756e:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73746174656d6f6e69746f725f72657365745f72756e:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:3231:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:3339:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f636865636b5f74696d696e675f7265706f7274:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f636865636b5f74696d696e675f7265706f7274:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f6d6574686f646f6c6f67795f7265706f7274:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f6d6574686f646f6c6f67795f7265706f7274:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f74696d696e675f73756d6d6172795f7265706f7274:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f74696d696e675f73756d6d6172795f7265706f7274:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f766965775f74696d696e675f636f6e73747261696e7473:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f766965775f74696d696e675f636f6e73747261696e7473:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:3635:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:323633:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6f7074696f6e73766965775f72657365745f746f5f64656661756c7473:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6f7074696f6e73766965775f72657365745f746f5f64656661756c7473:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6f7074696f6e73766965775f73686f775f7369676e616c5f696e6469636573:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6f7074696f6e73766965775f73686f775f7369676e616c5f696e6469636573:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f6164645f6d61726b6572:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f6164645f6d61726b6572:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f676f746f5f6c6173745f74696d65:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f676f746f5f6c6173745f74696d65:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f676f746f5f74696d655f30:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f676f746f5f74696d655f30:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f6e6578745f6d61726b6572:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f6e6578745f6d61726b6572:33:00:00
eof:2706062306 eof:1736165994

25
VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf
View file

@ -1,18 +1,23 @@
version:1 version:1
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3137:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3230:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:32:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:32:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:33:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65646974756e646f:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65646974756e646f:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:34:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:33:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:39:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3132:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:37:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:32:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3738:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f77736f75726365:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74696d696e67636f6e73747261696e747377697a617264:32:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3131:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c65766965776e6176696761746f72:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:35:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:313331:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74696d696e67636f6e73747261696e747377697a617264:34:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c65766965776e6176696761746f72:34:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:3133:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:35:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00
eof:1901464571 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:77617665666f726d73617665636f6e66696775726174696f6e:3131:00:00
eof:158833456

2
VHDL/ALU/ALU.cache/wt/project.wpc
View file

@ -1,3 +1,3 @@
version:1 version:1
6d6f64655f636f756e7465727c4755494d6f6465:19 6d6f64655f636f756e7465727c4755494d6f6465:21
eof: eof:

8
VHDL/ALU/ALU.cache/wt/synthesis.wdf
View file

@ -33,7 +33,7 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323673:00:00 73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313873:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313637332e3239334d42:00:00 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313637332e3238314d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3531332e3436394d42:00:00 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3531332e3436314d42:00:00
eof:2352502396 eof:428720552

124
VHDL/ALU/ALU.cache/wt/webtalk_pa.xml
View file

@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue May 30 00:50:19 2023"> <application name="pa" timeStamp="Tue May 30 13:19:37 2023">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="489b0519ba8b4bcea2b75f67f8ebbc30" type="ProjectID"/> <property name="ProjectID" value="489b0519ba8b4bcea2b75f67f8ebbc30" type="ProjectID"/>
<property name="ProjectIteration" value="4" type="ProjectIteration"/> <property name="ProjectIteration" value="4" type="ProjectIteration"/>
@ -17,53 +17,65 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item> </item>
<item name="Java Command Handlers"> <item name="Java Command Handlers">
<property name="AddSources" value="17" type="JavaHandler"/> <property name="AddSources" value="20" type="JavaHandler"/>
<property name="CloseProject" value="2" type="JavaHandler"/> <property name="CloseProject" value="2" type="JavaHandler"/>
<property name="EditDelete" value="3" type="JavaHandler"/> <property name="EditDelete" value="3" type="JavaHandler"/>
<property name="EditUndo" value="1" type="JavaHandler"/> <property name="EditUndo" value="1" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/> <property name="NewProject" value="1" type="JavaHandler"/>
<property name="OpenProject" value="3" type="JavaHandler"/> <property name="OpenProject" value="4" type="JavaHandler"/>
<property name="RunImplementation" value="3" type="JavaHandler"/> <property name="RunImplementation" value="3" type="JavaHandler"/>
<property name="RunSynthesis" value="9" type="JavaHandler"/> <property name="RunSynthesis" value="12" type="JavaHandler"/>
<property name="ShowView" value="7" type="JavaHandler"/> <property name="SaveFileProxyHandler" value="2" type="JavaHandler"/>
<property name="SimulationRelaunch" value="3" type="JavaHandler"/> <property name="SetTopNode" value="1" type="JavaHandler"/>
<property name="SimulationRun" value="78" type="JavaHandler"/> <property name="ShowSource" value="1" type="JavaHandler"/>
<property name="TimingConstraintsWizard" value="2" type="JavaHandler"/> <property name="ShowView" value="11" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="3" type="JavaHandler"/> <property name="SimulationRelaunch" value="5" type="JavaHandler"/>
<property name="ToolsSettings" value="5" type="JavaHandler"/> <property name="SimulationRun" value="131" type="JavaHandler"/>
<property name="TimingConstraintsWizard" value="4" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="4" type="JavaHandler"/>
<property name="ToolsSettings" value="13" type="JavaHandler"/>
<property name="UpdateSourceFiles" value="5" type="JavaHandler"/> <property name="UpdateSourceFiles" value="5" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/> <property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
<property name="WaveformSaveConfiguration" value="11" type="JavaHandler"/>
</item> </item>
<item name="Gui Handlers"> <item name="Gui Handlers">
<property name="AbstractCombinedPanel_ADD_ELEMENT" value="36" type="GuiHandlerData"/> <property name="AbstractCombinedPanel_ADD_ELEMENT" value="36" type="GuiHandlerData"/>
<property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="13" type="GuiHandlerData"/> <property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="13" type="GuiHandlerData"/>
<property name="AddSrcWizard_SPECIFY_OR_CREATE_CONSTRAINT_FILES" value="1" type="GuiHandlerData"/> <property name="AbstractFileView_RELOAD" value="1" type="GuiHandlerData"/>
<property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="2" type="GuiHandlerData"/> <property name="AddSrcWizard_SPECIFY_OR_CREATE_CONSTRAINT_FILES" value="2" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="12" type="GuiHandlerData"/> <property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="3" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="60" type="GuiHandlerData"/> <property name="BaseDialog_APPLY" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="17" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="84" type="GuiHandlerData"/>
<property name="CmdMsgDialog_MESSAGES" value="4" type="GuiHandlerData"/> <property name="CmdMsgDialog_MESSAGES" value="4" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="24" type="GuiHandlerData"/> <property name="CmdMsgDialog_OK" value="25" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/> <property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/> <property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="4" type="GuiHandlerData"/>
<property name="ConstraintsChooserPanel_ADD_EXISTING_OR_CREATE_NEW_CONSTRAINTS" value="1" type="GuiHandlerData"/> <property name="ConstraintsChooserPanel_ADD_EXISTING_OR_CREATE_NEW_CONSTRAINTS" value="1" type="GuiHandlerData"/>
<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/> <property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/>
<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/> <property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
<property name="ConstraintsChooserPanel_FILE_TABLE" value="1" type="GuiHandlerData"/> <property name="ConstraintsChooserPanel_FILE_TABLE" value="1" type="GuiHandlerData"/>
<property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/> <property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="14" type="GuiHandlerData"/> <property name="CreateRunReportDialog_REPORT_NAME" value="1" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="15" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_TYPE" value="1" type="GuiHandlerData"/>
<property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="148" type="GuiHandlerData"/> <property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="148" type="GuiHandlerData"/>
<property name="DefineModulesDialog_ENTITY_NAME" value="3" type="GuiHandlerData"/> <property name="DefineModulesDialog_ENTITY_NAME" value="3" type="GuiHandlerData"/>
<property name="ExpReportTreePanel_EDIT_REPORT_OPTIONS" value="1" type="GuiHandlerData"/>
<property name="ExpReportTreePanel_EXP_REPORT_TREE_TABLE" value="9" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/> <property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="309" type="GuiHandlerData"/> <property name="FileSetPanel_FILE_SET_PANEL_TREE" value="453" type="GuiHandlerData"/>
<property name="FileSetPanel_MESSAGES" value="1" type="GuiHandlerData"/> <property name="FileSetPanel_MESSAGES" value="1" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="106" type="GuiHandlerData"/> <property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="195" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/> <property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="3" type="GuiHandlerData"/> <property name="GettingStartedView_OPEN_PROJECT" value="3" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="6" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_FIT" value="6" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="49" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_IN" value="103" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="60" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_OUT" value="134" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="2" type="GuiHandlerData"/> <property name="HCodeEditor_CLOSE" value="2" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="3" type="GuiHandlerData"/> <property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="16" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="1" type="GuiHandlerData"/>
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/> <property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
<property name="LogMonitor_MONITOR" value="1" type="GuiHandlerData"/> <property name="LogMonitor_MONITOR" value="1" type="GuiHandlerData"/>
<property name="LogPanel_COPY" value="1" type="GuiHandlerData"/> <property name="LogPanel_COPY" value="1" type="GuiHandlerData"/>
@ -73,11 +85,11 @@ This means code written to parse this file will need to be revisited each subseq
<property name="MainMenuMgr_CHECKPOINT" value="18" type="GuiHandlerData"/> <property name="MainMenuMgr_CHECKPOINT" value="18" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="16" type="GuiHandlerData"/> <property name="MainMenuMgr_EDIT" value="16" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="7" type="GuiHandlerData"/> <property name="MainMenuMgr_EXPORT" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="68" type="GuiHandlerData"/> <property name="MainMenuMgr_FILE" value="70" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/> <property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="12" type="GuiHandlerData"/> <property name="MainMenuMgr_IP" value="12" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="25" type="GuiHandlerData"/> <property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="25" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="46" type="GuiHandlerData"/> <property name="MainMenuMgr_PROJECT" value="47" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="10" type="GuiHandlerData"/> <property name="MainMenuMgr_REPORTS" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="14" type="GuiHandlerData"/> <property name="MainMenuMgr_SIMULATION_WAVEFORM" value="14" type="GuiHandlerData"/>
@ -87,51 +99,61 @@ This means code written to parse this file will need to be revisited each subseq
<property name="MainMenuMgr_WINDOW" value="6" type="GuiHandlerData"/> <property name="MainMenuMgr_WINDOW" value="6" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="7" type="GuiHandlerData"/> <property name="MainToolbarMgr_RUN" value="7" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/> <property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="21" type="GuiHandlerData"/> <property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="25" type="GuiHandlerData"/>
<property name="OpenFileAction_CANCEL" value="1" type="GuiHandlerData"/> <property name="OpenFileAction_CANCEL" value="2" type="GuiHandlerData"/>
<property name="OpenFileAction_OPEN_DIRECTORY" value="3" type="GuiHandlerData"/> <property name="OpenFileAction_OPEN_DIRECTORY" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="15" type="GuiHandlerData"/> <property name="PACommandNames_ADD_SOURCES" value="18" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="7" type="GuiHandlerData"/> <property name="PACommandNames_AUTO_UPDATE_HIER" value="16" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_INSTANTIATION" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_LOG_WINDOW" value="1" type="GuiHandlerData"/> <property name="PACommandNames_LOG_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_REPORTS_WINDOW" value="3" type="GuiHandlerData"/> <property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_REPORTS_WINDOW" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/> <property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="4" type="GuiHandlerData"/> <property name="PACommandNames_SET_AS_TOP" value="6" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="3" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RELAUNCH" value="5" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="79" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RESET" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="133" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_SYNTHESIS_FUNCTIONAL" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN_POST_SYNTHESIS_FUNCTIONAL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_SETTINGS" value="8" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_REPLACE_FILE" value="5" type="GuiHandlerData"/> <property name="PACommandNames_SRC_REPLACE_FILE" value="5" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="20" type="GuiHandlerData"/> <property name="PAViews_CODE" value="35" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/> <property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/> <property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/>
<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="3" type="GuiHandlerData"/> <property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="4" type="GuiHandlerData"/>
<property name="PrimaryClocksPanel_RECOMMENDED_CONSTRAINTS_TABLE" value="2" type="GuiHandlerData"/> <property name="PrimaryClocksPanel_RECOMMENDED_CONSTRAINTS_TABLE" value="2" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/> <property name="ProgressDialog_BACKGROUND" value="15" type="GuiHandlerData"/>
<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/> <property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="ProjectSettingsGadget_EDIT_PROJECT_SETTINGS" value="2" type="GuiHandlerData"/> <property name="ProjectSettingsGadget_EDIT_PROJECT_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="ProjectSettingsSimulationPanel_SELECT_TESTBENCH_TOP_MODULE" value="2" type="GuiHandlerData"/>
<property name="ProjectSettingsSimulationPanel_TABBED_PANE" value="5" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="1" type="GuiHandlerData"/> <property name="ProjectTab_RELOAD" value="1" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="3" type="GuiHandlerData"/> <property name="RDICommands_DELETE" value="3" type="GuiHandlerData"/>
<property name="RDICommands_LINE_COMMENT" value="9" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="10" type="GuiHandlerData"/> <property name="RDICommands_SAVE_FILE" value="10" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="167" type="GuiHandlerData"/> <property name="RDIViews_WAVEFORM_VIEWER" value="628" type="GuiHandlerData"/>
<property name="RTLOptionsPanel_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="2" type="GuiHandlerData"/> <property name="RTLOptionsPanel_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="2" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="1" type="GuiHandlerData"/> <property name="RemoveSourcesDialog_ALSO_DELETE" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="9" type="GuiHandlerData"/> <property name="SaveProjectUtils_SAVE" value="9" type="GuiHandlerData"/>
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="8" type="GuiHandlerData"/>
<property name="SettingsDialog_PROJECT_TREE" value="1" type="GuiHandlerData"/> <property name="SettingsDialog_PROJECT_TREE" value="1" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="10" type="GuiHandlerData"/> <property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="45" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="28" type="GuiHandlerData"/> <property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="74" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="3" type="GuiHandlerData"/> <property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="4" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="18" type="GuiHandlerData"/> <property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="21" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="13" type="GuiHandlerData"/> <property name="SrcChooserPanel_CREATE_FILE" value="15" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="6" type="GuiHandlerData"/> <property name="SrcChooserTable_SRC_CHOOSER_TABLE" value="2" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="16" type="GuiHandlerData"/>
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/> <property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/> <property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/> <property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="2" type="GuiHandlerData"/> <property name="TaskBanner_CLOSE" value="2" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="21" type="GuiHandlerData"/> <property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="39" type="GuiHandlerData"/>
<property name="TimingConstraintsWizard_CREATE_CHECK_TIMING_REPORT" value="1" type="GuiHandlerData"/> <property name="TimingConstraintsWizard_CREATE_CHECK_TIMING_REPORT" value="2" type="GuiHandlerData"/>
<property name="TimingConstraintsWizard_CREATE_METHODOLOGY_REPORT" value="1" type="GuiHandlerData"/> <property name="TimingConstraintsWizard_CREATE_METHODOLOGY_REPORT" value="2" type="GuiHandlerData"/>
<property name="TimingConstraintsWizard_CREATE_TIMING_SUMMARY_REPORT" value="1" type="GuiHandlerData"/> <property name="TimingConstraintsWizard_CREATE_TIMING_SUMMARY_REPORT" value="2" type="GuiHandlerData"/>
<property name="TimingConstraintsWizard_VIEW_TIMING_CONSTRAINTS" value="1" type="GuiHandlerData"/> <property name="TimingConstraintsWizard_VIEW_TIMING_CONSTRAINTS" value="2" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="65" type="GuiHandlerData"/> <property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="263" type="GuiHandlerData"/>
<property name="WaveformOptionsView_RESET_TO_DEFAULTS" value="1" type="GuiHandlerData"/> <property name="WaveformOptionsView_RESET_TO_DEFAULTS" value="1" type="GuiHandlerData"/>
<property name="WaveformOptionsView_SHOW_SIGNAL_INDICES" value="4" type="GuiHandlerData"/> <property name="WaveformOptionsView_SHOW_SIGNAL_INDICES" value="4" type="GuiHandlerData"/>
<property name="WaveformView_ADD_MARKER" value="4" type="GuiHandlerData"/> <property name="WaveformView_ADD_MARKER" value="4" type="GuiHandlerData"/>
@ -140,9 +162,9 @@ This means code written to parse this file will need to be revisited each subseq
<property name="WaveformView_NEXT_MARKER" value="3" type="GuiHandlerData"/> <property name="WaveformView_NEXT_MARKER" value="3" type="GuiHandlerData"/>
</item> </item>
<item name="Other"> <item name="Other">
<property name="GuiMode" value="3" type="GuiMode"/> <property name="GuiMode" value="4" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/> <property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="1" type="TclMode"/> <property name="TclMode" value="2" type="TclMode"/>
</item> </item>
</section> </section>
</application> </application>

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_11.xml Normal file
View file

@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_12.xml Normal file
View file

@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_13.xml Normal file
View file

@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

2
VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst
View file

@ -1,5 +1,5 @@
<?xml version="1.0"?> <?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0"> <ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="rlacroix" Host="" Pid="608282"> <Process Command="vivado" Owner="rlacroix" Host="" Pid="10810">
</Process> </Process>
</ProcessHandle> </ProcessHandle>

BIN
VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp
View file

Binary file not shown.

32
VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl
View file

@ -17,30 +17,30 @@ proc create_report { reportName command } {
send_msg_id runtcl-5 warning "$msg" send_msg_id runtcl-5 warning "$msg"
} }
} }
set_msg_config -id {Common 17-41} -limit 10000000
create_project -in_memory -part xc7a35tcpg236-1 create_project -in_memory -part xc7a35tcpg236-1
set_param project.singleFileAddWarning.threshold 0 set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0 set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt} [current_project] set_property webtalk.parent_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt [current_project]
set_property parent.project_path {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr} [current_project] set_property parent.project_path /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr [current_project]
set_property default_lib xil_defaultlib [current_project] set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project] set_property target_language VHDL [current_project]
set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] set_property board_part digilentinc.com:basys3:part0:1.1 [current_project]
set_property ip_output_repo {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip} [current_project] set_property ip_output_repo /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project] set_property ip_cache_permissions {read write} [current_project]
read_vhdl -library xil_defaultlib { read_vhdl -library xil_defaultlib {
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd} /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd} /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd} /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd} /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd} /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd} /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd} /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd} /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd} /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd} /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
} }
# Mark all dcp files as not used in implementation to prevent them from being # Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the # stitched into the results of this synthesis run. Any black boxes in the
@ -50,8 +50,8 @@ read_vhdl -library xil_defaultlib {
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp set_property used_in_implementation false $dcp
} }
read_xdc {{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc}} read_xdc /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc
set_property used_in_implementation false [get_files {{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc}}] set_property used_in_implementation false [get_files /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
set_param ips.enableIPCacheLiteLoad 0 set_param ips.enableIPCacheLiteLoad 0
close [open __synthesis_is_running__ w] close [open __synthesis_is_running__ w]

192
VHDL/ALU/ALU.runs/synth_1/Pipeline.vds
View file

@ -2,12 +2,12 @@
# Vivado v2018.2 (64-bit) # Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Tue May 30 00:39:32 2023 # Start of session at: Tue May 30 09:12:59 2023
# Process ID: 608313 # Process ID: 10840
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 # Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1
# Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl # Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds # Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou # Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou
#----------------------------------------------------------- #-----------------------------------------------------------
source Pipeline.tcl -notrace source Pipeline.tcl -notrace
Command: synth_design -top Pipeline -part xc7a35tcpg236-1 Command: synth_design -top Pipeline -part xc7a35tcpg236-1
@ -15,44 +15,46 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 608386 INFO: Helper process launched with PID 10853
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 108497 ; free virtual = 138755 Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.699 ; free physical = 57815 ; free virtual = 69577
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38]
INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177]
INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187] INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187]
INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193] INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193]
INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205]
INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47]
INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217] INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217]
INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229] INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229]
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240] INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240]
INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250]
INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259]
INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
INFO: [Synth 8-637] synthesizing blackbox instance 'CU' of component 'ControlUnit' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329] INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329]
WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50] INFO: [Synth 8-638] synthesizing module 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40]
WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170] INFO: [Synth 8-256] done synthesizing module 'AleaControler' (10#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40]
INFO: [Synth 8-256] done synthesizing module 'Pipeline' (10#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50]
WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170]
INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138756 Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57806 ; free virtual = 69569
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report Check Netlist: Report Check Netlist:
@ -61,46 +63,46 @@ Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+ +------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+ +------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177]
WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205]
WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Handling Custom Attributes Start Handling Custom Attributes
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757 Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757 Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7a35tcpg236-1 INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints Processing XDC Constraints
Initializing timing engine Initializing timing engine
Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
Completed Processing XDC Constraints Completed Processing XDC Constraints
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed. No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1673.293 ; gain = 0.000 ; free physical = 108244 ; free virtual = 138510 Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57555 ; free virtual = 69319
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591 Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Loading Part and Timing Information Start Loading Part and Timing Information
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Loading part: xc7a35tcpg236-1 Loading part: xc7a35tcpg236-1
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints Start Applying 'set_property' XDC Constraints
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108339 ; free virtual = 138592 Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
@ -219,9 +221,9 @@ INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too
INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261] WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108313 ; free virtual = 138566 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57618 ; free virtual = 69383
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@ -327,8 +329,8 @@ Finished Part Resource Summary
Start Cross Boundary and Area Optimization Start Cross Boundary and Area Optimization
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met Warning: Parallel synthesis criteria is not met
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55] WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51]
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51] WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55]
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline.
@ -431,7 +433,7 @@ WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][5]) is unused an
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:41 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108314 ; free virtual = 138572 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57609 ; free virtual = 69379
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@ -443,13 +445,13 @@ Report RTL Partitions:
Start Applying XDC Timing Constraints Start Applying XDC Timing Constraints
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108174 ; free virtual = 138436 Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Timing Optimization Start Timing Optimization
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433 Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@ -461,7 +463,7 @@ Report RTL Partitions:
Start Technology Mapping Start Technology Mapping
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433 Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@ -485,7 +487,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup Finished Final Netlist Cleanup
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report Check Netlist: Report Check Netlist:
@ -498,7 +500,7 @@ Report Check Netlist:
Start Renaming Generated Instances Start Renaming Generated Instances
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@ -510,73 +512,55 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy Start Rebuilding User Hierarchy
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Ports Start Renaming Generated Ports
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Handling Custom Attributes Start Handling Custom Attributes
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Nets Start Renaming Generated Nets
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Writing Synthesis Report Start Writing Synthesis Report
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report BlackBoxes: Report BlackBoxes:
+------+--------------+----------+ +-+--------------+----------+
| |BlackBox name |Instances | | |BlackBox name |Instances |
+------+--------------+----------+ +-+--------------+----------+
|1 |ControlUnit | 1| +-+--------------+----------+
+------+--------------+----------+
Report Cell Usage: Report Cell Usage:
+------+-------------------+------+ +-+-----+------+
| |Cell |Count | | |Cell |Count |
+------+-------------------+------+ +-+-----+------+
|1 |ControlUnit_bbox_0 | 1| +-+-----+------+
|2 |BUFG | 1|
|3 |LUT1 | 2|
|4 |LUT2 | 14|
|5 |LUT3 | 2|
|6 |LUT4 | 2|
|7 |LUT5 | 4|
|8 |LUT6 | 15|
|9 |FDRE | 34|
|10 |FDSE | 13|
|11 |IBUF | 1|
+------+-------------------+------+
Report Instance Areas: Report Instance Areas:
+------+-------------+------------------+------+ +------+---------+-------+------+
| |Instance |Module |Cells | | |Instance |Module |Cells |
+------+-------------+------------------+------+ +------+---------+-------+------+
|1 |top | | 89| |1 |top | | 0|
|2 | MemInst |InstructionMemory | 17| +------+---------+-------+------+
|3 | Stage1 |Stage_Li_Di | 11|
|4 | Stage2 |Stage_Di_Ex | 11|
|5 | inst_point |IP | 47|
+------+-------------+------------------+------+
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 2292 warnings. Synthesis finished with 0 errors, 0 critical warnings and 2331 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1673.293 ; gain = 142.434 ; free physical = 108225 ; free virtual = 138487 Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 1673.281 ; gain = 142.324 ; free physical = 57567 ; free virtual = 69336
Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108235 ; free virtual = 138498 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57570 ; free virtual = 69340
INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
@ -585,9 +569,9 @@ No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis INFO: [Common 17-83] Releasing license: Synthesis
159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered. 159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully synth_design completed successfully
synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:54 . Memory (MB): peak = 1673.293 ; gain = 513.469 ; free physical = 108228 ; free virtual = 138491 synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 513.461 ; free physical = 57552 ; free virtual = 69322
WARNING: [Constraints 18-5210] No constraint will be written out. WARNING: [Constraints 18-5210] No constraint will be written out.
INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated. INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1697.305 ; gain = 0.000 ; free physical = 108229 ; free virtual = 138491 report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57537 ; free virtual = 69306
INFO: [Common 17-206] Exiting Vivado at Tue May 30 00:40:40 2023... INFO: [Common 17-206] Exiting Vivado at Tue May 30 09:13:40 2023...

BIN
VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb
View file

Binary file not shown.

102
VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt
View file

@ -1,12 +1,12 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 | Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
| Date : Tue May 30 00:40:39 2023 | Date : Tue May 30 09:13:39 2023
| Host : srv-tp04 running 64-bit Ubuntu 20.04.6 LTS | Host : insa-11267 running 64-bit Ubuntu 20.04.6 LTS
| Command : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb | Command : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb
| Design : Pipeline | Design : Pipeline
| Device : 7a35tcpg236-1 | Device : 7a35tcpg236-1
| Design State : Synthesized | Design State : Fully Placed
----------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
Utilization Design Information Utilization Design Information
@ -15,14 +15,15 @@ Table of Contents
----------------- -----------------
1. Slice Logic 1. Slice Logic
1.1 Summary of Registers by Type 1.1 Summary of Registers by Type
2. Memory 2. Slice Logic Distribution
3. DSP 3. Memory
4. IO and GT Specific 4. DSP
5. Clocking 5. IO and GT Specific
6. Specific Feature 6. Clocking
7. Primitives 7. Specific Feature
8. Black Boxes 8. Primitives
9. Instantiated Netlists 9. Black Boxes
10. Instantiated Netlists
1. Slice Logic 1. Slice Logic
-------------- --------------
@ -30,16 +31,15 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+ +-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+ +-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 28 | 0 | 20800 | 0.13 | | Slice LUTs | 0 | 0 | 20800 | 0.00 |
| LUT as Logic | 28 | 0 | 20800 | 0.13 | | LUT as Logic | 0 | 0 | 20800 | 0.00 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 | | LUT as Memory | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 47 | 0 | 41600 | 0.11 | | Slice Registers | 0 | 0 | 41600 | 0.00 |
| Register as Flip Flop | 47 | 0 | 41600 | 0.11 | | Register as Flip Flop | 0 | 0 | 41600 | 0.00 |
| Register as Latch | 0 | 0 | 41600 | 0.00 | | Register as Latch | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 0 | 0 | 16300 | 0.00 | | F7 Muxes | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 | | F8 Muxes | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+-----------+-------+ +-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type 1.1 Summary of Registers by Type
@ -56,12 +56,31 @@ Table of Contents
| 0 | Yes | - | - | | 0 | Yes | - | - |
| 0 | Yes | - | Set | | 0 | Yes | - | Set |
| 0 | Yes | - | Reset | | 0 | Yes | - | Reset |
| 13 | Yes | Set | - | | 0 | Yes | Set | - |
| 34 | Yes | Reset | - | | 0 | Yes | Reset | - |
+-------+--------------+-------------+--------------+ +-------+--------------+-------------+--------------+
2. Memory 2. Slice Logic Distribution
---------------------------
+--------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------+------+-------+-----------+-------+
| Slice | 0 | 0 | 8150 | 0.00 |
| SLICEL | 0 | 0 | | |
| SLICEM | 0 | 0 | | |
| LUT as Logic | 0 | 0 | 20800 | 0.00 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 |
| Unique Control Sets | 0 | | | |
+--------------------------+------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
--------- ---------
+----------------+------+-------+-----------+-------+ +----------------+------+-------+-----------+-------+
@ -74,7 +93,7 @@ Table of Contents
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP 4. DSP
------ ------
+-----------+------+-------+-----------+-------+ +-----------+------+-------+-----------+-------+
@ -84,13 +103,13 @@ Table of Contents
+-----------+------+-------+-----------+-------+ +-----------+------+-------+-----------+-------+
4. IO and GT Specific 5. IO and GT Specific
--------------------- ---------------------
+-----------------------------+------+-------+-----------+-------+ +-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+ +-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 1 | 0 | 106 | 0.94 | | Bonded IOB | 0 | 0 | 106 | 0.00 |
| Bonded IPADs | 0 | 0 | 10 | 0.00 | | Bonded IPADs | 0 | 0 | 10 | 0.00 |
| Bonded OPADs | 0 | 0 | 4 | 0.00 | | Bonded OPADs | 0 | 0 | 4 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 | | PHY_CONTROL | 0 | 0 | 5 | 0.00 |
@ -109,13 +128,13 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+ +-----------------------------+------+-------+-----------+-------+
5. Clocking 6. Clocking
----------- -----------
+------------+------+-------+-----------+-------+ +------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+ +------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 | | BUFGCTRL | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 20 | 0.00 | | BUFIO | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 5 | 0.00 | | MMCME2_ADV | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 5 | 0.00 | | PLLE2_ADV | 0 | 0 | 5 | 0.00 |
@ -125,7 +144,7 @@ Table of Contents
+------------+------+-------+-----------+-------+ +------------+------+-------+-----------+-------+
6. Specific Feature 7. Specific Feature
------------------- -------------------
+-------------+------+-------+-----------+-------+ +-------------+------+-------+-----------+-------+
@ -143,38 +162,25 @@ Table of Contents
+-------------+------+-------+-----------+-------+ +-------------+------+-------+-----------+-------+
7. Primitives 8. Primitives
------------- -------------
+----------+------+---------------------+ +----------+------+---------------------+
| Ref Name | Used | Functional Category | | Ref Name | Used | Functional Category |
+----------+------+---------------------+ +----------+------+---------------------+
| FDRE | 34 | Flop & Latch |
| LUT6 | 15 | LUT |
| LUT2 | 14 | LUT |
| FDSE | 13 | Flop & Latch |
| LUT5 | 4 | LUT |
| LUT4 | 2 | LUT |
| LUT3 | 2 | LUT |
| LUT1 | 2 | LUT |
| IBUF | 1 | IO |
| BUFG | 1 | Clock |
+----------+------+---------------------+
8. Black Boxes 9. Black Boxes
-------------- --------------
+-------------+------+ +----------+------+
| Ref Name | Used | | Ref Name | Used |
+-------------+------+ +----------+------+
| ControlUnit | 1 |
+-------------+------+
10. Instantiated Netlists
-------------------------
9. Instantiated Netlists
------------------------
+----------+------+ +----------+------+
| Ref Name | Used | | Ref Name | Used |
+----------+------+ +----------+------+

17
VHDL/ALU/ALU.runs/synth_1/gen_run.xml
View file

@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1685399970"> <GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1685430778">
<File Type="VDS-TIMING-PB" Name="Pipeline_timing_summary_synth.pb"/> <File Type="PA-TCL" Name="Pipeline.tcl"/>
<File Type="VDS-TIMINGSUMMARY" Name="Pipeline_timing_summary_synth.rpt"/> <File Type="REPORTS-TCL" Name="Pipeline_reports.tcl"/>
<File Type="RDS-RDS" Name="Pipeline.vds"/>
<File Type="RDS-DCP" Name="Pipeline.dcp"/> <File Type="RDS-DCP" Name="Pipeline.dcp"/>
<File Type="RDS-UTIL-PB" Name="Pipeline_utilization_synth.pb"/> <File Type="RDS-UTIL-PB" Name="Pipeline_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="Pipeline_utilization_synth.rpt"/> <File Type="RDS-UTIL" Name="Pipeline_utilization_synth.rpt"/>
<File Type="RDS-PROPCONSTRS" Name="Pipeline_drc_synth.rpt"/>
<File Type="RDS-RDS" Name="Pipeline.vds"/>
<File Type="REPORTS-TCL" Name="Pipeline_reports.tcl"/>
<File Type="PA-TCL" Name="Pipeline.tcl"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ALU.vhd"> <File Path="$PSRCDIR/sources_1/new/ALU.vhd">
@ -17,6 +14,12 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/AleaControler.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/IP.vhd"> <File Path="$PSRCDIR/sources_1/new/IP.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>

37
VHDL/ALU/ALU.runs/synth_1/project.wdf
View file

@ -1,5 +1,5 @@
version:1 version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3131:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
@ -13,7 +13,7 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3830:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3836:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
@ -28,35 +28,4 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6165663336656633613064393464616339653630353862363536393037616664:506172656e742050412070726f6a656374204944:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6165663336656633613064393464616339653630353862363536393037616664:506172656e742050412070726f6a656374204944:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f7072696d6172795f636c6f636b73:31:00:00 eof:3805747332
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f7072696d6172795f636c6f636b73:31:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f67656e6572617465645f636c6f636b73:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f67656e6572617465645f636c6f636b73:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f666f727761726465645f636c6f636b73:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f666f727761726465645f636c6f636b73:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f65787465726e616c5f64656c617973:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f65787465726e616c5f64656c617973:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f696e7075745f64656c617973:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f696e7075745f64656c617973:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f6f75747075745f64656c617973:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f6f75747075745f64656c617973:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f636f6d62696e6174696f6e616c5f7061746873:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f636f6d62696e6174696f6e616c5f7061746873:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f7068795f6578636c5f636c6f636b5f67726f757073:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f7068795f6578636c5f636c6f636b5f67726f757073:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f6c6f675f6578636c5f636c6f636b5f67726f757073:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f6c6f675f6578636c5f636c6f636b5f67726f757073:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f6173796e635f636c6f636b5f67726f757073:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f6173796e635f636c6f636b5f67726f757073:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f66616c73655f7061746873:30:00:00
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f66616c73655f7061746873:30:00:00
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636865636b73:64656661756c74:5b6e6f745f7370656369666965645d:00
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:706f73745f77697a617264:00:00
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666f726d6174:64656661756c74:5b6e6f745f7370656369666965645d:00
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6661696c5f6f6e:64656661756c74:5b6e6f745f7370656369666965645d:00
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72657475726e5f737472696e67:64656661756c74:5b6e6f745f7370656369666965645d:00
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d65737361676573:64656661756c74:5b6e6f745f7370656369666965645d:00
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666f726365:64656661756c74:5b6e6f745f7370656369666965645d:00
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d776169766564:64656661756c74:5b6e6f745f7370656369666965645d:00
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617070656e64:64656661756c74:5b6e6f745f7370656369666965645d:00
eof:2501282044

182
VHDL/ALU/ALU.runs/synth_1/runme.log
View file

@ -14,44 +14,46 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 608386 INFO: Helper process launched with PID 10853
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 108497 ; free virtual = 138755 Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.699 ; free physical = 57815 ; free virtual = 69577
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38]
INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177]
INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187] INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187]
INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193] INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193]
INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205]
INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47]
INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217] INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217]
INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229] INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229]
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240] INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240]
INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250]
INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259]
INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
INFO: [Synth 8-637] synthesizing blackbox instance 'CU' of component 'ControlUnit' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329] INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329]
WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50] INFO: [Synth 8-638] synthesizing module 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40]
WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170] INFO: [Synth 8-256] done synthesizing module 'AleaControler' (10#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40]
INFO: [Synth 8-256] done synthesizing module 'Pipeline' (10#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50]
WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170]
INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138756 Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57806 ; free virtual = 69569
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report Check Netlist: Report Check Netlist:
@ -60,46 +62,46 @@ Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+ +------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+ +------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177]
WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205]
WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Handling Custom Attributes Start Handling Custom Attributes
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757 Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757 Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7a35tcpg236-1 INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints Processing XDC Constraints
Initializing timing engine Initializing timing engine
Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
Completed Processing XDC Constraints Completed Processing XDC Constraints
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed. No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1673.293 ; gain = 0.000 ; free physical = 108244 ; free virtual = 138510 Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57555 ; free virtual = 69319
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591 Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Loading Part and Timing Information Start Loading Part and Timing Information
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Loading part: xc7a35tcpg236-1 Loading part: xc7a35tcpg236-1
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints Start Applying 'set_property' XDC Constraints
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108339 ; free virtual = 138592 Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
@ -218,9 +220,9 @@ INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too
INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261] WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108313 ; free virtual = 138566 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57618 ; free virtual = 69383
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@ -326,8 +328,8 @@ Finished Part Resource Summary
Start Cross Boundary and Area Optimization Start Cross Boundary and Area Optimization
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met Warning: Parallel synthesis criteria is not met
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55] WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51]
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51] WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55]
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline.
@ -430,7 +432,7 @@ WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][5]) is unused an
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:41 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108314 ; free virtual = 138572 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57609 ; free virtual = 69379
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@ -442,13 +444,13 @@ Report RTL Partitions:
Start Applying XDC Timing Constraints Start Applying XDC Timing Constraints
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108174 ; free virtual = 138436 Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Timing Optimization Start Timing Optimization
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433 Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@ -460,7 +462,7 @@ Report RTL Partitions:
Start Technology Mapping Start Technology Mapping
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433 Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@ -484,7 +486,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup Finished Final Netlist Cleanup
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report Check Netlist: Report Check Netlist:
@ -497,7 +499,7 @@ Report Check Netlist:
Start Renaming Generated Instances Start Renaming Generated Instances
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@ -509,73 +511,55 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy Start Rebuilding User Hierarchy
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Ports Start Renaming Generated Ports
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Handling Custom Attributes Start Handling Custom Attributes
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Nets Start Renaming Generated Nets
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Writing Synthesis Report Start Writing Synthesis Report
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report BlackBoxes: Report BlackBoxes:
+------+--------------+----------+ +-+--------------+----------+
| |BlackBox name |Instances | | |BlackBox name |Instances |
+------+--------------+----------+ +-+--------------+----------+
|1 |ControlUnit | 1| +-+--------------+----------+
+------+--------------+----------+
Report Cell Usage: Report Cell Usage:
+------+-------------------+------+ +-+-----+------+
| |Cell |Count | | |Cell |Count |
+------+-------------------+------+ +-+-----+------+
|1 |ControlUnit_bbox_0 | 1| +-+-----+------+
|2 |BUFG | 1|
|3 |LUT1 | 2|
|4 |LUT2 | 14|
|5 |LUT3 | 2|
|6 |LUT4 | 2|
|7 |LUT5 | 4|
|8 |LUT6 | 15|
|9 |FDRE | 34|
|10 |FDSE | 13|
|11 |IBUF | 1|
+------+-------------------+------+
Report Instance Areas: Report Instance Areas:
+------+-------------+------------------+------+ +------+---------+-------+------+
| |Instance |Module |Cells | | |Instance |Module |Cells |
+------+-------------+------------------+------+ +------+---------+-------+------+
|1 |top | | 89| |1 |top | | 0|
|2 | MemInst |InstructionMemory | 17| +------+---------+-------+------+
|3 | Stage1 |Stage_Li_Di | 11|
|4 | Stage2 |Stage_Di_Ex | 11|
|5 | inst_point |IP | 47|
+------+-------------+------------------+------+
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 2292 warnings. Synthesis finished with 0 errors, 0 critical warnings and 2331 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1673.293 ; gain = 142.434 ; free physical = 108225 ; free virtual = 138487 Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 1673.281 ; gain = 142.324 ; free physical = 57567 ; free virtual = 69336
Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108235 ; free virtual = 138498 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57570 ; free virtual = 69340
INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
@ -584,9 +568,9 @@ No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis INFO: [Common 17-83] Releasing license: Synthesis
159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered. 159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully synth_design completed successfully
synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:54 . Memory (MB): peak = 1673.293 ; gain = 513.469 ; free physical = 108228 ; free virtual = 138491 synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 513.461 ; free physical = 57552 ; free virtual = 69322
WARNING: [Constraints 18-5210] No constraint will be written out. WARNING: [Constraints 18-5210] No constraint will be written out.
INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated. INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1697.305 ; gain = 0.000 ; free physical = 108229 ; free virtual = 138491 report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57537 ; free virtual = 69306
INFO: [Common 17-206] Exiting Vivado at Tue May 30 00:40:40 2023... INFO: [Common 17-206] Exiting Vivado at Tue May 30 09:13:40 2023...

2
VHDL/ALU/ALU.runs/synth_1/runme.sh
View file

@ -20,7 +20,7 @@ else
fi fi
export LD_LIBRARY_PATH export LD_LIBRARY_PATH
HD_PWD='/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1' HD_PWD='/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1'
cd "$HD_PWD" cd "$HD_PWD"
HD_LOG=runme.log HD_LOG=runme.log

10
VHDL/ALU/ALU.runs/synth_1/vivado.jou
View file

@ -2,11 +2,11 @@
# Vivado v2018.2 (64-bit) # Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Tue May 30 00:39:32 2023 # Start of session at: Tue May 30 09:12:59 2023
# Process ID: 608313 # Process ID: 10840
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 # Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1
# Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl # Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds # Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou # Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou
#----------------------------------------------------------- #-----------------------------------------------------------
source Pipeline.tcl -notrace source Pipeline.tcl -notrace

BIN
VHDL/ALU/ALU.runs/synth_1/vivado.pb
View file

Binary file not shown.

11
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline.tcl Normal file
View file

@ -0,0 +1,11 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_behav.wdb Normal file
View file

Binary file not shown.

16
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_vhdl.prj Normal file
View file

@ -0,0 +1,16 @@
# compile vhdl design source files
vhdl xil_defaultlib \
"../../../../ALU.srcs/sources_1/new/ALU.vhd" \
"../../../../ALU.srcs/sources_1/new/AleaControler.vhd" \
"../../../../ALU.srcs/sources_1/new/IP.vhd" \
"../../../../ALU.srcs/sources_1/new/InstructionMemory.vhd" \
"../../../../ALU.srcs/sources_1/new/Memory.vhd" \
"../../../../ALU.srcs/sources_1/new/Registers.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Li_Di.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" \
"../../../../ALU.srcs/sources_1/new/Pipeline.vhd" \
# Do not sort compile order
nosort

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl
View file

@ -8,4 +8,4 @@ if { [string length $curr_wave] == 0 } {
} }
} }
run 1000ns run 50us

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb
View file

Binary file not shown.

3
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_vhdl.prj
View file

@ -1,6 +1,7 @@
# compile vhdl design source files # compile vhdl design source files
vhdl xil_defaultlib \ vhdl xil_defaultlib \
"../../../../ALU.srcs/sources_1/new/ALU.vhd" \ "../../../../ALU.srcs/sources_1/new/ALU.vhd" \
"../../../../ALU.srcs/sources_1/new/AleaControler.vhd" \
"../../../../ALU.srcs/sources_1/new/IP.vhd" \ "../../../../ALU.srcs/sources_1/new/IP.vhd" \
"../../../../ALU.srcs/sources_1/new/InstructionMemory.vhd" \ "../../../../ALU.srcs/sources_1/new/InstructionMemory.vhd" \
"../../../../ALU.srcs/sources_1/new/Memory.vhd" \ "../../../../ALU.srcs/sources_1/new/Memory.vhd" \
@ -10,7 +11,7 @@ vhdl xil_defaultlib \
"../../../../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" \ "../../../../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Li_Di.vhd" \ "../../../../ALU.srcs/sources_1/new/Stage_Li_Di.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" \ "../../../../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" \
"../../../../ALU.srcs/sim_1/new/VHDL.vhd" \ "../../../../ALU.srcs/sim_1/new/test_total.vhd" \
# Do not sort compile order # Do not sort compile order
nosort nosort

119
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
View file

@ -217,3 +217,122 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Pro
INFO: [VRFC 10-307] analyzing entity Test_total INFO: [VRFC 10-307] analyzing entity Test_total
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_total INFO: [VRFC 10-307] analyzing entity Test_total
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity IP
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity DataMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Registers
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Stage_Di_Ex
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Stage_Ex_Mem
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Stage_Li_Di
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Stage_Mem_Re
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_total
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_total
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Registers
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Registers
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity IP
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity DataMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity DataMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_total
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_total
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
ERROR: [VRFC 10-825] illegal identifier : __En [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:38]
ERROR: [VRFC 10-1504] unit instructionmemory ignored due to previous errors [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35]
INFO: [VRFC 10-240] VHDL file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity DataMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity AleaControler
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity DataMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity DataMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity DataMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity DataMemory

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator # Simulator : Xilinx Vivado Simulator
# Description : Script for compiling the simulation design source files # Description : Script for compiling the simulation design source files
# #
# Generated by Vivado on Tue May 30 00:45:29 CEST 2023 # Generated by Vivado on Tue May 30 13:26:07 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# #
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

1
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log
View file

@ -3,6 +3,5 @@ Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total -log elaborate.log Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total -log elaborate.log
Using 8 slave threads. Using 8 slave threads.
Starting static elaboration Starting static elaboration
WARNING: [VRFC 10-122] controlunit remains a black-box since it has no binding entity [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329]
Completed static elaboration Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator # Simulator : Xilinx Vivado Simulator
# Description : Script for elaborating the compiled design # Description : Script for elaborating the compiled design
# #
# Generated by Vivado on Tue May 30 00:45:30 CEST 2023 # Generated by Vivado on Tue May 30 13:26:09 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# #
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log
View file

@ -1,2 +0,0 @@
Vivado Simulator 2018.2
Time resolution is 1 ps

4
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator # Simulator : Xilinx Vivado Simulator
# Description : Script for simulating the design by launching the simulator # Description : Script for simulating the design by launching the simulator
# #
# Generated by Vivado on Tue May 30 00:45:32 CEST 2023 # Generated by Vivado on Tue May 30 13:26:10 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# #
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
@ -23,4 +23,4 @@ then
exit $RETVAL exit $RETVAL
fi fi
} }
ExecStep xsim Test_total_behav -key {Behavioral:sim_1:Functional:Test_total} -tclbatch Test_total.tcl -view /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log ExecStep xsim Test_total_behav -key {Behavioral:sim_1:Functional:Test_total} -tclbatch Test_total.tcl -view /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log

14
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
View file

@ -2,11 +2,11 @@
# Webtalk v2018.2 (64-bit) # Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon May 29 21:55:04 2023 # Start of session at: Tue May 30 08:48:34 2023
# Process ID: 509586 # Process ID: 5876
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim # Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace # Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log # Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou # Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#----------------------------------------------------------- #-----------------------------------------------------------
source /home/rlacroix/Bureau/4ir/syst -notrace source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace

17
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
View file

@ -2,13 +2,12 @@
# Webtalk v2018.2 (64-bit) # Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon May 29 21:55:04 2023 # Start of session at: Tue May 30 08:48:34 2023
# Process ID: 509586 # Process ID: 5876
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim # Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace # Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log # Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou # Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#----------------------------------------------------------- #-----------------------------------------------------------
source /home/rlacroix/Bureau/4ir/syst -notrace source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
couldn't read file "/home/rlacroix/Bureau/4ir/syst": no such file or directory INFO: [Common 17-206] Exiting Webtalk at Tue May 30 08:48:35 2023...
INFO: [Common 17-206] Exiting Webtalk at Mon May 29 21:55:04 2023...

12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.jou
View file

@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon May 29 19:26:30 2023
# Process ID: 334386
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace

13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.log
View file

@ -1,13 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon May 29 19:26:30 2023
# Process ID: 334386
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Mon May 29 19:26:31 2023...

12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.jou Normal file
View file

@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon May 29 21:55:04 2023
# Process ID: 509586
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/rlacroix/Bureau/4ir/syst -notrace

14
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.log Normal file
View file

@ -0,0 +1,14 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon May 29 21:55:04 2023
# Process ID: 509586
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/rlacroix/Bureau/4ir/syst -notrace
couldn't read file "/home/rlacroix/Bureau/4ir/syst": no such file or directory
INFO: [Common 17-206] Exiting Webtalk at Mon May 29 21:55:04 2023...

12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.jou Normal file
View file

@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Tue May 30 08:48:10 2023
# Process ID: 5794
# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace

13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.log Normal file
View file

@ -0,0 +1,13 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Tue May 30 08:48:10 2023
# Process ID: 5794
# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue May 30 08:48:11 2023...

12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou
View file

@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Sun May 14 22:27:00 2023
# Process ID: 831173
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace

13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log
View file

@ -1,13 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Sun May 14 22:27:00 2023
# Process ID: 831173
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Sun May 14 22:27:01 2023...

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb
View file

Binary file not shown.

1
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/Compile_Options.txt Normal file
View file

@ -0,0 +1 @@
-wto "aef36ef3a0d94dac9e6058b656907afd" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "Pipeline_behav" "xil_defaultlib.Pipeline" -log "elaborate.log"

1
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/TempBreakPointFile.txt Normal file
View file

@ -0,0 +1 @@
Breakpoint File Version 1.0

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_0.lnx64.o Normal file
View file

Binary file not shown.

122
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.c Normal file
View file

@ -0,0 +1,122 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern void execute_76(char*, char *);
extern void execute_77(char*, char *);
extern void execute_78(char*, char *);
extern void execute_79(char*, char *);
extern void execute_80(char*, char *);
extern void execute_81(char*, char *);
extern void execute_82(char*, char *);
extern void execute_87(char*, char *);
extern void execute_51(char*, char *);
extern void execute_52(char*, char *);
extern void execute_58(char*, char *);
extern void execute_60(char*, char *);
extern void execute_62(char*, char *);
extern void execute_63(char*, char *);
extern void execute_64(char*, char *);
extern void execute_66(char*, char *);
extern void execute_68(char*, char *);
extern void execute_69(char*, char *);
extern void execute_71(char*, char *);
extern void execute_73(char*, char *);
extern void execute_75(char*, char *);
extern void execute_84(char*, char *);
extern void execute_85(char*, char *);
extern void execute_86(char*, char *);
extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[26] = {(funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_87, (funcp)execute_51, (funcp)execute_52, (funcp)execute_58, (funcp)execute_60, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_66, (funcp)execute_68, (funcp)execute_69, (funcp)execute_71, (funcp)execute_73, (funcp)execute_75, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 26;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/Pipeline_behav/xsim.reloc", (void **)funcTab, 26);
iki_vhdl_file_variable_register(dp + 24592);
iki_vhdl_file_variable_register(dp + 24648);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/Pipeline_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/Pipeline_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/Pipeline_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/Pipeline_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/Pipeline_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.lnx64.o Normal file
View file

Binary file not shown.

5
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/.xsim_webtallk.info Normal file
View file

@ -0,0 +1,5 @@
1685429290
1685429313
6
1
aef36ef3a0d94dac9e6058b656907afd

53
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.html Normal file
View file

@ -0,0 +1,53 @@
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2258646</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Tue May 30 08:48:33 2023</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>LIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2018.2 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>aef36ef3a0d94dac9e6058b656907afd</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>6ef722b6-53ec-42dc-bc5c-9d79054a9923</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>6ef722b6-53ec-42dc-bc5c-9d79054a9923</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz</TD>
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>3200.000 MHz</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Ubuntu</TD>
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>Ubuntu 20.04.6 LTS</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>67.000 GB</TD>
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>command=xsim</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>iteration=0</TD>
<TD>runtime=1 us</TD>
<TD>simulation_memory=118556_KB</TD>
<TD>simulation_time=0.01_sec</TD>
</TR><TR ALIGN='LEFT'> <TD>trace_waveform=true</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
</BODY>
</HTML>

38
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.wdm Normal file
View file

@ -0,0 +1,38 @@
version = "1.0";
clients =
(
{ client_name = "project";
rules = (
{
context="software_version_and_target_device";
xml_map="software_version_and_target_device";
html_map="software_version_and_target_device";
html_format="UserEnvStyle";
},
{
context="user_environment";
xml_map="user_environment";
html_map="user_environment";
html_format="UserEnvStyle";
}
);
},
{ client_name = "xsim";
rules = (
{
context="xsim\\command_line_options";
xml_map="xsim\\command_line_options";
html_map="xsim\\command_line_options";
html_format="UnisimStatsStyle";
},
{
context="xsim\\usage";
xml_map="xsim\\usage";
html_map="xsim\\usage";
html_format="UnisimStatsStyle";
}
);
}
);

44
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.xml Normal file
View file

@ -0,0 +1,44 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Tue May 30 08:48:34 2023'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2258646" description="" />
<keyValuePair key="date_generated" value="Tue May 30 08:48:33 2023" description="" />
<keyValuePair key="os_platform" value="LIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.2 (64-bit)" description="" />
<keyValuePair key="project_id" value="aef36ef3a0d94dac9e6058b656907afd" description="" />
<keyValuePair key="project_iteration" value="2" description="" />
<keyValuePair key="random_id" value="6ef722b6-53ec-42dc-bc5c-9d79054a9923" description="" />
<keyValuePair key="registration_id" value="6ef722b6-53ec-42dc-bc5c-9d79054a9923" description="" />
<keyValuePair key="route_design" value="FALSE" description="" />
<keyValuePair key="target_device" value="not_applicable" description="" />
<keyValuePair key="target_family" value="not_applicable" description="" />
<keyValuePair key="target_package" value="not_applicable" description="" />
<keyValuePair key="target_speed" value="not_applicable" description="" />
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
</section>
<section name="user_environment" level="1" order="2" description="">
<keyValuePair key="cpu_name" value="Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" description="" />
<keyValuePair key="cpu_speed" value="3200.000 MHz" description="" />
<keyValuePair key="os_name" value="Ubuntu" description="" />
<keyValuePair key="os_release" value="Ubuntu 20.04.6 LTS" description="" />
<keyValuePair key="system_ram" value="67.000 GB" description="" />
<keyValuePair key="total_processors" value="1" description="" />
</section>
<section name="vivado_usage" level="1" order="3" description="">
</section>
<section name="xsim" level="1" order="4" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="command" value="xsim" description="" />
</section>
<section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="0" description="" />
<keyValuePair key="runtime" value="1 us" description="" />
<keyValuePair key="simulation_memory" value="118556_KB" description="" />
<keyValuePair key="simulation_time" value="0.01_sec" description="" />
<keyValuePair key="trace_waveform" value="true" description="" />
</section>
</section>
</section>
</webTalkData>

32
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl Normal file
View file

@ -0,0 +1,32 @@
webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Tue May 30 13:19:41 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "5" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "3200.000 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.02_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "118560_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3468895090 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.dbg Normal file
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.mem Normal file
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.reloc Normal file
View file

Binary file not shown.

12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.rlx Normal file
View file

@ -0,0 +1,12 @@
{
crc : 6748289172475844442 ,
ccp_crc : 0 ,
cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Pipeline_behav xil_defaultlib.Pipeline" ,
buildDate : "Jun 14 2018" ,
buildTime : "20:07:38" ,
linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/Pipeline_behav/xsimk\" \"xsim.dir/Pipeline_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/Pipeline_behav/obj/xsim_1.lnx64.o\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simulator_kernel.so\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simbridge_kernel.so\"" ,
aggregate_nets :
[
]
}

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.rtti Normal file
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.svtype Normal file
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.type Normal file
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.xdbg Normal file
View file

Binary file not shown.

41
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimSettings.ini Normal file
View file

@ -0,0 +1,41 @@
[General]
ARRAY_DISPLAY_LIMIT=1024
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=65536
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=75
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
OBJECT_NAME_COLUMN_WIDTH=75
OBJECT_VALUE_COLUMN_WIDTH=75
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1

0
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimcrash.log Normal file
View file

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimk Executable file
View file

Binary file not shown.

7
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimkernel.log Normal file
View file

@ -0,0 +1,7 @@
Running: xsim.dir/Pipeline_behav/xsimk -simmode gui -wdb Pipeline_behav.wdb -simrunnum 0 -socket 54161
Design successfully loaded
Design Loading Memory Usage: 32724 KB (Peak: 32776 KB)
Design Loading CPU Usage: 0 ms
Simulation completed
Simulation Memory Usage: 118560 KB (Peak: 179996 KB)
Simulation CPU Usage: 20 ms

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o
View file

Binary file not shown.

31
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c
View file

@ -43,38 +43,41 @@
#define alloca _alloca #define alloca _alloca
#endif #endif
typedef void (*funcp)(char *, char *); typedef void (*funcp)(char *, char *);
extern void execute_84(char*, char *); extern void execute_89(char*, char *);
extern void execute_76(char*, char *); extern void execute_90(char*, char *);
extern void execute_77(char*, char *);
extern void execute_78(char*, char *);
extern void execute_79(char*, char *); extern void execute_79(char*, char *);
extern void execute_80(char*, char *); extern void execute_80(char*, char *);
extern void execute_81(char*, char *); extern void execute_81(char*, char *);
extern void execute_82(char*, char *); extern void execute_82(char*, char *);
extern void execute_83(char*, char *); extern void execute_83(char*, char *);
extern void execute_51(char*, char *); extern void execute_84(char*, char *);
extern void execute_52(char*, char *); extern void execute_85(char*, char *);
extern void execute_58(char*, char *); extern void execute_88(char*, char *);
extern void execute_53(char*, char *);
extern void execute_54(char*, char *);
extern void execute_60(char*, char *); extern void execute_60(char*, char *);
extern void execute_62(char*, char *); extern void execute_62(char*, char *);
extern void execute_63(char*, char *);
extern void execute_64(char*, char *); extern void execute_64(char*, char *);
extern void execute_65(char*, char *);
extern void execute_66(char*, char *); extern void execute_66(char*, char *);
extern void execute_68(char*, char *); extern void execute_68(char*, char *);
extern void execute_69(char*, char *); extern void execute_70(char*, char *);
extern void execute_71(char*, char *); extern void execute_71(char*, char *);
extern void execute_73(char*, char *); extern void execute_73(char*, char *);
extern void execute_75(char*, char *); extern void execute_75(char*, char *);
extern void execute_76(char*, char *);
extern void execute_78(char*, char *);
extern void execute_87(char*, char *);
extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[24] = {(funcp)execute_84, (funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_51, (funcp)execute_52, (funcp)execute_58, (funcp)execute_60, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_66, (funcp)execute_68, (funcp)execute_69, (funcp)execute_71, (funcp)execute_73, (funcp)execute_75, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; funcp funcTab[27] = {(funcp)execute_89, (funcp)execute_90, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_88, (funcp)execute_53, (funcp)execute_54, (funcp)execute_60, (funcp)execute_62, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_68, (funcp)execute_70, (funcp)execute_71, (funcp)execute_73, (funcp)execute_75, (funcp)execute_76, (funcp)execute_78, (funcp)execute_87, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 24; const int NumRelocateId= 27;
void relocate(char *dp) void relocate(char *dp)
{ {
iki_relocate(dp, "xsim.dir/Test_total_behav/xsim.reloc", (void **)funcTab, 24); iki_relocate(dp, "xsim.dir/Test_total_behav/xsim.reloc", (void **)funcTab, 27);
iki_vhdl_file_variable_register(dp + 23824); iki_vhdl_file_variable_register(dp + 23784);
iki_vhdl_file_variable_register(dp + 23880); iki_vhdl_file_variable_register(dp + 23840);
/*Populate the transaction function pointer field in the whole net structure */ /*Populate the transaction function pointer field in the whole net structure */

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o
View file

Binary file not shown.

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info
View file

@ -1,5 +1,5 @@
1685389741 1685389741
1685390103 1685390103
18 104
1 1
aef36ef3a0d94dac9e6058b656907afd aef36ef3a0d94dac9e6058b656907afd

22
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl
View file

@ -1,6 +1,6 @@
webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/ webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/
webtalk_register_client -client project webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Tue May 30 00:50:26 2023" -context "software_version_and_target_device" webtalk_add_data -client project -key date_generated -value "Tue May 30 13:19:40 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
@ -14,19 +14,19 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "17" -context "software_version_and_target_device" webtalk_add_data -client project -key project_iteration -value "103" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "900.000 MHz" -context "user_environment" webtalk_add_data -client project -key cpu_speed -value "2757.340 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "2" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment" webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment"
webtalk_register_client -client xsim webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" webtalk_add_data -client xsim -key runtime -value "50 us" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "118556_KB" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Memory -value "122660_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2174300005 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>" webtalk_transmit -clientid 653659988 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate webtalk_terminate

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc
View file

Binary file not shown.

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx
View file

@ -1,6 +1,6 @@
{ {
crc : 747761180757353282 , crc : 5669434041321685966 ,
ccp_crc : 0 , ccp_crc : 0 ,
cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total" , cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total" ,
buildDate : "Jun 14 2018" , buildDate : "Jun 14 2018" ,

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg
View file

Binary file not shown.

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimSettings.ini
View file

@ -19,7 +19,7 @@ INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true VARIABLE_OBJECT_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=75 SCOPE_NAME_COLUMN_WIDTH=169
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
OBJECT_NAME_COLUMN_WIDTH=75 OBJECT_NAME_COLUMN_WIDTH=75

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk
View file

Binary file not shown.

9
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log
View file

@ -1,7 +1,4 @@
Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb -simrunnum 0 -socket 36415 Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb -simrunnum 0 -socket 58539
Design successfully loaded Design successfully loaded
Design Loading Memory Usage: 32720 KB (Peak: 32772 KB) Design Loading Memory Usage: 32724 KB (Peak: 32776 KB)
Design Loading CPU Usage: 60 ms Design Loading CPU Usage: 10 ms
Simulation completed
Simulation Memory Usage: 118556 KB (Peak: 179992 KB)
Simulation CPU Usage: 60 ms

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb Normal file
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory.vdb
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ip.vdb
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_di_ex.vdb
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_ex_mem.vdb
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_li_di.vdb
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_mem_re.vdb
View file

Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb
View file

Binary file not shown.

23
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
View file

@ -2,14 +2,15 @@
2018.2 2018.2
Jun 14 2018 Jun 14 2018
20:07:38 20:07:38
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1685389246,vhdl,,,,test_alu,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685437044,vhdl,,,,test_total,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685389246,vhdl,,,,alu,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685389246,vhdl,,,,alu,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685386043,vhdl,,,,ip,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd,1685444515,vhdl,,,,aleacontroler,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685397138,vhdl,,,,instructionmemory,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685436168,vhdl,,,,ip,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685386043,vhdl,,,,datamemory,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685439807,vhdl,,,,instructionmemory,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685397138,vhdl,,,,pipeline,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685445542,vhdl,,,,datamemory,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685386043,vhdl,,,,registers,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685443285,vhdl,,,,pipeline,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685435532,vhdl,,,,registers,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd,1685386043,vhdl,,,,stage_li_di,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd,1685386043,vhdl,,,,stage_mem_re,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd,1685386043,vhdl,,,,stage_li_di,,,,,,,,
/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd,1685386043,vhdl,,,,stage_mem_re,,,,,,,,

64
VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd Normal file
View file

@ -0,0 +1,64 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.05.2023 17:40:52
-- Design Name:
-- Module Name: Test_Alu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_total is
-- Port ( );
end Test_total;
architecture Behavioral of test_total is
component Pipeline
Port ( rst : in STD_LOGIC; Clk : in STD_LOGIC);
end component;
constant clock_period : time := 10 ns;
signal clock : Std_logic := '0';
signal rst : Std_logic := '1';
begin
-- instantiate
Pl : Pipeline PORT MAP (
Rst => rst,
Clk => clock
);
Clock_process : process
begin
clock <= not(clock);
wait for 100ns;
end process;
rst <= '0' after 50ns;
end Behavioral;

62
VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd
View file

@ -25,43 +25,49 @@ use IEEE.STD_LOGIC_UNSIGNED.all;
-- we freeze IP on the current instruction -- we freeze IP on the current instruction
-- we insert NOPs in the LI_DI OP while there is a conflict in order to let the problematic instruction finish -- we insert NOPs in the LI_DI OP while there is a conflict in order to let the problematic instruction finish
entity ControlUnit is entity AleaControler is
Port ( Port (
-- get the current op and variables from the 3 pipelines stages that can interract -- get the current op and variables from the 3 pipelines stages that can interract
Op_DI, Op_EX, Op_Mem : in STD_LOGIC_VECTOR (7 downto 0); Op_DI, Op_EX, Op_Mem, Op_Re : in STD_LOGIC_VECTOR (7 downto 0);
A_EX, A_Mem : in STD_LOGIC_VECTOR (7 downto 0); A_EX, A_Mem, A_Re : in STD_LOGIC_VECTOR (7 downto 0);
B_DI : in STD_LOGIC_VECTOR (7 downto 0); B_DI : in STD_LOGIC_VECTOR (7 downto 0);
C_DI : in STD_LOGIC_VECTOR (7 downto 0); C_DI : in STD_LOGIC_VECTOR (7 downto 0);
CNTRL : out STD_LOGIC); CNTRL : out STD_LOGIC);
end ControlUnit; end AleaControler;
architecture Behavioral of ControlUnit is architecture Behavioral of AleaControler is
signal alea_DI_EX or alea_DI_MEM: STD_LOGIC; signal alea_DI_EX, alea_DI_MEM: STD_LOGIC;
signal is_LI_arithmetic, is_DI_arithmetic: STD_LOGIC; signal is_LI_arithmetic, is_DI_arithmetic: STD_LOGIC;
begin begin
CNTRL <= alea_DI_EX or alea_DI_MEM; -- either a problem between the 1st and 2nd or 1st and 3rd CNTRL <= -- either a problem between the 1st and 2nd or 1st and 3rd
'1' when
-- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read)
(
-- check Op1 & Op2
((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_EX /= x"08" and Op_EX /= x"ff")) and
-- check Registers are the same
((A_Ex = B_DI) or (A_EX = C_DI))
) or
-- read after write : Op1 other than STORE/NOP, op3 other than AFC/NOP, R(write) = R(read)
(
-- check Op1 & Op2
((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_Mem /= x"08" and Op_Mem /= x"ff")) and
-- check Registers are the same
((A_Mem = B_DI) or (A_Mem = C_DI))
) or
-- read after write : Op1 other than STORE/NOP, op4 other than AFC/NOP, R(write) = R(read)
(
-- check Op1 & Op2
((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_Re /= x"08" and Op_Re /= x"ff")) and
alea_DI_EX <= '1' when -- check Registers are the same
-- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read) ((A_Re = B_DI) or (A_Re = C_DI))
( )
-- check Op1 & Op2 else '0';
(OP_DI != x"08" or OP_DI != x"ff") and (Op_EX != x"06" Op_EX != x"ff") and
-- check Registers are the same
(A_Ex = B_DI) or (A_EX = C_DI)
)
else '0';
alea_DI_Mem <= '1' when
-- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read)
(
-- check Op1 & Op2
(OP_DI != x"08" or OP_DI != x"ff") and (Op_Mem != x"06" Op_Mem!= x"ff") and
-- check Registers are the same
(A_Mem = B_DI) or (A_Mem = C_DI)
)
else '0';
end Behavioral; end Behavioral;

4
VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd
View file

@ -35,7 +35,7 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity IP is entity IP is
Port ( CLK : in STD_LOGIC; Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC; -- rst when 0 RST : in STD_LOGIC; -- rst when 1
LOAD : in STD_LOGIC; LOAD : in STD_LOGIC;
EN : in STD_LOGIC; -- enable when 0 EN : in STD_LOGIC; -- enable when 0
Din : in STD_LOGIC_VECTOR (7 downto 0); Din : in STD_LOGIC_VECTOR (7 downto 0);
@ -49,7 +49,7 @@ begin
begin begin
wait until rising_edge(CLK); wait until rising_edge(CLK);
if (RST = '0') then if (RST = '1') then
aux <= x"00"; aux <= x"00";
elsif (LOAD = '1') then elsif (LOAD = '1') then
aux <= Din; aux <= Din;

13
VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd
View file

@ -40,14 +40,9 @@ end InstructionMemory;
architecture Behavioral of InstructionMemory is architecture Behavioral of InstructionMemory is
type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0); type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0);
signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000")); -- signal Mem : Mem_array := ((x"06000200"),(x"08020000"),(x"07000200"),(x"08000000"),(x"06000200"),(x"08020000"),(x"07000000"),(x"07010200"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08010000"),others => (x"ff000000"));
signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000600"),(x"08030000"),(x"07000000"),(x"07010300"),(x"02000001"),(x"08040000"),(x"07000400"),(x"08010000"),(x"06000200"),(x"08030000"),(x"07000100"),(x"07010300"),(x"04000001"),(x"08040000"),(x"07000400"),(x"07010000"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000"));
-- signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000"));
begin begin
Inst_out <= Mem(to_integer(unsigned(Addr)));
process
begin
wait until clk'event and clk = '1';
Inst_out <= Mem(to_integer(unsigned(Addr)));
end process;
end Behavioral; end Behavioral;

13
VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd
View file

@ -43,21 +43,18 @@ end DataMemory;
architecture Behavioral of DataMemory is architecture Behavioral of DataMemory is
type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0); type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0);
signal Mem : Mem_array; signal Mem : Mem_array := (others => x"00");
begin begin
process process
begin begin
wait until clk'event and clk = '1'; wait until clk'event and clk = '1';
if Rst = '0' then -- Reset if Rst = '1' then -- Reset
mem <= (others => x"00"); mem <= (others => x"00");
else if Rw = '1' then --reading else if Rw = '0' then --writing
Data_out <= Mem(to_integer(unsigned(Addr)));
else -- writting
Mem(to_integer(unsigned(Addr))) <= Data_in; Mem(to_integer(unsigned(Addr))) <= Data_in;
end if; end if;
end if; end if;
end process; end process;
Data_out <= Mem(to_integer(unsigned(Addr))); --reading
end Behavioral; end Behavioral;

60
VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
View file

@ -32,22 +32,21 @@ use IEEE.STD_LOGIC_1164.ALL;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity Pipeline is entity Pipeline is
Port ( Clk : in STD_LOGIC); Port (RST : in STD_LOGIC; Clk : in STD_LOGIC);
end Pipeline; end Pipeline;
architecture Behavioral of Pipeline is architecture Behavioral of Pipeline is
component IP is component IP is
port ( CLK : in STD_LOGIC; port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC; -- rst when 0 RST : in STD_LOGIC; -- rst when 1
LOAD : in STD_LOGIC; LOAD : in STD_LOGIC;
EN : in STD_LOGIC; -- enable when 1 EN : in STD_LOGIC; -- enable when 0
Din : in STD_LOGIC_VECTOR (7 downto 0); Din : in STD_LOGIC_VECTOR (7 downto 0);
Dout : out STD_LOGIC_VECTOR (7 downto 0)); Dout : out STD_LOGIC_VECTOR (7 downto 0));
end component; end component;
signal IP_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal IP_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal Rst : STD_LOGIC; -- to modify
component InstructionMemory component InstructionMemory
Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
@ -55,7 +54,7 @@ architecture Behavioral of Pipeline is
Inst_out : out STD_LOGIC_VECTOR (31 downto 0)); Inst_out : out STD_LOGIC_VECTOR (31 downto 0));
end component; end component;
signal Li : STD_LOGIC_VECTOR (31 downto 0) := (others => '0'); signal Li : STD_LOGIC_VECTOR (31 downto 0) := (others => '1');
component Stage_Li_Di component Stage_Li_Di
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
@ -70,8 +69,6 @@ architecture Behavioral of Pipeline is
); );
end component; end component;
signal Li_A, Li_Op, Li_B, Li_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
component Registers component Registers
Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0); Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0);
Addr_B : in STD_LOGIC_VECTOR (3 downto 0); Addr_B : in STD_LOGIC_VECTOR (3 downto 0);
@ -85,8 +82,8 @@ architecture Behavioral of Pipeline is
); );
end component; end component;
signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal Di_RegB, Di_FinalB, Di_C2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal Di_RegB, Di_FinalB, Di_C2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
component Stage_Di_Ex component Stage_Di_Ex
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
@ -101,7 +98,7 @@ architecture Behavioral of Pipeline is
); );
end component; end component;
signal Ex_A, Ex_Op, Ex_B, Ex_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal Ex_A, Ex_Op, Ex_B, Ex_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
component ALU component ALU
Port ( A : in STD_LOGIC_VECTOR (7 downto 0); Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
@ -115,7 +112,7 @@ architecture Behavioral of Pipeline is
); );
end component; end component;
signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag : STD_LOGIC; signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag : STD_LOGIC;
component Stage_Ex_Mem component Stage_Ex_Mem
@ -129,9 +126,9 @@ architecture Behavioral of Pipeline is
); );
end component; end component;
signal Mem_A, Mem_Op, Mem_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal Mem_A, Mem_Op, Mem_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal Mem_RW : STD_LOGIC; signal Mem_RW : STD_LOGIC;
signal Mem_Addr, Mem_Data_Out, Mem_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal Mem_Addr, Mem_Data_Out, Mem_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
component DataMemory component DataMemory
Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
@ -153,24 +150,24 @@ architecture Behavioral of Pipeline is
Out_Op : out STD_LOGIC_VECTOR (7 downto 0) Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
); );
end component; end component;
component ControlUnit is component AleaControler is
Port ( Op_DI, Op_EX, Op_Mem : in STD_LOGIC_VECTOR (7 downto 0); Port ( Op_DI, Op_EX, Op_Mem, Op_Re : in STD_LOGIC_VECTOR (7 downto 0);
A_EX, A_Mem : in STD_LOGIC_VECTOR (7 downto 0); A_EX, A_Mem, A_Re : in STD_LOGIC_VECTOR (7 downto 0);
B_DI : in STD_LOGIC_VECTOR (7 downto 0); B_DI : in STD_LOGIC_VECTOR (7 downto 0);
C_DI : in STD_LOGIC_VECTOR (7 downto 0); C_DI : in STD_LOGIC_VECTOR (7 downto 0);
CNTRL : out STD_LOGIC CNTRL : out STD_LOGIC
); );
end component; end component;
signal Re_A, Re_Op, Re_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal Re_A, Re_Op, Re_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal Re_W : STD_LOGIC; signal Re_W : STD_LOGIC;
-- to control jumping and where to jump -- to control jumping and where to jump
signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal jump : STD_LOGIC; signal jump : STD_LOGIC;
signal nop_Cntrl : STD_LOGIC; signal nop_Cntrl : STD_LOGIC;
signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
begin begin
-- instructionPointer -- instructionPointer
@ -178,7 +175,7 @@ inst_point : IP port map (
CLK=> clk, CLK=> clk,
Dout=> IP_out, Dout=> IP_out,
Din => addr_to_jump, Din => addr_to_jump,
RST => '1', RST => rst,
EN => nop_Cntrl, EN => nop_Cntrl,
LOAD => jump); LOAD => jump);
@ -272,7 +269,7 @@ Stage4 : Stage_Mem_Re PORT MAP (
-- DIV x"04" -- DIV x"04"
-- COP x"05" -- COP x"05"
-- AFC x"06" -- AFC x"06"
-- LOAD x"07" -- LOAD x"07"OP_DI
-- STORE x"08" -- STORE x"08"
-- INF x"09" -- INF x"09"
-- SUP x"0A" -- SUP x"0A"
@ -289,7 +286,8 @@ Stage4 : Stage_Mem_Re PORT MAP (
-- Mux post registers -- Mux post registers
Di_FinalB <= Di_B when Di_FinalB <= Di_B when
Di_OP = x"06" -- AFC Di_OP = x"06" or -- AFC
Di_OP = x"07" -- LOAD
else Di_RegB; else Di_RegB;
-- Mux post ALU -- Mux post ALU
@ -312,23 +310,23 @@ Mem_FinalB <= Mem_B when
or Mem_Op = x"03" -- SUB or Mem_Op = x"03" -- SUB
or Mem_Op = x"02" -- MUL or Mem_Op = x"02" -- MUL
or Mem_Op = x"04" -- DIV or Mem_Op = x"04" -- DIV
else Mem_FinalB ; --LOAD & STORE else Mem_Data_out ; --LOAD & STORE
-- Mux pre data memory -- Mux pre data memory
Mem_Addr <= Mem_B when Mem_Op = x"07" --LOAD Mem_Addr <= Mem_B when Mem_Op = x"07" --LOAD
else Mem_A; --STORE else Mem_A; --STORE
-- LC pre data memory -- LC pre data memory
Mem_RW <= '1' when Mem_Op = x"07" --LOAD Mem_RW <= '0' when Mem_Op = x"08" --STORE
else '0'; --STORE else '1'; --STORE
-- LC post Pip_Mem_Re -- LC post Pip_Mem_Re
Re_W <= '0' when Re_Op = x"08" --STORE Re_W <= '0' when Re_Op = x"08" or Re_Op = x"ff" --STORE
else '1'; else '1';
CU : ControlUnit port map ( CU : AleaControler port map (
Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op, Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op, Op_Re => Mem_Op,
A_EX => Di_A, A_Mem => Ex_A, A_EX => Di_A, A_Mem => Ex_A, A_Re => Mem_A,
B_DI => Li(15 downto 8), B_DI => Li(15 downto 8),
C_DI => Li(7 downto 0), C_DI => Li(7 downto 0),
CNTRL => nop_Cntrl); CNTRL => nop_Cntrl);
@ -336,4 +334,4 @@ CU : ControlUnit port map (
-- in case of alea : replace li(31 downto 24) by NOP -- in case of alea : replace li(31 downto 24) by NOP
OP_LI_DI <= X"ff" when nop_Cntrl='1' else Li(31 downto 24); OP_LI_DI <= X"ff" when nop_Cntrl='1' else Li(31 downto 24);
end Behavioral; end Behavioral;

4
VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd
View file

@ -46,13 +46,13 @@ end Registers;
architecture Behavioral of Registers is architecture Behavioral of Registers is
type Reg_array is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0); type Reg_array is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0);
signal Regs : Reg_array; signal Regs : Reg_array := (others => x"00");
begin begin
process process
begin begin
wait until clk'event and clk = '1'; wait until clk'event and clk = '1';
if Rst = '0' then -- Reset if Rst = '1' then -- Reset
Regs <= (others => x"00"); Regs <= (others => x"00");
elsif W = '1' then -- Writing elsif W = '1' then -- Writing
Regs(to_integer(unsigned(Addr_W))) <= Data; Regs(to_integer(unsigned(Addr_W))) <= Data;

19
VHDL/ALU/ALU.xpr
View file

@ -3,7 +3,7 @@
<!-- --> <!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --> <!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="38" Path="/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr"> <Project Version="7" Minor="38" Path="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr">
<DefaultLaunch Dir="$PRUNDIR"/> <DefaultLaunch Dir="$PRUNDIR"/>
<Configuration> <Configuration>
<Option Name="Id" Val="aef36ef3a0d94dac9e6058b656907afd"/> <Option Name="Id" Val="aef36ef3a0d94dac9e6058b656907afd"/>
@ -33,7 +33,7 @@
<Option Name="DSAVendor" Val="xilinx"/> <Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="basys3"/> <Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="60"/> <Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="82"/> <Option Name="WTXSimLaunchSim" Val="136"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
@ -67,6 +67,12 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/AleaControler.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/IP.vhd"> <File Path="$PSRCDIR/sources_1/new/IP.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@ -142,8 +148,15 @@
</FileSet> </FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1"> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/test_total.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/VHDL.vhd"> <File Path="$PSRCDIR/sim_1/new/VHDL.vhd">
<FileInfo> <FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
@ -161,7 +174,7 @@
<Option Name="TransportIntDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/Test_Alu_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/Test_Alu_behav.wcfg"/>
<Option Name="NLNetlistMode" Val="funcsim"/> <Option Name="xsim.simulate.runtime" Val="50us"/>
</Config> </Config>
</FileSet> </FileSet>
</FileSets> </FileSets>

Some files were not shown because too many files have changed in this diff Show more