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Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/runme.log
Lacroix Raphael 576b41da4d fixed data path and aleas
2023-05-30 13:38:05 +02:00

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*** Running vivado
with args -log Pipeline.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl
****** Vivado v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source Pipeline.tcl -notrace
Command: synth_design -top Pipeline -part xc7a35tcpg236-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 10853
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.699 ; free physical = 57815 ; free virtual = 69577
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38]
INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177]
INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187]
INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193]
INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205]
INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47]
INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217]
INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229]
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240]
INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250]
INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259]
INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329]
INFO: [Synth 8-638] synthesizing module 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40]
INFO: [Synth 8-256] done synthesizing module 'AleaControler' (10#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40]
WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50]
WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170]
INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57806 ; free virtual = 69569
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177]
WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205]
WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250]
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
Completed Processing XDC Constraints
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57555 ; free virtual = 69319
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcpg236-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396
---------------------------------------------------------------------------------
INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[1]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[2]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[3]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[4]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[5]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[6]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[7]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[8]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[9]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[10]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[11]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[12]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[13]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[14]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Regs_reg[15]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "Mem_reg[0]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[1]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[2]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[3]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[4]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[5]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[6]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[7]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[8]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[9]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[10]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[11]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[12]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[13]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[14]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[15]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[16]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[17]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[18]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[19]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[20]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[21]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[22]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[23]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[24]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[25]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[26]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[27]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[28]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[29]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[30]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[31]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[32]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[33]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[34]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[35]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[36]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[37]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[38]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[39]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[40]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[41]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[42]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[43]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[44]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[45]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[46]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[47]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[48]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[49]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[50]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[51]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[52]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[53]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[54]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[55]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[56]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[57]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[58]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[59]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[60]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[61]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[62]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[63]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[64]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[65]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[66]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[67]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[68]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[69]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[70]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[71]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[72]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[73]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[74]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[75]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[76]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[77]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[78]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[79]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[80]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[81]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[82]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[83]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[84]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[85]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[86]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[87]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[88]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[89]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[90]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[91]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[92]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[93]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[94]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[95]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261]
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57618 ; free virtual = 69383
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 9 Bit Adders := 1
2 Input 8 Bit Adders := 2
3 Input 8 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 288
+---Muxes :
257 Input 32 Bit Muxes := 1
2 Input 8 Bit Muxes := 8
2 Input 1 Bit Muxes := 279
12 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module Pipeline
Detailed RTL Component Info :
+---Muxes :
2 Input 8 Bit Muxes := 3
2 Input 1 Bit Muxes := 2
Module IP
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module InstructionMemory
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
+---Muxes :
257 Input 32 Bit Muxes := 1
Module Stage_Li_Di
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 4
Module Registers
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 16
+---Muxes :
2 Input 8 Bit Muxes := 2
2 Input 1 Bit Muxes := 16
Module Stage_Di_Ex
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 4
Module ALU
Detailed RTL Component Info :
+---Adders :
2 Input 9 Bit Adders := 1
3 Input 8 Bit Adders := 1
2 Input 8 Bit Adders := 1
+---Muxes :
2 Input 8 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
12 Input 1 Bit Muxes := 3
Module Stage_Ex_Mem
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 3
Module DataMemory
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 257
+---Muxes :
2 Input 1 Bit Muxes := 256
Module Stage_Mem_Re
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 3
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51]
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55]
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][4]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][3]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][2]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][1]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][7]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][6]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][5]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57609 ; free virtual = 69379
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+-+-----+------+
| |Cell |Count |
+-+-----+------+
+-+-----+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 0|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 2331 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 1673.281 ; gain = 142.324 ; free physical = 57567 ; free virtual = 69336
Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57570 ; free virtual = 69340
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 513.461 ; free physical = 57552 ; free virtual = 69322
WARNING: [Constraints 18-5210] No constraint will be written out.
INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57537 ; free virtual = 69306
INFO: [Common 17-206] Exiting Vivado at Tue May 30 09:13:40 2023...
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