71 lines
2.1 KiB
VHDL
71 lines
2.1 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 15.05.2023 12:56:05
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-- Design Name:
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-- Module Name: registers - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Registers is
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Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0);
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Addr_B : in STD_LOGIC_VECTOR (3 downto 0);
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Addr_W : in STD_LOGIC_VECTOR (3 downto 0);
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W : in STD_LOGIC;
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Data : in STD_LOGIC_VECTOR (7 downto 0);
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Rst : in STD_LOGIC;
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Clk : in STD_LOGIC;
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QA : out STD_LOGIC_VECTOR (7 downto 0);
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QB : out STD_LOGIC_VECTOR (7 downto 0));
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end Registers;
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architecture Behavioral of Registers is
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type Reg_array is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0);
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signal Regs : Reg_array := (others => x"00");
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begin
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process
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begin
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wait until clk'event and clk = '1';
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if Rst = '1' then -- Reset
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Regs <= (others => x"00");
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elsif W = '1' then -- Writing
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Regs(to_integer(unsigned(Addr_W))) <= Data;
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end if;
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end process;
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QA <= Regs(to_integer(unsigned(Addr_A)))
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when W = '0' or Addr_W /= Addr_A
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else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q
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QB <= Regs(to_integer(unsigned(Addr_B)))
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when W = '0' or Addr_W /= Addr_B
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else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q
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end Behavioral;
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