60 lines
1.6 KiB
VHDL
60 lines
1.6 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 15.05.2023 13:37:41
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-- Design Name:
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-- Module Name: DataMemory - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity DataMemory is
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Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
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Data_in : in STD_LOGIC_VECTOR (7 downto 0);
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Rw : in STD_LOGIC;
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Rst : in STD_LOGIC;
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Clk : in STD_LOGIC;
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Data_out : out STD_LOGIC_VECTOR (7 downto 0));
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end DataMemory;
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architecture Behavioral of DataMemory is
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type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0);
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signal Mem : Mem_array := (others => x"00");
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begin
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process
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begin
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wait until clk'event and clk = '1';
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if Rst = '1' then -- Reset
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mem <= (others => x"00");
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else if Rw = '0' then --writing
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Mem(to_integer(unsigned(Addr))) <= Data_in;
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end if;
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end if;
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end process;
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Data_out <= Mem(to_integer(unsigned(Addr))); --reading
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end Behavioral;
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