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added test files for full CPU

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Lacroix Raphael 2023-05-29 21:37:49 +02:00
parent 873502243b
commit 474ba6b265
42 changed files with 214 additions and 68 deletions
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2
VHDL/ALU/ALU.cache/wt/project.wpc
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@ -1,3 +1,3 @@
version:1 version:1
6d6f64655f636f756e7465727c4755494d6f6465:16 6d6f64655f636f756e7465727c4755494d6f6465:17
eof: eof:

2
VHDL/ALU/ALU.runs/synth_1/gen_run.xml
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1684097307"> <GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1684097307">
<File Type="RDS-DCP" Name="ALU.dcp"/>
<File Type="PA-TCL" Name="ALU.tcl"/> <File Type="PA-TCL" Name="ALU.tcl"/>
<File Type="RDS-DCP" Name="ALU.dcp"/>
<File Type="REPORTS-TCL" Name="ALU_reports.tcl"/> <File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>
<File Type="RDS-RDS" Name="ALU.vds"/> <File Type="RDS-RDS" Name="ALU.vds"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
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11
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj
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@ -1,7 +1,16 @@
# compile vhdl design source files # compile vhdl design source files
vhdl xil_defaultlib \ vhdl xil_defaultlib \
"../../../../ALU.srcs/sources_1/new/ALU.vhd" \ "../../../../ALU.srcs/sources_1/new/ALU.vhd" \
"../../../../ALU.srcs/sim_1/new/VHDL.vhd" \ "../../../../ALU.srcs/sources_1/new/IP.vhd" \
"../../../../ALU.srcs/sources_1/new/InstructionMemory.vhd" \
"../../../../ALU.srcs/sources_1/new/Memory.vhd" \
"../../../../ALU.srcs/sources_1/new/Pipeline.vhd" \
"../../../../ALU.srcs/sources_1/new/Registers.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Li_Di.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" \
"../../../../ALU.srcs/sim_1/new/test_total.vhd" \
# Do not sort compile order # Do not sort compile order
nosort nosort

30
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
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@ -169,3 +169,33 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/
INFO: [VRFC 10-307] analyzing entity ALU INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity IP
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity InstructionMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity DataMemory
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Registers
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Stage_Di_Ex
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Stage_Ex_Mem
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Stage_Li_Di
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Stage_Mem_Re
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
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@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator # Simulator : Xilinx Vivado Simulator
# Description : Script for compiling the simulation design source files # Description : Script for compiling the simulation design source files
# #
# Generated by Vivado on Mon May 29 20:22:53 CEST 2023 # Generated by Vivado on Mon May 29 21:34:18 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# #
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

10
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log
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@ -3,6 +3,7 @@ Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log
Using 8 slave threads. Using 8 slave threads.
Starting static elaboration Starting static elaboration
WARNING: [VRFC 10-122] controlunit remains a black-box since it has no binding entity [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:325]
Completed static elaboration Completed static elaboration
Starting simulation data flow analysis Starting simulation data flow analysis
Completed simulation data flow analysis Completed simulation data flow analysis
@ -13,6 +14,15 @@ Compiling package ieee.std_logic_1164
Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned Compiling package ieee.std_logic_unsigned
Compiling package ieee.numeric_std Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.IP [ip_default]
Compiling architecture behavioral of entity xil_defaultlib.InstructionMemory [instructionmemory_default]
Compiling architecture behavioral of entity xil_defaultlib.Stage_Li_Di [stage_li_di_default]
Compiling architecture behavioral of entity xil_defaultlib.Registers [registers_default]
Compiling architecture behavioral of entity xil_defaultlib.Stage_Di_Ex [stage_di_ex_default]
Compiling architecture behavioral of entity xil_defaultlib.ALU [alu_default] Compiling architecture behavioral of entity xil_defaultlib.ALU [alu_default]
Compiling architecture behavioral of entity xil_defaultlib.Stage_Ex_Mem [stage_ex_mem_default]
Compiling architecture behavioral of entity xil_defaultlib.DataMemory [datamemory_default]
Compiling architecture behavioral of entity xil_defaultlib.Stage_Mem_Re [stage_mem_re_default]
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [pipeline_default]
Compiling architecture behavioral of entity xil_defaultlib.test_alu Compiling architecture behavioral of entity xil_defaultlib.test_alu
Built simulation snapshot Test_Alu_behav Built simulation snapshot Test_Alu_behav

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
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@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator # Simulator : Xilinx Vivado Simulator
# Description : Script for elaborating the compiled design # Description : Script for elaborating the compiled design
# #
# Generated by Vivado on Mon May 29 20:22:55 CEST 2023 # Generated by Vivado on Mon May 29 21:34:19 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# #
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log
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@ -1,2 +0,0 @@
Vivado Simulator 2018.2
Time resolution is 1 ps

4
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
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@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator # Simulator : Xilinx Vivado Simulator
# Description : Script for simulating the design by launching the simulator # Description : Script for simulating the design by launching the simulator
# #
# Generated by Vivado on Mon May 29 20:22:56 CEST 2023 # Generated by Vivado on Mon May 29 21:34:22 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# #
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
@ -23,4 +23,4 @@ then
exit $RETVAL exit $RETVAL
fi fi
} }
ExecStep xsim Test_Alu_behav -key {Behavioral:sim_1:Functional:Test_Alu} -tclbatch Test_Alu.tcl -view /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log ExecStep xsim Test_Alu_behav -key {Behavioral:sim_1:Functional:Test_Alu} -tclbatch Test_Alu.tcl -view /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb
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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o
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34
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c
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@ -43,20 +43,38 @@
#define alloca _alloca #define alloca _alloca
#endif #endif
typedef void (*funcp)(char *, char *); typedef void (*funcp)(char *, char *);
extern void execute_53(char*, char *); extern void execute_87(char*, char *);
extern void execute_79(char*, char *);
extern void execute_80(char*, char *);
extern void execute_81(char*, char *);
extern void execute_82(char*, char *);
extern void execute_83(char*, char *);
extern void execute_84(char*, char *);
extern void execute_85(char*, char *);
extern void execute_86(char*, char *);
extern void execute_54(char*, char *); extern void execute_54(char*, char *);
extern void execute_55(char*, char *); extern void execute_55(char*, char *);
extern void execute_51(char*, char *); extern void execute_61(char*, char *);
extern void execute_52(char*, char *); extern void execute_63(char*, char *);
extern void execute_65(char*, char *);
extern void execute_66(char*, char *);
extern void execute_67(char*, char *);
extern void execute_69(char*, char *);
extern void execute_71(char*, char *);
extern void execute_72(char*, char *);
extern void execute_74(char*, char *);
extern void execute_76(char*, char *);
extern void execute_78(char*, char *);
extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[6] = {(funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_51, (funcp)execute_52, (funcp)vhdl_transfunc_eventcallback}; funcp funcTab[24] = {(funcp)execute_87, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_54, (funcp)execute_55, (funcp)execute_61, (funcp)execute_63, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)execute_69, (funcp)execute_71, (funcp)execute_72, (funcp)execute_74, (funcp)execute_76, (funcp)execute_78, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 6; const int NumRelocateId= 24;
void relocate(char *dp) void relocate(char *dp)
{ {
iki_relocate(dp, "xsim.dir/Test_Alu_behav/xsim.reloc", (void **)funcTab, 6); iki_relocate(dp, "xsim.dir/Test_Alu_behav/xsim.reloc", (void **)funcTab, 24);
iki_vhdl_file_variable_register(dp + 3800); iki_vhdl_file_variable_register(dp + 23824);
iki_vhdl_file_variable_register(dp + 3856); iki_vhdl_file_variable_register(dp + 23880);
/*Populate the transaction function pointer field in the whole net structure */ /*Populate the transaction function pointer field in the whole net structure */

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o
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2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info
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@ -1,5 +1,5 @@
1685381189 1685381189
1685382347 1685382347
69 72
1 1
aef36ef3a0d94dac9e6058b656907afd aef36ef3a0d94dac9e6058b656907afd

32
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl
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@ -1,6 +1,6 @@
webtalk_init -webtalk_dir /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/ webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/
webtalk_register_client -client project webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Mon May 29 20:28:58 2023" -context "software_version_and_target_device" webtalk_add_data -client project -key date_generated -value "Mon May 29 21:34:21 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
@ -12,9 +12,9 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "48ade6b1-45bb-42c1-b620-33b3e004d501" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "68" -context "software_version_and_target_device" webtalk_add_data -client project -key project_iteration -value "71" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment"
@ -22,11 +22,21 @@ webtalk_add_data -client project -key cpu_speed -value "800.000 MHz" -context "u
webtalk_add_data -client project -key total_processors -value "2" -context "user_environment" webtalk_add_data -client project -key total_processors -value "2" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment" webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment"
webtalk_register_client -client xsim webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key File_Counter -value "19" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Memory -value "122620_KB" -context "xsim\\usage" webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_transmit -clientid 1496851547 -regid "" -xml /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>" webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "60 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "4 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "22" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "17" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "1.43_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "205220_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2966348998 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate webtalk_terminate

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@ -1,6 +1,6 @@
{ {
crc : 5165304247125619484 , crc : 3586580812418567682 ,
ccp_crc : 0 , ccp_crc : 0 ,
cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu" , cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu" ,
buildDate : "Jun 14 2018" , buildDate : "Jun 14 2018" ,

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@ -1,7 +1,4 @@
Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 59047 Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 56337
Design successfully loaded Design successfully loaded
Design Loading Memory Usage: 32684 KB (Peak: 32736 KB) Design Loading Memory Usage: 32728 KB (Peak: 32780 KB)
Design Loading CPU Usage: 20 ms Design Loading CPU Usage: 30 ms
Simulation completed
Simulation Memory Usage: 122620 KB (Peak: 179956 KB)
Simulation CPU Usage: 30 ms

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@ -2,5 +2,14 @@
2018.2 2018.2
Jun 14 2018 Jun 14 2018
20:07:38 20:07:38
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1685384562,vhdl,,,,test_alu,,,,,,,, /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685388243,vhdl,,,,test_alu,,,,,,,,
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685384160,vhdl,,,,alu,,,,,,,, /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685386043,vhdl,,,,alu,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685386043,vhdl,,,,ip,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685386043,vhdl,,,,instructionmemory,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685386043,vhdl,,,,datamemory,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685388854,vhdl,,,,pipeline,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685386043,vhdl,,,,registers,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd,1685386043,vhdl,,,,stage_li_di,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd,1685386043,vhdl,,,,stage_mem_re,,,,,,,,

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@ -1,2 +1,2 @@
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu INFO: [VRFC 10-307] analyzing entity Pipeline

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VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd Normal file
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@ -0,0 +1,61 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.05.2023 17:40:52
-- Design Name:
-- Module Name: Test_Alu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Alu is
-- Port ( );
end Test_Alu;
architecture Behavioral of Test_Alu is
component Pipeline
Port ( Clk : in STD_LOGIC);
end component;
constant clock_period : time := 10 ns;
signal clock : Std_logic;
begin
-- instantiate
Pl : Pipeline PORT MAP (
Clk => clock
);
Clock_process : process
begin
clock <= not(clock);
wait for 100ns;
end process;
end Behavioral;

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VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
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@ -38,7 +38,7 @@ end Pipeline;
architecture Behavioral of Pipeline is architecture Behavioral of Pipeline is
component IP is component IP is
port ( CK : in STD_LOGIC; port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC; -- rst when 0 RST : in STD_LOGIC; -- rst when 0
LOAD : in STD_LOGIC; LOAD : in STD_LOGIC;
EN : in STD_LOGIC; -- enable when 1 EN : in STD_LOGIC; -- enable when 1
@ -106,7 +106,7 @@ architecture Behavioral of Pipeline is
component ALU component ALU
Port ( A : in STD_LOGIC_VECTOR (7 downto 0); Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0); B : in STD_LOGIC_VECTOR (7 downto 0);
Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0);
S : out STD_LOGIC_VECTOR (7 downto 0); S : out STD_LOGIC_VECTOR (7 downto 0);
N : out STD_LOGIC; N : out STD_LOGIC;
O : out STD_LOGIC; O : out STD_LOGIC;
@ -166,10 +166,11 @@ architecture Behavioral of Pipeline is
signal Re_W : STD_LOGIC; signal Re_W : STD_LOGIC;
-- to control jumping and where to jump -- to control jumping and where to jump
signal addr_to_jump : STD_LOGIC; signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal jump : STD_LOGIC; signal jump : STD_LOGIC;
signal nop_Cntrl : STD_LOGIC; signal nop_Cntrl : STD_LOGIC;
signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
begin begin
-- instructionPointer -- instructionPointer
@ -177,7 +178,7 @@ inst_point : IP port map (
CLK=> clk, CLK=> clk,
Dout=> IP_out, Dout=> IP_out,
Din => addr_to_jump, Din => addr_to_jump,
RST => "1", RST => '1',
EN => nop_Cntrl, EN => nop_Cntrl,
LOAD => jump); LOAD => jump);
@ -202,9 +203,9 @@ Stage1 : Stage_Li_Di PORT MAP (
-- Registers -- Registers
StageRegisters : Registers PORT MAP ( StageRegisters : Registers PORT MAP (
Addr_A => Di_B, Addr_A => Di_B(3 downto 0), -- becquse the registers are on 4 bits
Addr_B => Di_C, Addr_B => Di_C(3 downto 0),
Addr_W => Re_A, Addr_W => Re_A(3 downto 0),
W => Re_W, W => Re_W,
Data => Re_B, Data => Re_B,
Rst => Rst, Rst => Rst,
@ -296,11 +297,8 @@ Ex_FinalB <= Ex_B when
else Ex_Res_Alu; else Ex_Res_Alu;
-- LC pre ALU -- LC pre ALU
Ex_Ctrl_ALu <= "000" when Ex_Op = x"01" --ADD Ex_Ctrl_ALu <= x"00" when Ex_Op = x"05" or Ex_Op = x"06" or Ex_Op = x"07" or Ex_Op = x"08" --(not using ALU)
else "001" when Ex_Op = x"03" -- SUB else Ex_Op;
else "010" when Ex_Op = x"02" -- MUL
else "100" when Ex_Op = x"04" -- DIV
else "111"; --ERROR
-- Mux post data memory -- Mux post data memory
Mem_FinalB <= Mem_B when Mem_FinalB <= Mem_B when
@ -325,13 +323,13 @@ Re_W <= '0' when Re_Op = x"08" --STORE
else '1'; else '1';
CU : ControlUnit port map ( CU : ControlUnit port map (
Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op; Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op,
A_EX =< Di_A, A_Mem => Ex_A; A_EX => Di_A, A_Mem => Ex_A,
B_DI => Li(15 downto 8); B_DI => Li(15 downto 8),
C_DI => Li(7 downto 0); C_DI => Li(7 downto 0),
CNTRL => nop_Cntrl); CNTRL => nop_Cntrl);
end Behavioral;
-- in case of alea : replace li(31 downto 24) by NOP -- in case of alea : replace li(31 downto 24) by NOP
OP_LI_DI<= X"ff" when nop_Cntrl='1' else li(31 downto 24); OP_LI_DI <= X"ff" when nop_Cntrl='1' else Li(31 downto 24);
end Behavioral;

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VHDL/ALU/ALU.xpr
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@ -3,7 +3,7 @@
<!-- --> <!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --> <!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="38" Path="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr"> <Project Version="7" Minor="38" Path="/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr">
<DefaultLaunch Dir="$PRUNDIR"/> <DefaultLaunch Dir="$PRUNDIR"/>
<Configuration> <Configuration>
<Option Name="Id" Val="aef36ef3a0d94dac9e6058b656907afd"/> <Option Name="Id" Val="aef36ef3a0d94dac9e6058b656907afd"/>
@ -33,7 +33,7 @@
<Option Name="DSAVendor" Val="xilinx"/> <Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="basys3"/> <Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="60"/> <Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="62"/> <Option Name="WTXSimLaunchSim" Val="67"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
@ -67,6 +67,12 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/IP.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/InstructionMemory.vhd"> <File Path="$PSRCDIR/sources_1/new/InstructionMemory.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@ -115,13 +121,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/IP.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Pipeline"/> <Option Name="TopModule" Val="Pipeline"/>
@ -136,8 +135,15 @@
</FileSet> </FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1"> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/test_total.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/VHDL.vhd"> <File Path="$PSRCDIR/sim_1/new/VHDL.vhd">
<FileInfo> <FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>