61 lines
1.2 KiB
VHDL
61 lines
1.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12.05.2023 17:40:52
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-- Design Name:
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-- Module Name: Test_Alu - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Test_Alu is
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-- Port ( );
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end Test_Alu;
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architecture Behavioral of Test_Alu is
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component Pipeline
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Port ( Clk : in STD_LOGIC);
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end component;
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constant clock_period : time := 10 ns;
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signal clock : Std_logic;
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begin
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-- instantiate
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Pl : Pipeline PORT MAP (
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Clk => clock
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);
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Clock_process : process
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begin
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clock <= not(clock);
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wait for 100ns;
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end process;
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end Behavioral;
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