From 474ba6b265444a5596429b16492446f93c2095ca Mon Sep 17 00:00:00 2001 From: Lacroix Raphael Date: Mon, 29 May 2023 21:37:49 +0200 Subject: [PATCH] added test files for full CPU --- VHDL/ALU/ALU.cache/wt/project.wpc | 2 +- VHDL/ALU/ALU.runs/synth_1/gen_run.xml | 2 +- .../sim_1/behav/xsim/Test_Alu_behav.wdb | Bin 7598 -> 18187 bytes .../sim_1/behav/xsim/Test_Alu_vhdl.prj | 11 +++- VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log | 30 +++++++++ VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh | 2 +- .../ALU.sim/sim_1/behav/xsim/elaborate.log | 10 +++ .../ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh | 2 +- .../ALU/ALU.sim/sim_1/behav/xsim/simulate.log | 2 - VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh | 4 +- VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb | Bin 2065 -> 3787 bytes .../Test_Alu_behav/obj/xsim_0.lnx64.o | Bin 36800 -> 51400 bytes .../xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c | 34 +++++++--- .../Test_Alu_behav/obj/xsim_1.lnx64.o | Bin 4296 -> 5504 bytes .../webtalk/.xsim_webtallk.info | 2 +- .../Test_Alu_behav/webtalk/xsim_webtalk.tcl | 32 +++++---- .../xsim/xsim.dir/Test_Alu_behav/xsim.dbg | Bin 3860 -> 16884 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.mem | Bin 3015 -> 4686 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.reloc | Bin 400 -> 1978 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.rlx | 2 +- .../xsim/xsim.dir/Test_Alu_behav/xsim.rtti | Bin 318 -> 711 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.type | Bin 7168 -> 7424 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.xdbg | Bin 2456 -> 79456 bytes .../behav/xsim/xsim.dir/Test_Alu_behav/xsimk | Bin 48456 -> 62272 bytes .../xsim.dir/Test_Alu_behav/xsimkernel.log | 9 +-- .../xsim/xsim.dir/xil_defaultlib/alu.vdb | Bin 8874 -> 8794 bytes .../xsim.dir/xil_defaultlib/datamemory.vdb | Bin 0 -> 4136 bytes .../xil_defaultlib/instructionmemory.vdb | Bin 0 -> 3186 bytes .../behav/xsim/xsim.dir/xil_defaultlib/ip.vdb | Bin 0 -> 3608 bytes .../xsim/xsim.dir/xil_defaultlib/pipeline.vdb | Bin 0 -> 30040 bytes .../xsim.dir/xil_defaultlib/registers.vdb | Bin 0 -> 5762 bytes .../xsim.dir/xil_defaultlib/stage_di_ex.vdb | Bin 0 -> 3387 bytes .../xsim.dir/xil_defaultlib/stage_ex_mem.vdb | Bin 0 -> 2905 bytes .../xsim.dir/xil_defaultlib/stage_li_di.vdb | Bin 0 -> 3387 bytes .../xsim.dir/xil_defaultlib/stage_mem_re.vdb | Bin 0 -> 2905 bytes .../xsim/xsim.dir/xil_defaultlib/test_alu.vdb | Bin 7771 -> 1994 bytes .../xil_defaultlib/xil_defaultlib.rlx | 13 +++- VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log | 4 +- VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb | Bin 355 -> 361 bytes VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd | 61 ++++++++++++++++++ VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd | 36 +++++------ VHDL/ALU/ALU.xpr | 24 ++++--- 42 files changed, 214 insertions(+), 68 deletions(-) create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory.vdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ip.vdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_di_ex.vdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_ex_mem.vdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_li_di.vdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_mem_re.vdb create mode 100644 VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd diff --git a/VHDL/ALU/ALU.cache/wt/project.wpc b/VHDL/ALU/ALU.cache/wt/project.wpc index f16dd14..aaeed60 100644 --- a/VHDL/ALU/ALU.cache/wt/project.wpc +++ b/VHDL/ALU/ALU.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:16 +6d6f64655f636f756e7465727c4755494d6f6465:17 eof: diff --git a/VHDL/ALU/ALU.runs/synth_1/gen_run.xml b/VHDL/ALU/ALU.runs/synth_1/gen_run.xml index 4be73d3..1dceaba 100644 --- a/VHDL/ALU/ALU.runs/synth_1/gen_run.xml +++ b/VHDL/ALU/ALU.runs/synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb index ba34593131186ec1c85d57400e9a5ca188e32fe2..90d8f1eb688b3d4fcc1f6e39f693210eaa9a1739 100644 GIT binary patch literal 18187 zcmeI4e~esJ6~}KWKg#a~1PX`@KT6Aw?#ynt%K}1oW_Q{hy6tXvx9w8IVY)l*4xODD z=SSHlD2-96F=~y8Atac_2q`EEe~67nQ$myPRhKzt}Avhom4KkWG+{kU_`*Wa(nZ&a05KVQDP4 zChN|?39ocZ1BWox8Ue^k^6@=YS z|M;D5=cX8+9qZa(I?Js_P6xjJ!;L%vQ>S3$Ytv)vN794A)uYHAK79BAURfH_=KCnW zA=@`LG!lUG+#b=P%VZwd-n|10k3bU0vxD5)vFxgB*bYTIwS$#7VFzo9)A>TZUf3~f znRgj2qV0?%WGEIk$U7D5+lO4nPj2L%9leC^eCF&^A4YalHn4UL5l&0Fgnf|tC4}R>3*s{ian3%-JS!Tv_bkIzf!6@n2h7XR zbm4;#-_ECT&WNC$S0P+$9)>7GeK}+VLgqCH7qcHgl;N0p4{?lS-hgo3dIsV%37l_+ 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zG{SU3DFN^A83eqa%L%s;DhPH0#@lKilzTSMx{Pl7jba zTQcVR=KTkbXUCeB+w1lpw-zX&FLRcxiSBv$zS*u5_XVOyx|;W27L!IsuN(Z~i#v{} z?@t^sD6NJ4$v+*JFS~fkmej=*?_)15+*O!jJ3Qxtilc>(?!Nk&;+l@VNtvC4U%h5` zW=qSe{4ZL*YfQfA(7tcSez8J(@X2jA4L^2r(etrsZ?4i#Eq-EWp0xA*-7{y~7aq!9 z-kN%CU8G=Xr?&d=y0PDNynCx?a6c2eY5Vl)_kRI z?tptHtla(6_DwyhpInmJ-gU*pUw?k}{oNm3ws}~6!9v<>c``~vr4e_o2(3Ahhkr~Oi6?O&-z1<5|cWzKl4&V8~osDlC9kz1q%Qq|< aI+vYyc?Ub+(vtM2%$|8&Lt7uae)R8!fG8;d diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj index 566e460..89210f4 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj @@ -1,7 +1,16 @@ # compile vhdl design source files vhdl xil_defaultlib \ "../../../../ALU.srcs/sources_1/new/ALU.vhd" \ -"../../../../ALU.srcs/sim_1/new/VHDL.vhd" \ +"../../../../ALU.srcs/sources_1/new/IP.vhd" \ +"../../../../ALU.srcs/sources_1/new/InstructionMemory.vhd" \ +"../../../../ALU.srcs/sources_1/new/Memory.vhd" \ +"../../../../ALU.srcs/sources_1/new/Pipeline.vhd" \ +"../../../../ALU.srcs/sources_1/new/Registers.vhd" \ +"../../../../ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" \ +"../../../../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" \ +"../../../../ALU.srcs/sources_1/new/Stage_Li_Di.vhd" \ +"../../../../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" \ +"../../../../ALU.srcs/sim_1/new/test_total.vhd" \ # Do not sort compile order nosort diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log index dd78853..dc2baa5 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log @@ -169,3 +169,33 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/ INFO: [VRFC 10-307] analyzing entity ALU INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity IP +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity DataMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Registers +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Stage_Di_Ex +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Stage_Ex_Mem +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Stage_Li_Di +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Stage_Mem_Re +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh index c6f28cd..e3f9952 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for compiling the simulation design source files # -# Generated by Vivado on Mon May 29 20:22:53 CEST 2023 +# Generated by Vivado on Mon May 29 21:34:18 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log index 42b35ed..2afd0f2 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log @@ -3,6 +3,7 @@ Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log Using 8 slave threads. Starting static elaboration +WARNING: [VRFC 10-122] controlunit remains a black-box since it has no binding entity [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:325] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis @@ -13,6 +14,15 @@ Compiling package ieee.std_logic_1164 Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_unsigned Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.IP [ip_default] +Compiling architecture behavioral of entity xil_defaultlib.InstructionMemory [instructionmemory_default] +Compiling architecture behavioral of entity xil_defaultlib.Stage_Li_Di [stage_li_di_default] +Compiling architecture behavioral of entity xil_defaultlib.Registers [registers_default] +Compiling architecture behavioral of entity xil_defaultlib.Stage_Di_Ex [stage_di_ex_default] Compiling architecture behavioral of entity xil_defaultlib.ALU [alu_default] +Compiling architecture behavioral of entity xil_defaultlib.Stage_Ex_Mem [stage_ex_mem_default] +Compiling architecture behavioral of entity xil_defaultlib.DataMemory [datamemory_default] +Compiling architecture behavioral of entity xil_defaultlib.Stage_Mem_Re [stage_mem_re_default] +Compiling architecture behavioral of entity xil_defaultlib.Pipeline [pipeline_default] Compiling architecture behavioral of entity xil_defaultlib.test_alu Built simulation snapshot Test_Alu_behav diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh index 96c200b..04e7d7a 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for elaborating the compiled design # -# Generated by Vivado on Mon May 29 20:22:55 CEST 2023 +# Generated by Vivado on Mon May 29 21:34:19 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log index 2cc3412..e69de29 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log @@ -1,2 +0,0 @@ -Vivado Simulator 2018.2 -Time resolution is 1 ps diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh index bed3f56..d012529 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for simulating the design by launching the simulator # -# Generated by Vivado on Mon May 29 20:22:56 CEST 2023 +# Generated by Vivado on Mon May 29 21:34:22 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. @@ -23,4 +23,4 @@ then exit $RETVAL fi } -ExecStep xsim Test_Alu_behav -key {Behavioral:sim_1:Functional:Test_Alu} -tclbatch Test_Alu.tcl -view /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log +ExecStep xsim Test_Alu_behav -key {Behavioral:sim_1:Functional:Test_Alu} -tclbatch Test_Alu.tcl -view /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb index 8504d15d475a598ff93e91b4c65e61e9d815752a..ad883cce76ea8a25f4a8b57f45d6bda09ecfa0f7 100644 GIT binary patch delta 683 zcmZ{hL2DC16oB0XR+wIbh-g7NV7&MS>*iDi zFW!_OBI3zIuR?GB05AF@`cs@8T@-B__;;4t{SSL5GV~5 zbdrnYX?LP3YEULX(b7y9DixieOi|7#NQ-vS30K=u9A8_h3>F8Vaf(U2MphCftyXy{ z(Z**}n2IvDx0)b+6%ffXRRGiOJ6auL#cr1xM9FTTW@ce5MLAV$sMQm&-949p0!+8> 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1685382347 -69 +72 1 aef36ef3a0d94dac9e6058b656907afd diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl index 3e4dbde..e89f7e4 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ -webtalk_init -webtalk_dir /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/ +webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Mon May 29 20:28:58 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Mon May 29 21:34:21 2023" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" @@ -12,9 +12,9 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key random_id -value "48ade6b1-45bb-42c1-b620-33b3e004d501" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "68" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "71" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment" @@ -22,11 +22,21 @@ webtalk_add_data -client project -key cpu_speed -value "800.000 MHz" -context "u webtalk_add_data -client project -key total_processors -value "2" -context "user_environment" webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment" webtalk_register_client -client xsim -webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" -webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "122620_KB" -context "xsim\\usage" -webtalk_transmit -clientid 1496851547 -regid "" -xml /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key File_Counter -value "19" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "60 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "4 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "22" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "17" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "1.43_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "205220_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2966348998 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


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-/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1685384562,vhdl,,,,test_alu,,,,,,,, -/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685384160,vhdl,,,,alu,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685388243,vhdl,,,,test_alu,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685386043,vhdl,,,,alu,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685386043,vhdl,,,,ip,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685386043,vhdl,,,,instructionmemory,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685386043,vhdl,,,,datamemory,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685388854,vhdl,,,,pipeline,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685386043,vhdl,,,,registers,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd,1685386043,vhdl,,,,stage_li_di,,,,,,,, +/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd,1685386043,vhdl,,,,stage_mem_re,,,,,,,, diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log index afa41cd..717e173 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log @@ -1,2 +1,2 @@ -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb index 57833cc129cdd43fa4a036315c4e2cbd3e772c37..f7a006d6dd0b5dedbffac1f146600b92624da808 100644 GIT binary patch delta 91 zcmaFN^pc5*>&HYU2lXaKt~~vW{M=OiqMXF!qWsJXeW%i*)WlMKlguLh;>zL@h0MIP o{E68{qWPso$*INhhWdG_<@y1c1*tiid8rdu)o{Srll2%)0ouAD0ssI2 delta 85 zcmaFK^q7f>>(fLg2hCcpO#O`f+*JL clock +); + +Clock_process : process +begin + clock <= not(clock); + wait for 100ns; +end process; + + +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd index 9c1a093..bafb897 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd @@ -38,7 +38,7 @@ end Pipeline; architecture Behavioral of Pipeline is component IP is - port ( CK : in STD_LOGIC; + port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; -- rst when 0 LOAD : in STD_LOGIC; EN : in STD_LOGIC; -- enable when 1 @@ -106,7 +106,7 @@ architecture Behavioral of Pipeline is component ALU Port ( A : in STD_LOGIC_VECTOR (7 downto 0); B : in STD_LOGIC_VECTOR (7 downto 0); - Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div + Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0); S : out STD_LOGIC_VECTOR (7 downto 0); N : out STD_LOGIC; O : out STD_LOGIC; @@ -166,10 +166,11 @@ architecture Behavioral of Pipeline is signal Re_W : STD_LOGIC; -- to control jumping and where to jump - signal addr_to_jump : STD_LOGIC; + signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal jump : STD_LOGIC; signal nop_Cntrl : STD_LOGIC; + signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); begin -- instructionPointer @@ -177,7 +178,7 @@ inst_point : IP port map ( CLK=> clk, Dout=> IP_out, Din => addr_to_jump, - RST => "1", + RST => '1', EN => nop_Cntrl, LOAD => jump); @@ -202,9 +203,9 @@ Stage1 : Stage_Li_Di PORT MAP ( -- Registers StageRegisters : Registers PORT MAP ( - Addr_A => Di_B, - Addr_B => Di_C, - Addr_W => Re_A, + Addr_A => Di_B(3 downto 0), -- becquse the registers are on 4 bits + Addr_B => Di_C(3 downto 0), + Addr_W => Re_A(3 downto 0), W => Re_W, Data => Re_B, Rst => Rst, @@ -296,11 +297,8 @@ Ex_FinalB <= Ex_B when else Ex_Res_Alu; -- LC pre ALU -Ex_Ctrl_ALu <= "000" when Ex_Op = x"01" --ADD - else "001" when Ex_Op = x"03" -- SUB - else "010" when Ex_Op = x"02" -- MUL - else "100" when Ex_Op = x"04" -- DIV - else "111"; --ERROR +Ex_Ctrl_ALu <= x"00" when Ex_Op = x"05" or Ex_Op = x"06" or Ex_Op = x"07" or Ex_Op = x"08" --(not using ALU) + else Ex_Op; -- Mux post data memory Mem_FinalB <= Mem_B when @@ -325,13 +323,13 @@ Re_W <= '0' when Re_Op = x"08" --STORE else '1'; CU : ControlUnit port map ( - Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op; - A_EX =< Di_A, A_Mem => Ex_A; - B_DI => Li(15 downto 8); - C_DI => Li(7 downto 0); + Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op, + A_EX => Di_A, A_Mem => Ex_A, + B_DI => Li(15 downto 8), + C_DI => Li(7 downto 0), CNTRL => nop_Cntrl); -end Behavioral; - -- in case of alea : replace li(31 downto 24) by NOP - OP_LI_DI<= X"ff" when nop_Cntrl='1' else li(31 downto 24); \ No newline at end of file + OP_LI_DI <= X"ff" when nop_Cntrl='1' else Li(31 downto 24); + + end Behavioral; \ No newline at end of file diff --git a/VHDL/ALU/ALU.xpr b/VHDL/ALU/ALU.xpr index 41a3ef6..90e3ff5 100644 --- a/VHDL/ALU/ALU.xpr +++ b/VHDL/ALU/ALU.xpr @@ -3,7 +3,7 @@ - + + + + + + + @@ -115,13 +121,6 @@ - - - - - - -