Browse Source

Processeur OK 22 Instructions, reste a sécuriser les accès mémoire avec des modulo

Paul Faure 4 months ago
parent
commit
d1bbb37208

+ 33
- 33
Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc View File

@@ -4,9 +4,9 @@
4 4
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
5 5
 
6 6
 ## Clock signal
7
-#set_property PACKAGE_PIN W5 [get_ports clk]
8
-	#set_property IOSTANDARD LVCMOS33 [get_ports clk]
9
-	#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
7
+set_property PACKAGE_PIN W5 [get_ports CLK]
8
+set_property IOSTANDARD LVCMOS33 [get_ports CLK]
9
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
10 10
 
11 11
 ## Switches
12 12
 set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
@@ -25,22 +25,22 @@ set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
25 25
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
26 26
 set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
27 27
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
28
-set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
29
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
30
-set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
31
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
32
-set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
33
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
34
-set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
35
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
36
-set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
37
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
38
-set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
39
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
40
-set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
41
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
42
-set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
43
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
28
+#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
29
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
30
+#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
31
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
32
+#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
33
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
34
+#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
35
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
36
+#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
37
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
38
+#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
39
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
40
+#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
41
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
42
+#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
43
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
44 44
 
45 45
 
46 46
 ## LEDs
@@ -68,14 +68,14 @@ set_property PACKAGE_PIN V14 [get_ports {led[7]}]
68 68
 	#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
69 69
 #set_property PACKAGE_PIN U3 [get_ports {led[11]}]
70 70
 	#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
71
-set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
72
-	set_property IOSTANDARD LVCMOS33 [get_ports {flag[0]}]
73
-set_property PACKAGE_PIN N3 [get_ports {flag[1]}]
74
-	set_property IOSTANDARD LVCMOS33 [get_ports {flag[1]}]
75
-set_property PACKAGE_PIN P1 [get_ports {flag[2]}]
76
-	set_property IOSTANDARD LVCMOS33 [get_ports {flag[2]}]
77
-set_property PACKAGE_PIN L1 [get_ports {flag[3]}]
78
-	set_property IOSTANDARD LVCMOS33 [get_ports {flag[3]}]
71
+#set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
72
+#	set_property IOSTANDARD LVCMOS33 [get_ports {flag[0]}]
73
+#set_property PACKAGE_PIN N3 [get_ports {flag[1]}]
74
+#	set_property IOSTANDARD LVCMOS33 [get_ports {flag[1]}]
75
+#set_property PACKAGE_PIN P1 [get_ports {flag[2]}]
76
+#	set_property IOSTANDARD LVCMOS33 [get_ports {flag[2]}]
77
+#set_property PACKAGE_PIN L1 [get_ports {flag[3]}]
78
+#	set_property IOSTANDARD LVCMOS33 [get_ports {flag[3]}]
79 79
 
80 80
 
81 81
 ##7 segment display
@@ -110,12 +110,12 @@ set_property PACKAGE_PIN L1 [get_ports {flag[3]}]
110 110
 ##Buttons
111 111
 set_property PACKAGE_PIN U18 [get_ports btnC]
112 112
 	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
113
-#set_property PACKAGE_PIN T18 [get_ports btnU]
114
-	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
115
-set_property PACKAGE_PIN W19 [get_ports btnL]
116
-	set_property IOSTANDARD LVCMOS33 [get_ports btnL]
117
-set_property PACKAGE_PIN T17 [get_ports btnR]
118
-	set_property IOSTANDARD LVCMOS33 [get_ports btnR]
113
+##set_property PACKAGE_PIN T18 [get_ports btnU]
114
+#	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
115
+#set_property PACKAGE_PIN W19 [get_ports btnL]
116
+#	set_property IOSTANDARD LVCMOS33 [get_ports btnL]
117
+#set_property PACKAGE_PIN T17 [get_ports btnR]
118
+#	set_property IOSTANDARD LVCMOS33 [get_ports btnR]
119 119
 #set_property PACKAGE_PIN U17 [get_ports btnD]
120 120
 	#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
121 121
 

+ 12
- 8
Processeur.srcs/sim_1/new/Test_Pipeline.vhd View File

@@ -39,30 +39,34 @@ architecture Behavioral of Test_Pipeline is
39 39
     
40 40
     component Pipeline is
41 41
     Generic (Nb_bits : Natural := 8;
42
-             Instruction_En_Memoire_Size : Natural := 28;
42
+             Instruction_En_Memoire_Size : Natural := 29;
43 43
              Addr_Memoire_Instruction_Size : Natural := 3;
44 44
              Memoire_Instruction_Size : Natural := 8;
45
-             Instruction_Bus_Size : Natural := 4;
46
-             Nb_Instructions : Natural := 16;
45
+             Instruction_Bus_Size : Natural := 5;
46
+             Nb_Instructions : Natural := 32;
47 47
              Nb_Registres : Natural := 16;
48
-             Memoire_Size : Natural := 8;
48
+             Memoire_Size : Natural := 32;
49 49
              Memoire_Adresses_Retour_Size : Natural := 16;
50 50
              Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
51 51
     Port (CLK : STD_LOGIC;
52
-          RST : STD_LOGIC);
52
+          RST : STD_LOGIC;
53
+          STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
54
+          STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
53 55
     end component;
54 56
     
55 57
     signal my_CLK : STD_LOGIC := '0';
56 58
     signal my_RST : STD_LOGIC := '1';
59
+    signal my_STD_IN : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
60
+    signal my_STD_OUT : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
57 61
     
58 62
     constant CLK_period : time := 10 ns;
59 63
     
60 64
 begin
61 65
     instance : Pipeline
62
-    generic map (Addr_Memoire_Instruction_Size => 4,
63
-                 Memoire_Instruction_Size => 16)
64 66
     port map (CLK => my_CLK,
65
-              RST => my_RST);
67
+              RST => my_RST,
68
+              STD_IN => my_STD_IN,
69
+              STD_OUT => my_STD_OUT);
66 70
               
67 71
     CLK_process :process
68 72
     begin

+ 4
- 1
Processeur.srcs/sources_1/new/BancRegistres.vhd View File

@@ -39,13 +39,15 @@ entity BancRegistres is
39 39
              Nb_regs : Natural);
40 40
     Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
41 41
            AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
42
+           AddrC : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
42 43
            AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
43 44
            W : in STD_LOGIC;
44 45
            DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
45 46
            RST : in STD_LOGIC;
46 47
            CLK : in STD_LOGIC;
47 48
            QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
48
-           QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
49
+           QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
50
+           QC : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
49 51
 end BancRegistres;
50 52
 
51 53
 -- ASK MEILLEURE IDEE UN TABLEAU
@@ -65,4 +67,5 @@ begin
65 67
     end process;
66 68
     QA <= REGISTRES (((to_integer(unsigned(AddrA)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrA)));
67 69
     QB <= REGISTRES (((to_integer(unsigned(AddrB)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrB)));
70
+    QC <= REGISTRES (((to_integer(unsigned(AddrC)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrC)));    
68 71
 end Behavioral;

+ 57
- 0
Processeur.srcs/sources_1/new/Clock_Divider.vhd View File

@@ -0,0 +1,57 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 08.05.2021 21:00:25
6
+-- Design Name: 
7
+-- Module Name: Clock_Divider - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Clock_Divider is
35
+    Port ( CLK_IN : in STD_LOGIC;
36
+           CLK_OUT : out STD_LOGIC);
37
+end Clock_Divider;
38
+
39
+architecture Behavioral of Clock_Divider is
40
+    signal N : Integer := 0;
41
+    signal CLK : STD_LOGIC := '1';
42
+begin
43
+    process
44
+    begin
45
+        wait until CLK_IN'event and CLK_IN = '1';
46
+        N <= N + 1;
47
+        if (N = 1000) then
48
+            N <= 0;
49
+            if (CLK = '1') then
50
+                CLK <= '0';
51
+            else 
52
+                CLK <= '1';
53
+            end if;
54
+        end if;
55
+    end process;
56
+    CLK_OUT <= CLK;
57
+end Behavioral;

+ 85
- 22
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd View File

@@ -41,13 +41,15 @@ entity Etage1_LectureInstruction is
41 41
              Nb_registres : Natural;
42 42
              Mem_adresse_retour_size : Natural;
43 43
              Adresse_size_mem_adresse_retour : Natural;
44
-             Instructions_critiques_lecture : STD_LOGIC_VECTOR;
45
-             Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
44
+             Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
45
+             Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
46
+             Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
46 47
              Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
47 48
              Code_Instruction_JMP : STD_LOGIC_VECTOR;
48 49
              Code_Instruction_JMZ : STD_LOGIC_VECTOR;
49 50
              Code_Instruction_CALL : STD_LOGIC_VECTOR;
50
-             Code_Instruction_RET : STD_LOGIC_VECTOR);
51
+             Code_Instruction_RET : STD_LOGIC_VECTOR;
52
+             Code_Instruction_STOP : STD_LOGIC_VECTOR);
51 53
     Port ( CLK : in STD_LOGIC;
52 54
            RST : in STD_LOGIC;
53 55
            Z : in STD_LOGIC;
@@ -85,11 +87,12 @@ architecture Behavioral of Etage1_LectureInstruction is
85 87
     signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
86 88
     
87 89
     subtype Registre is integer range -1 to Nb_registres - 1;
88
-    type Tab_registres is array (1 to 4) of Registre;
90
+    type Tab_registres is array (1 to 3) of Registre;
89 91
     signal Tableau : Tab_registres := (others => - 1);
90 92
     
91 93
     signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
92
-    signal Nul : STD_LOGIC := '0';
94
+    signal E : STD_LOGIC;
95
+    signal F : STD_LOGIC;
93 96
     signal R_Aux : STD_LOGIC := '0';
94 97
     signal W_Aux : STD_LOGIC := '0';
95 98
 
@@ -99,6 +102,7 @@ architecture Behavioral of Etage1_LectureInstruction is
99 102
     signal bulles : boolean := false;
100 103
     
101 104
     signal compteur : integer := 0;
105
+    signal locked : boolean := false;
102 106
     
103 107
 begin
104 108
     instance : MemoireInstructions
@@ -119,8 +123,8 @@ begin
119 123
                RST => RST,
120 124
                CLK => CLK,
121 125
                D_OUT => Adresse_Retour,
122
-               E => Nul,
123
-               F => Nul
126
+               E => E,
127
+               F => F
124 128
     );
125 129
 
126 130
               
@@ -130,34 +134,35 @@ begin
130 134
         if (RST = '0') then
131 135
             Tableau <= (others => -1);
132 136
             Pointeur_Instruction <= (others => '0');
137
+            compteur <= 0;
138
+            locked <= false;
133 139
             C <= Argument_nul;
134 140
             B <= Argument_nul;
135 141
             A <= Argument_nul;
136 142
             Instruction <= Instruction_nulle;
137 143
         else
138
-            Tableau(4) <= Tableau(3);
139 144
             Tableau(3) <= Tableau(2);
140 145
             Tableau(2) <= Tableau(1);
141 146
             Tableau(1) <= -1;
142 147
             if (not bulles) then
143 148
                 if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
144
-                    C <= Argument_nul;
145
-                    B <= Argument_nul;
146
-                    A <= Argument_nul;
147
-                    Instruction <= Instruction_nulle;
149
+                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
150
+                    B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
151
+                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
152
+                    Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
148 153
                     Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
149 154
                 elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
150
-                    C <= Argument_nul;
151
-                    B <= Argument_nul;
152
-                    A <= Argument_nul;
153
-                    Instruction <= Instruction_nulle;
155
+                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
156
+                    B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
157
+                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
158
+                    Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
154 159
                     Pointeur_Instruction <= Adresse_Retour;
155 160
                 elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
156 161
                     compteur <= compteur + 1;
157
-                    C <= Argument_nul;
158
-                    B <= Argument_nul;
159
-                    A <= Argument_nul;
160
-                    Instruction <= Instruction_nulle;
162
+                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
163
+                    B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
164
+                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
165
+                    Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
161 166
                     if (compteur = 2) then
162 167
                         if (Z = '1') then
163 168
                             Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
@@ -166,6 +171,21 @@ begin
166 171
                         end if;
167 172
                         compteur <= 0;
168 173
                     end if;
174
+                elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_STOP) then
175
+                    if (not locked) then
176
+                        if (Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits) = Argument_nul) then
177
+                            locked <= true;
178
+                        end if;
179
+                        compteur <= compteur + 1;
180
+                        if (compteur + 1 = to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)))) then
181
+                            Pointeur_Instruction <= Pointeur_Instruction + 1;
182
+                            compteur <= 0;
183
+                        end if;
184
+                    end if;
185
+                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
186
+                    B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
187
+                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
188
+                    Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
169 189
                 else
170 190
                     C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
171 191
                     B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
@@ -186,8 +206,51 @@ begin
186 206
     end process;
187 207
     
188 208
     
189
-    -- Condition degueu -> Instruction qui lit dans B et B dans tableau ou instruction qui lit dans C et C dans tableau 
190
-    bulles <= ((Instructions_critiques_lecture(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') and ((to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(1)) or (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(2)) or (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(3)))) or ((Instructions_critiques_lecture_double(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') and ((to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(1)) or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(2)) or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))));
209
+    -- Condition degueu -> Instruction critique en lecture simple qui lit dans B et B dans tableau ou instruction critique en lecture double qui lit dans C et C dans tableau 
210
+    bulles <= 
211
+    (
212
+        (
213
+            Instructions_critiques_lecture_A(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
214
+        )
215
+        and 
216
+        (
217
+            (to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(1))
218
+            or 
219
+            (to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(2))
220
+            or 
221
+            (to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(3))
222
+        )
223
+    ) 
224
+    or 
225
+    (
226
+        (
227
+            Instructions_critiques_lecture_B(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
228
+        )
229
+        and 
230
+        (
231
+            (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(1))
232
+            or 
233
+            (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(2))
234
+            or 
235
+            (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(3))
236
+        )
237
+    ) 
238
+    or
239
+    (
240
+        (
241
+            Instructions_critiques_lecture_C(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
242
+        )
243
+        and 
244
+        (
245
+            (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(1))
246
+            or
247
+            (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(2))
248
+            or 
249
+            (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))
250
+        )
251
+    );
252
+    
253
+    
191 254
     R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
192 255
              '0';
193 256
     W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else

+ 54
- 13
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd View File

@@ -36,9 +36,14 @@ entity Etage2_5_Registres is
36 36
               Nb_registres : Natural;
37 37
               Instruction_bus_size : Natural;
38 38
               Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
39
-              Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
39
+              Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
40
+              Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
41
+              Code_Instruction_PRI : STD_LOGIC_VECTOR;
42
+              Code_Instruction_GET : STD_LOGIC_VECTOR);
40 43
     Port ( CLK : in STD_LOGIC;
41 44
            RST : in STD_LOGIC;
45
+           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
46
+           STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
42 47
            IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
43 48
            IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
44 49
            IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -59,13 +64,15 @@ architecture Behavioral of Etage2_5_Registres is
59 64
              Nb_regs : Natural);
60 65
     Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
61 66
            AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
67
+           AddrC : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
62 68
            AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
63 69
            W : in STD_LOGIC;
64 70
            DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
65 71
            RST : in STD_LOGIC;
66 72
            CLK : in STD_LOGIC;
67 73
            QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
68
-           QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
74
+           QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
75
+           QC : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
69 76
     end component;
70 77
     
71 78
     component LC is
@@ -87,9 +94,13 @@ architecture Behavioral of Etage2_5_Registres is
87 94
     end component;
88 95
     
89 96
     signal Commande_BancRegistres : STD_LOGIC_VECTOR (0 downto 0) := "0";
90
-    signal Sortie_BancRegistres : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
97
+    signal Entree_BancRegistre_DATA : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
98
+    signal Sortie_BancRegistres_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
99
+    signal Sortie_BancRegistres_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
100
+    signal intern_OUT_2_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
91 101
     signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
92 102
     signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
103
+    signal intern_STD_OUT : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
93 104
     
94 105
 begin
95 106
     instance_LC : LC
@@ -99,36 +110,66 @@ begin
99 110
     port map (   Instruction => IN_5_Instruction,
100 111
                  Commande => Commande_BancRegistres);
101 112
                  
102
-    instance_MUX : MUX
113
+    instance_MUX_A : MUX
103 114
     generic map (Nb_bits => Nb_bits,
104 115
                  Instruction_Vector_Size => Instruction_bus_size,
105
-                 Bits_Controle => Bits_Controle_MUX_2)
116
+                 Bits_Controle => Bits_Controle_MUX_2_A)
117
+    port map (   Instruction => IN_2_Instruction,
118
+                 IN1 => IN_2_A,
119
+                 IN2 => Sortie_BancRegistres_A,
120
+                 OUTPUT => intern_OUT_2_A);
121
+                 
122
+    instance_MUX_B : MUX
123
+    generic map (Nb_bits => Nb_bits,
124
+                 Instruction_Vector_Size => Instruction_bus_size,
125
+                 Bits_Controle => Bits_Controle_MUX_2_B)
106 126
     port map (   Instruction => IN_2_Instruction,
107 127
                  IN1 => IN_2_B,
108
-                 IN2 => Sortie_BancRegistres,
128
+                 IN2 => Sortie_BancRegistres_B,
109 129
                  OUTPUT => intern_OUT_2_B);
110 130
 
111 131
     instance_BancRegistres : BancRegistres
112 132
     generic map (Nb_bits => Nb_bits,
113 133
                  Addr_size => Nb_bits,
114 134
                  Nb_regs => Nb_registres)
115
-    port map ( AddrA => IN_2_B,
116
-               AddrB => IN_2_C,
135
+    port map ( AddrA => IN_2_A,
136
+               AddrB => IN_2_B,
137
+               AddrC => IN_2_C,
117 138
                AddrW => IN_5_A,
118 139
                W => Commande_BancRegistres(0),
119
-               DATA => IN_5_B,
140
+               DATA => Entree_BancRegistre_DATA,
120 141
                RST => RST,
121 142
                CLK => CLK,
122
-               QA => Sortie_BancRegistres,
123
-               QB => intern_OUT_2_C);                 
143
+               QA => Sortie_BancRegistres_A,
144
+               QB => Sortie_BancRegistres_B,
145
+               QC => intern_OUT_2_C);                 
124 146
                  
125 147
     OUT_2_A <= (others => '0') when RST = '0' else
126
-               IN_2_A;
148
+               intern_OUT_2_A;
127 149
     OUT_2_B <= (others => '0') when RST = '0' else
128 150
                intern_OUT_2_B;
129 151
     OUT_2_C <= (others => '0') when RST = '0' else
130 152
                intern_OUT_2_C;
131 153
     OUT_2_Instruction <= (others => '0') when RST = '0' else
132
-               IN_2_Instruction;    
154
+                         IN_2_Instruction;    
155
+      
156
+    process 
157
+    begin
158
+        wait until CLK'event and CLK = '1';
159
+        if (RST = '0') then
160
+            intern_STD_OUT <= (others => '0');
161
+        else
162
+            if (IN_2_Instruction = Code_Instruction_PRI) then
163
+                intern_STD_OUT <= intern_OUT_2_A;
164
+            end if;
165
+        end if;
166
+    end process;
167
+    STD_OUT <= intern_STD_OUT when RST = '1' else
168
+               (others => '0');
169
+    
170
+    Entree_BancRegistre_DATA <= (others => '0') when RST = '0' else
171
+                                STD_IN when IN_2_Instruction = Code_Instruction_GET else
172
+                                IN_5_B;
173
+    
133 174
     
134 175
 end Behavioral;

+ 62
- 3
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd View File

@@ -21,10 +21,11 @@
21 21
 
22 22
 library IEEE;
23 23
 use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 25
 
25 26
 -- Uncomment the following library declaration if using
26 27
 -- arithmetic functions with Signed or Unsigned values
27
---use IEEE.NUMERIC_STD.ALL;
28
+-- use IEEE.NUMERIC_STD.ALL;
28 29
 
29 30
 -- Uncomment the following library declaration if instantiating
30 31
 -- any Xilinx leaf cells in this code.
@@ -35,9 +36,14 @@ entity Etage4_Memoire is
35 36
     Generic ( Nb_bits : Natural;
36 37
               Mem_size : Natural;
37 38
               Instruction_bus_size : Natural;
39
+              Mem_EBP_size : Natural;
40
+              Adresse_size_mem_EBP : Natural;
38 41
               Bits_Controle_LC : STD_LOGIC_VECTOR;
39 42
               Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
40
-              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
43
+              Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
44
+              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR;
45
+              Code_Instruction_CALL : STD_LOGIC_VECTOR;
46
+              Code_Instruction_RET : STD_LOGIC_VECTOR);
41 47
     Port ( CLK : in STD_LOGIC;
42 48
            RST : in STD_LOGIC;
43 49
            IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -61,6 +67,20 @@ architecture Structural of Etage4_Memoire is
61 67
            D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
62 68
     end component;
63 69
     
70
+    component MemoireAdressesRetour is
71
+        Generic (Nb_bits : Natural;
72
+                 Addr_size : Natural;
73
+                 Mem_size : Natural);
74
+        Port ( R : in STD_LOGIC;
75
+               W : in STD_LOGIC;
76
+               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
77
+               RST : in STD_LOGIC;
78
+               CLK : in STD_LOGIC;
79
+               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
80
+               E : out STD_LOGIC;
81
+               F : out STD_LOGIC);
82
+    end component;
83
+    
64 84
     component LC is
65 85
         Generic (Instruction_Vector_Size : Natural;
66 86
                 Command_size : Natural;
@@ -80,9 +100,17 @@ architecture Structural of Etage4_Memoire is
80 100
     end component;
81 101
     
82 102
     signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
103
+    signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
104
+    signal Addr_MemoireDonnees_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
83 105
     signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0";
84 106
     signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
85 107
     signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
108
+    signal EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
109
+    signal R_Aux : STD_LOGIC := '0';
110
+    signal W_Aux : STD_LOGIC := '0';
111
+    signal E : STD_LOGIC;
112
+    signal F : STD_LOGIC;
113
+    
86 114
     
87 115
 begin
88 116
     instance_LC : LC
@@ -99,6 +127,15 @@ begin
99 127
     port map (   Instruction => IN_Instruction,
100 128
                  IN1 => IN_A,
101 129
                  IN2 => IN_B,
130
+                 OUTPUT => IN_Addr_MemoireDonnees);
131
+                 
132
+    instance_MUX_IN_EBP : MUX
133
+    generic map (Nb_bits => Nb_bits,
134
+                 Instruction_Vector_Size => Instruction_bus_size,
135
+                 Bits_Controle => Bits_Controle_MUX_IN_EBP)
136
+    port map (   Instruction => IN_Instruction,
137
+                 IN1 => IN_Addr_MemoireDonnees,
138
+                 IN2 => Addr_MemoireDonnees_EBP,
102 139
                  OUTPUT => Addr_MemoireDonnees);
103 140
                  
104 141
     instance_MUX_OUT : MUX
@@ -120,6 +157,21 @@ begin
120 157
                RST => RST,
121 158
                CLK => CLK,
122 159
                D_OUT => Sortie_MemoireDonnees);
160
+               
161
+    instance_MemoireEBP : MemoireAdressesRetour
162
+    generic map (Nb_bits => Nb_bits,
163
+                 Addr_size => Adresse_size_mem_EBP,
164
+                 Mem_size => Mem_EBP_size
165
+    )
166
+    port map ( R => R_Aux,
167
+               W => W_Aux,
168
+               D_IN => IN_B,
169
+               RST => RST,
170
+               CLK => CLK,
171
+               D_OUT => EBP,
172
+               E => E,
173
+               F => F
174
+    );
123 175
                  
124 176
     OUT_A <= (others => '0') when RST = '0' else
125 177
              IN_A;
@@ -127,5 +179,12 @@ begin
127 179
              intern_OUT_B;
128 180
     OUT_Instruction <= (others => '0') when RST = '0' else
129 181
              IN_Instruction;
130
-
182
+             
183
+    
184
+    R_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
185
+             '0';
186
+    W_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
187
+             '0';
188
+             
189
+    Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
131 190
 end Structural;

+ 1
- 0
Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd View File

@@ -67,6 +67,7 @@ begin
67 67
             end if;
68 68
         end if;
69 69
     end process;
70
+    
70 71
     E <= '1' when Addr = EMPTY else
71 72
          '0';
72 73
     F <= '1' when Addr = FULL else

+ 1
- 1
Processeur.srcs/sources_1/new/MemoireInstructions.vhd View File

@@ -40,7 +40,7 @@ entity MemoireInstructions is
40 40
 end MemoireInstructions;
41 41
 
42 42
 architecture Behavioral of MemoireInstructions is
43
-    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"f000000"&x"7040001"&x"6030001"&x"5020001"&x"9010500"&x"9000300"&x"d010000"&x"2000000"&x"e030000";
43
+    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := "10100"&x"000000"&"10001"&x"020000"&"01111"&x"010000"&"10101"&x"0a0000"&"10001"&x"000000"&"10101"&x"0a0000"&"10001"&x"010000"&"01001"&x"01ff00";
44 44
 begin
45 45
     D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
46 46
 end Behavioral;

+ 62
- 30
Processeur.srcs/sources_1/new/Pipeline.vhd View File

@@ -33,17 +33,19 @@ use IEEE.STD_LOGIC_1164.ALL;
33 33
 
34 34
 entity Pipeline is
35 35
     Generic (Nb_bits : Natural := 8;
36
-             Instruction_En_Memoire_Size : Natural := 28;
36
+             Instruction_En_Memoire_Size : Natural := 29;
37 37
              Addr_Memoire_Instruction_Size : Natural := 3;
38 38
              Memoire_Instruction_Size : Natural := 8;
39
-             Instruction_Bus_Size : Natural := 4;
40
-             Nb_Instructions : Natural := 16;
39
+             Instruction_Bus_Size : Natural := 5;
40
+             Nb_Instructions : Natural := 32;
41 41
              Nb_Registres : Natural := 16;
42
-             Memoire_Size : Natural := 8;
42
+             Memoire_Size : Natural := 32;
43 43
              Memoire_Adresses_Retour_Size : Natural := 16;
44 44
              Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
45 45
     Port (CLK : STD_LOGIC;
46
-          RST : STD_LOGIC);
46
+          RST : STD_LOGIC;
47
+          STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
48
+          STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
47 49
 end Pipeline;
48 50
 
49 51
 architecture Behavioral of Pipeline is
@@ -57,13 +59,15 @@ architecture Behavioral of Pipeline is
57 59
              Nb_registres : Natural;
58 60
              Mem_adresse_retour_size : Natural;
59 61
              Adresse_size_mem_adresse_retour : Natural;
60
-             Instructions_critiques_lecture : STD_LOGIC_VECTOR;
61
-             Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
62
+             Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
63
+             Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
64
+             Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
62 65
              Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
63 66
              Code_Instruction_JMP : STD_LOGIC_VECTOR;
64 67
              Code_Instruction_JMZ : STD_LOGIC_VECTOR;
65 68
              Code_Instruction_CALL : STD_LOGIC_VECTOR;
66
-             Code_Instruction_RET : STD_LOGIC_VECTOR);
69
+             Code_Instruction_RET : STD_LOGIC_VECTOR;
70
+             Code_Instruction_STOP : STD_LOGIC_VECTOR);
67 71
     Port ( CLK : in STD_LOGIC;
68 72
            RST : in STD_LOGIC;
69 73
            Z : in STD_LOGIC;
@@ -78,9 +82,14 @@ architecture Behavioral of Pipeline is
78 82
               Nb_registres : Natural;
79 83
               Instruction_bus_size : Natural;
80 84
               Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
81
-              Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
85
+              Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
86
+              Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
87
+              Code_Instruction_PRI : STD_LOGIC_VECTOR;
88
+              Code_Instruction_GET : STD_LOGIC_VECTOR);
82 89
     Port ( CLK : in STD_LOGIC;
83 90
            RST : in STD_LOGIC;
91
+           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
92
+           STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
84 93
            IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
85 94
            IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
86 95
            IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -117,9 +126,14 @@ architecture Behavioral of Pipeline is
117 126
         Generic ( Nb_bits : Natural;
118 127
                   Mem_size : Natural;
119 128
                   Instruction_bus_size : Natural;
129
+                  Mem_EBP_size : Natural;
130
+                  Adresse_size_mem_EBP : Natural;
120 131
                   Bits_Controle_LC : STD_LOGIC_VECTOR;
121 132
                   Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
122
-                  Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
133
+                  Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
134
+                  Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR;
135
+                  Code_Instruction_CALL : STD_LOGIC_VECTOR;
136
+                  Code_Instruction_RET : STD_LOGIC_VECTOR);
123 137
         Port ( CLK : in STD_LOGIC;
124 138
                RST : in STD_LOGIC;
125 139
                IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -163,21 +177,27 @@ architecture Behavioral of Pipeline is
163 177
     signal O : STD_LOGIC := '0';
164 178
     signal C : STD_LOGIC := '0';
165 179
     
166
-    constant Bits_Controle_MUX_2 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1101011000000001";
167
-    constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
168
-    constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111100000001";
169
-    constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111011111111111";
170
-    constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111101111111111";
171
-    constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000010000000000";
172
-    constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000011111111110";
173
-    constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1100";
174
-    constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1101";
175
-    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1110";
176
-    constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1111";
180
+    constant Bits_Controle_MUX_2_A      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
181
+    constant Bits_Controle_MUX_2_B      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
182
+    constant Bits_Controle_LC_3         : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
183
+    constant Bits_Controle_MUX_3        : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
184
+    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
185
+    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
186
+    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111100001111111111";
187
+    constant Bits_Controle_MUX_4_OUT    : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
188
+    constant Bits_Controle_LC_5         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
189
+    constant Code_Instruction_JMP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
190
+    constant Code_Instruction_JMZ  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000";
191
+    constant Code_Instruction_PRI  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001";
192
+    constant Code_Instruction_GET  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010";
193
+    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
194
+    constant Code_Instruction_RET  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
195
+    constant Code_Instruction_STOP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
177 196
     
178
-    constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000100111111110";
179
-    constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000000011111110";
180
-    constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000011111111110";
197
+    constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000100010000000000000";
198
+    constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000111100111111110";
199
+    constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
200
+    constant Instructions_critiques_ecriture  : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
181 201
 begin
182 202
     instance_Etage1 : Etage1_LectureInstruction
183 203
     generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
@@ -188,13 +208,15 @@ begin
188 208
                  Nb_registres => Nb_Registres,
189 209
                  Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
190 210
                  Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
191
-                 Instructions_critiques_lecture => Instructions_critiques_lecture,
192
-                 Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
211
+                 Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
212
+                 Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
213
+                 Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
193 214
                  Instructions_critiques_ecriture => Instructions_critiques_ecriture,
194 215
                  Code_Instruction_JMP => Code_Instruction_JMP,
195 216
                  Code_Instruction_JMZ => Code_Instruction_JMZ,
196 217
                  Code_Instruction_CALL => Code_Instruction_CALL,
197
-                 Code_Instruction_RET => Code_Instruction_RET
218
+                 Code_Instruction_RET => Code_Instruction_RET,
219
+                 Code_Instruction_STOP => Code_Instruction_STOP
198 220
     )
199 221
     port map (
200 222
         CLK => CLK,
@@ -211,10 +233,15 @@ begin
211 233
                  Nb_Registres => Nb_Registres,
212 234
                  Instruction_bus_size => Instruction_Bus_Size,
213 235
                  Bits_Controle_LC_5 => Bits_Controle_LC_5,
214
-                 Bits_Controle_MUX_2 => Bits_Controle_MUX_2
236
+                 Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
237
+                 Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B,
238
+                 Code_Instruction_PRI => Code_Instruction_PRI,
239
+                 Code_Instruction_GET => Code_Instruction_GET
215 240
     )
216 241
     port map(    CLK => CLK,
217 242
                  RST => RST,
243
+                 STD_IN => STD_IN,
244
+                 STD_OUT => STD_OUT,
218 245
                  IN_2_A => A_to_2,
219 246
                  IN_2_B => B_to_2,
220 247
                  IN_2_C => C_to_2,
@@ -247,14 +274,19 @@ begin
247 274
                  Z => Z,
248 275
                  C => C
249 276
     );
250
-    
277
+                      
251 278
     instance_Etage4 : Etage4_Memoire
252 279
     generic map( Nb_bits => Nb_bits,
253 280
                  Mem_size => Memoire_Size,
254 281
                  Instruction_bus_size => Instruction_Bus_Size,
282
+                 Mem_EBP_size => Memoire_Adresses_Retour_Size,
283
+                 Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,
255 284
                  Bits_Controle_LC => Bits_Controle_LC_4,
256 285
                  Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
257
-                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT
286
+                 Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
287
+                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT,
288
+                 Code_Instruction_CALL => Code_Instruction_CALL,
289
+                 Code_Instruction_RET => Code_Instruction_RET
258 290
     )
259 291
     port map(    CLK => CLK,
260 292
                  RST => RST,

+ 44
- 25
Processeur.srcs/sources_1/new/System.vhd View File

@@ -33,35 +33,54 @@ use IEEE.STD_LOGIC_1164.ALL;
33 33
 
34 34
 entity System is
35 35
     Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
36
-           flag : out STD_LOGIC_VECTOR (3 downto 0);
37
-           sw : in STD_LOGIC_VECTOR (15 downto 0);
36
+           sw : in STD_LOGIC_VECTOR (7 downto 0);
38 37
            btnC : in STD_LOGIC;
39
-           btnL : in STD_LOGIC;
40
-           btnR : in STD_LOGIC);
38
+           CLK : STD_LOGIC);
41 39
 end System;
42 40
 
43 41
 architecture Structural of System is
44
-    component ALU
45
-        Generic (Nb_bits : Natural);
46
-        Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
47
-               B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
48
-               OP : in STD_LOGIC_VECTOR (1 downto 0);
49
-               S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
50
-               N : out STD_LOGIC;
51
-               O : out STD_LOGIC;
52
-               Z : out STD_LOGIC;
53
-               C : out STD_LOGIC);
42
+    component Pipeline is
43
+    Generic (Nb_bits : Natural := 8;
44
+             Instruction_En_Memoire_Size : Natural := 29;
45
+             Addr_Memoire_Instruction_Size : Natural := 3;
46
+             Memoire_Instruction_Size : Natural := 8;
47
+             Instruction_Bus_Size : Natural := 5;
48
+             Nb_Instructions : Natural := 32;
49
+             Nb_Registres : Natural := 16;
50
+             Memoire_Size : Natural := 32;
51
+             Memoire_Adresses_Retour_Size : Natural := 16;
52
+             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
53
+    Port (CLK : STD_LOGIC;
54
+          RST : STD_LOGIC;
55
+          STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
56
+          STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
54 57
     end component;
55
-    signal aux: STD_LOGIC_VECTOR (1 downto 0);
56
-    signal aux4: STD_LOGIC;
57
-    signal aux5: STD_LOGIC;
58
-    signal aux6: STD_LOGIC;
59
-    signal aux7: STD_LOGIC;
58
+    
59
+    component Clock_Divider is
60
+        Port ( CLK_IN : in STD_LOGIC;
61
+               CLK_OUT : out STD_LOGIC);
62
+    end component;
63
+    
64
+    signal my_RST : STD_LOGIC;
65
+    signal my_CLK : STD_LOGIC;
66
+    signal buff_CLK : STD_LOGIC;
67
+        
60 68
 begin
61
-    aux <= "01" when btnC = '1' else
62
-           "10" when btnR = '1' else
63
-           "11" when btnL = '1' else
64
-           "00";
65
-    flag <= aux4 & aux5 & aux6 & aux7;
66
-    My_ALU: ALU generic map (Nb_bits => 8) port map(sw (15 downto 8), sw (7 downto 0), aux, led, aux4, aux5, aux6, aux7);
69
+    clk_div : Clock_Divider
70
+    port map (CLK_IN => CLK,
71
+              CLK_OUT => buff_CLK);
72
+              
73
+    clk_div_2 : Clock_Divider
74
+    port map (CLK_IN => buff_CLK,
75
+              CLK_OUT => my_CLK);
76
+              
77
+    instance : Pipeline
78
+    port map (CLK => my_CLK,
79
+              RST => my_RST,
80
+              STD_IN => sw,
81
+              STD_OUT => led);
82
+              
83
+    my_RST <= '0' when btnC = '1' else
84
+              '1';
67 85
 end Structural;
86
+

+ 11
- 3
Processeur.xpr View File

@@ -3,7 +3,7 @@
3 3
 <!--                                                         -->
4 4
 <!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.   -->
5 5
 
6
-<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Processeur/Processeur.xpr">
6
+<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr">
7 7
   <DefaultLaunch Dir="$PRUNDIR"/>
8 8
   <Configuration>
9 9
     <Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/>
@@ -32,7 +32,7 @@
32 32
     <Option Name="EnableBDX" Val="FALSE"/>
33 33
     <Option Name="DSABoardId" Val="basys3"/>
34 34
     <Option Name="DSANumComputeUnits" Val="16"/>
35
-    <Option Name="WTXSimLaunchSim" Val="145"/>
35
+    <Option Name="WTXSimLaunchSim" Val="176"/>
36 36
     <Option Name="WTModelSimLaunchSim" Val="0"/>
37 37
     <Option Name="WTQuestaLaunchSim" Val="0"/>
38 38
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -133,6 +133,12 @@
133 133
           <Attr Name="UsedIn" Val="simulation"/>
134 134
         </FileInfo>
135 135
       </File>
136
+      <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
137
+        <FileInfo>
138
+          <Attr Name="UsedIn" Val="synthesis"/>
139
+          <Attr Name="UsedIn" Val="simulation"/>
140
+        </FileInfo>
141
+      </File>
136 142
       <Config>
137 143
         <Option Name="DesignMode" Val="RTL"/>
138 144
         <Option Name="TopModule" Val="System"/>
@@ -246,6 +252,7 @@
246 252
         <Option Name="SrcSet" Val="sources_1"/>
247 253
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
248 254
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
255
+        <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
249 256
       </Config>
250 257
     </FileSet>
251 258
   </FileSets>
@@ -276,7 +283,7 @@
276 283
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
277 284
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
278 285
     </Run>
279
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
286
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
280 287
       <Strategy Version="1" Minor="2">
281 288
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
282 289
         <Step Id="init_design"/>
@@ -289,6 +296,7 @@
289 296
         <Step Id="post_route_phys_opt_design"/>
290 297
         <Step Id="write_bitstream"/>
291 298
       </Strategy>
299
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
292 300
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
293 301
     </Run>
294 302
   </Runs>

+ 7
- 154
vivado.jou View File

@@ -2,159 +2,12 @@
2 2
 # Vivado v2016.4 (64-bit)
3 3
 # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4 4
 # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Mon Apr 19 10:14:33 2021
6
-# Process ID: 6416
7
-# Current directory: C:/Users/Hp/Documents/Processeur
8
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16404 C:\Users\Hp\Documents\Processeur\Processeur.xpr
9
-# Log file: C:/Users/Hp/Documents/Processeur/vivado.log
10
-# Journal file: C:/Users/Hp/Documents/Processeur\vivado.jou
5
+# Start of session at: Mon May 03 15:56:37 2021
6
+# Process ID: 5172
7
+# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
8
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15260 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
9
+# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
10
+# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
11 11
 #-----------------------------------------------------------
12 12
 start_gui
13
-open_project C:/Users/Hp/Documents/Processeur/Processeur.xpr
14
-launch_simulation
15
-source Test_LC.tcl
16
-close_sim
17
-launch_simulation
18
-source Test_LC.tcl
19
-add_bp {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} 44
20
-remove_bps -file {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} -line 44
21
-close_sim
22
-launch_simulation
23
-launch_simulation
24
-source Test_LC.tcl
25
-close_sim
26
-launch_simulation
27
-source Test_LC.tcl
28
-close_sim
29
-launch_simulation
30
-source Test_LC.tcl
31
-close_sim
32
-launch_simulation
33
-source Test_LC.tcl
34
-close_sim
35
-launch_simulation
36
-source Test_LC.tcl
37
-close_sim
38
-launch_simulation
39
-source Test_LC.tcl
40
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
41
-close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd w ]
42
-add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd
43
-set_property top Test_Etage3_Calcul [get_filesets sim_1]
44
-set_property top_lib xil_defaultlib [get_filesets sim_1]
45
-launch_simulation
46
-launch_simulation
47
-launch_simulation
48
-launch_simulation
49
-source Test_Etage3_Calcul.tcl
50
-close_sim
51
-launch_simulation
52
-source Test_Etage3_Calcul.tcl
53
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
54
-close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd w ]
55
-add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
56
-set_property top Test_Etage4_Memoire [get_filesets sim_1]
57
-set_property top_lib xil_defaultlib [get_filesets sim_1]
58
-launch_simulation
59
-launch_simulation
60
-source Test_Etage4_Memoire.tcl
61
-set_property top Test_Etage3_Calcul [get_filesets sim_1]
62
-set_property top_lib xil_defaultlib [get_filesets sim_1]
63
-current_sim simulation_10
64
-close_sim
65
-launch_simulation
66
-source Test_Etage3_Calcul.tcl
67
-set_property top Test_Etage4_Memoire [get_filesets sim_1]
68
-set_property top_lib xil_defaultlib [get_filesets sim_1]
69
-current_sim simulation_11
70
-close_sim
71
-launch_simulation
72
-source Test_Etage4_Memoire.tcl
73
-close_sim
74
-launch_simulation
75
-source Test_Etage4_Memoire.tcl
76
-close_sim
77
-launch_simulation
78
-source Test_Etage4_Memoire.tcl
79
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
80
-close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd w ]
81
-add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd
82
-set_property top Test_Etage2_5_Registres [get_filesets sim_1]
83
-set_property top_lib xil_defaultlib [get_filesets sim_1]
84
-launch_simulation
85
-source Test_Etage2_5_Registres.tcl
86
-close_sim
87
-launch_simulation
88
-source Test_Etage2_5_Registres.tcl
89
-close_sim
90
-launch_simulation
91
-source Test_Etage2_5_Registres.tcl
92
-close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd w ]
93
-add_files C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd
94
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
95
-close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd w ]
96
-add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd
97
-set_property top Test_Pipeline [get_filesets sim_1]
98
-set_property top_lib xil_defaultlib [get_filesets sim_1]
99
-launch_simulation
100
-launch_simulation
101
-launch_simulation
102
-launch_simulation
103
-source Test_Pipeline.tcl
104
-add_wave {{/Test_Pipeline/instance/Instruction_1_to_2}} {{/Test_Pipeline/instance/Instruction_2_to_3}} {{/Test_Pipeline/instance/Instruction_3_to_4}} {{/Test_Pipeline/instance/Instruction_4_to_5}} 
105
-run all
106
-run 10 us
107
-run 10 us
108
-restart
109
-run 10 us
110
-restart
111
-run 10 us
112
-close_sim
113
-launch_simulation
114
-source Test_Pipeline.tcl
115
-restart
116
-run 10 us
117
-close_sim
118
-launch_simulation
119
-current_sim simulation_18
120
-launch_simulation
121
-launch_simulation
122
-launch_simulation
123
-source Test_Pipeline.tcl
124
-restart
125
-run 10 us
126
-close_sim
127
-launch_simulation
128
-source Test_Pipeline.tcl
129
-restart
130
-run 10 us
131
-save_wave_config {C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg}
132
-add_files -fileset sim_1 -norecurse C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
133
-set_property xsim.view C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg [get_filesets sim_1]
134
-close_sim
135
-launch_simulation
136
-source Test_Pipeline.tcl
137
-restart
138
-run 10 us
139
-restart
140
-run 10 us
141
-restart
142
-run 10 us
143
-close_sim
144
-launch_simulation
145
-current_sim simulation_18
146
-launch_simulation
147
-launch_simulation
148
-source Test_Pipeline.tcl
149
-restart
150
-run 10 us
151
-close_sim
152
-launch_simulation
153
-source Test_Pipeline.tcl
154
-restart
155
-run 10 us
156
-close_sim
157
-launch_simulation
158
-source Test_Pipeline.tcl
159
-restart
160
-run 10 us
13
+open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr

+ 13
- 4072
vivado.log
File diff suppressed because it is too large
View File


Loading…
Cancel
Save