Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.04.2021 17:35:57
-- Design Name: 
-- Module Name: Test_Pipeline - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_Pipeline is
--  Port ( );
end Test_Pipeline;

architecture Behavioral of Test_Pipeline is
    
    component Pipeline is
    Generic (Nb_bits : Natural := 8;
             Instruction_En_Memoire_Size : Natural := 29;
             Addr_Memoire_Instruction_Size : Natural := 3;
             Memoire_Instruction_Size : Natural := 8;
             Instruction_Bus_Size : Natural := 5;
             Nb_Instructions : Natural := 32;
             Nb_Registres : Natural := 16;
             Memoire_Size : Natural := 32;
             Memoire_Adresses_Retour_Size : Natural := 16;
             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
    Port (CLK : STD_LOGIC;
          RST : STD_LOGIC;
          STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
          STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
    end component;
    
    signal my_CLK : STD_LOGIC := '0';
    signal my_RST : STD_LOGIC := '1';
    signal my_STD_IN : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
    signal my_STD_OUT : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
    
    constant CLK_period : time := 10 ns;
    
begin
    instance : Pipeline
    port map (CLK => my_CLK,
              RST => my_RST,
              STD_IN => my_STD_IN,
              STD_OUT => my_STD_OUT);
              
    CLK_process :process
    begin
        my_CLK <= '1';
        wait for CLK_period/2;
        my_CLK <= '0';
        wait for CLK_period/2;
    end process;
    
    process 
    begin
        my_RST <= '0' after 34 ns, '1' after 57 ns;
        wait;
    end process;
end Behavioral;