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MemoireInstructions.vhd 1.5KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 16.04.2021 14:35:04
  6. -- Design Name:
  7. -- Module Name: MemoireInstructions - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity MemoireInstructions is
  30. Generic (Nb_bits : Natural;
  31. Addr_size : Natural;
  32. Mem_size : Natural);
  33. Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
  34. D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
  35. end MemoireInstructions;
  36. architecture Behavioral of MemoireInstructions is
  37. signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := "10100"&x"000000"&"10001"&x"020000"&"01111"&x"010000"&"10101"&x"0a0000"&"10001"&x"000000"&"10101"&x"0a0000"&"10001"&x"010000"&"01001"&x"01ff00";
  38. begin
  39. D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
  40. end Behavioral;