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Screen en cours

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This commit is contained in:
Paul Faure 2021-06-30 16:36:19 +02:00
parent 1c8364b30d
commit c5bf8f5b1f
15 changed files with 1494 additions and 108 deletions
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120
Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
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@ -9,22 +9,22 @@ set_property IOSTANDARD LVCMOS33 [get_ports CLK]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
## Switches ## Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}] #set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] # set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}] #set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] # set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}] #set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] # set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}] #set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] # set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw[4]}] #set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] # set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw[5]}] #set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] # set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw[6]}] #set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] # set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw[7]}] #set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] # set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}] #set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] # set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}] #set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
@ -44,22 +44,22 @@ set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
## LEDs ## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}] #set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] # set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}] #set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] # set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}] #set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] # set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}] #set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] # set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}] #set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] # set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}] #set_property PACKAGE_PIN U15 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] # set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}] #set_property PACKAGE_PIN U14 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] # set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}] #set_property PACKAGE_PIN V14 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] # set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}] #set_property PACKAGE_PIN V13 [get_ports {led[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}] #set_property PACKAGE_PIN V3 [get_ports {led[9]}]
@ -233,34 +233,34 @@ set_property PACKAGE_PIN U18 [get_ports btnC]
##VGA Connector ##VGA Connector
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
#set_property PACKAGE_PIN P19 [get_ports Hsync] set_property PACKAGE_PIN P19 [get_ports Hsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync] set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
#set_property PACKAGE_PIN R19 [get_ports Vsync] set_property PACKAGE_PIN R19 [get_ports Vsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync] set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
##USB-RS232 Interface ##USB-RS232 Interface

63
Processeur.srcs/sim_1/new/TestTableASCII.vhd Normal file
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@ -0,0 +1,63 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 29.06.2021 16:16:32
-- Design Name:
-- Module Name: TestTableASCII - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.font.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestTableASCII is
-- Port ( );
end TestTableASCII;
architecture Behavioral of TestTableASCII is
component TableASCII is
port ( CodeASCII : in Natural;
Font : out font_T);
end component;
signal my_CodeASCII : Natural := 0;
signal my_Font : font_T := (others => (others => '0'));
begin
instance : TableASCII
port map( CodeASCII => my_CodeASCII,
Font => my_Font
);
process
begin
my_CodeASCII <= 0 after 5 ns, 1 after 10 ns, 65 after 15 ns, 66 after 25 ns;
wait;
end process;
end Behavioral;

96
Processeur.srcs/sim_1/new/Test_Ecran.vhd Normal file
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@ -0,0 +1,96 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.06.2021 11:25:08
-- Design Name:
-- Module Name: Test_Ecran - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Ecran is
-- Port ( );
end Test_Ecran;
architecture Behavioral of Test_Ecran is
component Ecran is
Generic ( HEIGHT : Natural;
WIDTH : Natural;
CaracterHeight : Natural;
CaracterWidht : Natural
);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in STD_LOGIC_VECTOR (6 downto 0);
X : in Natural;
Y : in Natural;
OUT_ON : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
signal my_Data_Av : STD_LOGIC := '0';
signal my_Data_IN : STD_LOGIC_VECTOR (6 downto 0) := (others => '0');
signal my_X : Natural := 0;
signal my_Y : Natural := 0;
signal my_OUT_ON : STD_LOGIC_VECTOR (6 downto 0) := (others => '0');
constant CLK_period : time := 10 ns;
begin
instance : Ecran
generic map( HEIGHT => 14,
WIDTH => 22,
CaracterHeight => 4,
CaracterWidht => 5
)
port map( CLK => my_CLK,
RST => my_RST,
Data_Av => my_Data_Av,
Data_IN => my_Data_IN,
X => my_X,
Y => my_Y,
OUT_ON => my_OUT_ON);
CLK_process : process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
my_Data_Av <= '1' after 0 ns;
my_Data_IN <= "0000001" after 0 ns, "0000010" after 40 ns, "0000011" after 80 ns, "0000100" after 120 ns, "0001101" after 140 ns, "0000101" after 150 ns, "0000000" after 170 ns, "0000001" after 180 ns, "0000010" after 220 ns;
wait;
end process;
end Behavioral;

3
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
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@ -100,8 +100,7 @@ begin
IN_Instruction => my_IN_Instruction, IN_Instruction => my_IN_Instruction,
OUT_A => my_OUT_A, OUT_A => my_OUT_A,
OUT_B => my_OUT_B, OUT_B => my_OUT_B,
OUT_Instruction => my_OUT_Instruction, OUT_Instruction => my_OUT_Instruction);
OUT_AddrRetour => my_OUT_AddrRetour);
CLK_process :process CLK_process :process
begin begin

90
Processeur.srcs/sim_1/new/Test_ScreenSystem.vhd Normal file
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@ -0,0 +1,90 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 29.06.2021 08:40:33
-- Design Name:
-- Module Name: Test_ScreenSystem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_ScreenSystem is
-- Port ( );
end Test_ScreenSystem;
architecture Behavioral of Test_ScreenSystem is
component ScreenSystem is
Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC;
btnC : in STD_LOGIC;
CLK : in STD_LOGIC
);
end component;
signal my_vgaRed : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_vgaBlue : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_Hsync : STD_LOGIC := '0';
signal my_Vsync : STD_LOGIC := '0';
signal my_btnC : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
constant CLK_period : time := 10 ns;
begin
instance : ScreenSystem
port map (
vgaRed => my_vgaRed,
vgaBlue => my_vgaBlue,
vgaGreen => my_vgaGreen,
Hsync => my_Hsync,
Vsync => my_Vsync,
btnC => my_btnC,
CLK => my_CLK
);
CLK_process :process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
wait;
end process;
end Behavioral;

108
Processeur.srcs/sim_1/new/Test_VGAControler.vhd Normal file
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@ -0,0 +1,108 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.06.2021 15:55:57
-- Design Name:
-- Module Name: Test_VGAControler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Test_VGAControler is
-- Port ( );
end Test_VGAControler;
architecture Behavioral of Test_VGAControler is
component VGAControler is
Generic ( HEIGHT : Natural;
WIDTH : Natural;
X_PulseWidth : Natural;
X_FrontPorch : Natural;
X_BackPorch : Natural;
Y_PulseWidth : Natural;
Y_FrontPorch : Natural;
Y_BackPorch : Natural
);
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
X : out Natural;
Y : out Natural;
PIXEL_ON : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC);
end component;
signal my_VGA_RED : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_VGA_BLUE : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_VGA_GREEN : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_VGA_HS : STD_LOGIC := '0';
signal my_VGA_VS : STD_LOGIC := '0';
signal my_X : Natural := 0;
signal my_Y : Natural := 0;
signal my_PIXEL_ON : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
constant CLK_period : time := 10 ns;
begin
instance : VGAControler
generic map( HEIGHT => 4,
WIDTH =>10,
X_PulseWidth => 2,
X_FrontPorch => 1,
X_BackPorch => 3,
Y_PulseWidth => 1,
Y_FrontPorch => 1,
Y_BackPorch => 1)
port map( VGA_RED => my_VGA_RED,
VGA_BLUE => my_VGA_BLUE,
VGA_GREEN => my_VGA_GREEN,
VGA_HS => my_VGA_HS,
VGA_VS => my_VGA_VS,
X => my_X,
Y => my_Y,
PIXEL_ON => my_PIXEL_ON,
CLK => my_CLK,
RST => my_RST);
CLK_process : process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
my_PIXEL_ON <= '1' after 50 ns, '0' after 100 ns, '1' after 150 ns, '0' after 200 ns;
wait;
end process;
end Behavioral;

61
Processeur.srcs/sources_1/new/Compteur.vhd Normal file
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@ -0,0 +1,61 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.06.2021 14:59:39
-- Design Name:
-- Module Name: Compteur - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Compteur is
Generic (Min : Natural;
Max : Natural
);
Port (CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out Natural;
Carry : out STD_LOGIC);
end Compteur;
architecture Behavioral of Compteur is
signal current : Natural := Min;
signal InternCarry : STD_LOGIC := '0';
begin
process
begin
wait until CLK'event and CLK = '1';
if (RST = '0') then
current <= Min;
else
current <= current + 1;
if (current = Max) then
InternCarry <= '1';
current <= Min;
else
InternCarry <= '0';
end if;
end if;
end process;
Value <= current;
Carry <= InternCarry;
end Behavioral;

118
Processeur.srcs/sources_1/new/Ecran.vhd Normal file
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@ -0,0 +1,118 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.06.2021 09:20:00
-- Design Name:
-- Module Name: Ecran - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.font.all;
entity Ecran is
Generic ( HEIGHT : Natural;
WIDTH : Natural
);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in Natural;
X : in Natural;
Y : in Natural;
OUT_ON : out STD_LOGIC);
end Ecran;
architecture Behavioral of Ecran is
component TableASCII is
Port ( CodeASCII : Natural;
Font : out font_T);
end component;
constant Flush : Natural := 0;
constant RetourChariot : Natural := 13;
constant CaracterHeight : Natural := 16;
constant CaracterWidht : Natural := 16;
constant HeightSize : Natural := HEIGHT/CaracterHeight;
constant WidthSize : Natural := WIDTH/CaracterWidht;
type T_Ligne is array (0 to WidthSize - 1) of Natural;
type T_Ecran is array (0 to HeightSize - 1) of T_Ligne;
signal Ecran : T_Ecran := (others => (0 => 72, 1 => 101, 2 => 108, 3 => 108, 4 => 111, 5 => 32, 6 => 87, 7 => 111, 8 => 114, 9 => 108, 10 => 100, others => 0));
signal L : Natural := 0;
signal C : Natural := 0;
signal InitialL : Natural := 0;
signal Full : BOOLEAN := false;
signal CurrentCodeASCII : Natural := 0;
signal CurrentFont : font_T;
begin
instance_TableASCII : TableASCII
port map (CodeASCII => CurrentCodeASCII,
Font => CurrentFont);
process
begin
wait until CLK'event and CLK='1';
if (RST = '0') then
Ecran <= (others => (others => 0));
L <= 0;
C <= 0;
InitialL <= 0;
Full <= false;
elsif (Data_Av = '1') then
if (Data_IN = Flush) then
Ecran <= (others => (others => 0));
L <= 0;
C <= 0;
InitialL <= 0;
Full <= false;
elsif (Data_IN = RetourChariot) then
C <= 0;
L <= (L + 1) mod HeightSize;
if ((L + 1) mod HeightSize = 0 or Full) then
Full <= true;
InitialL <= (InitialL + 1) mod HeightSize;
Ecran((L + 1) mod HeightSize) <= (others => 0);
end if;
else
Ecran(L)(C) <= Data_IN;
C <= C + 1;
if (C + 1 = WidthSize) then
C <= 0;
L <= (L + 1) mod HeightSize;
if ((L + 1) mod HeightSize = 0 or Full) then
Full <= true;
InitialL <= (InitialL + 1) mod HeightSize;
Ecran((L + 1) mod HeightSize) <= (others => 0);
end if;
end if;
end if;
end if;
end process;
CurrentCodeASCII <= Ecran((Y/CaracterHeight + InitialL) mod HeightSize)(X/CaracterWidht) when (Y/CaracterHeight < HeightSize and X/CaracterWidht < WidthSize and RST='1') else
0;
OUT_ON <= CurrentFont((Y mod CaracterHeight) / (CaracterHeight / font_height), (X mod CaracterWidht) / (CaracterWidht / font_width));
end Behavioral;

169
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.06.2021 17:27:26
-- Design Name:
-- Module Name: ScreenSystem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ScreenSystem is
Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC;
btnC : in STD_LOGIC;
CLK : in STD_LOGIC
);
end ScreenSystem;
architecture Behavioral of ScreenSystem is
component VGAControler is
Generic ( HEIGHT : Natural;
WIDTH : Natural;
X_PulseWidth : Natural;
X_FrontPorch : Natural;
X_BackPorch : Natural;
Y_PulseWidth : Natural;
Y_FrontPorch : Natural;
Y_BackPorch : Natural
);
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
X : out Natural;
Y : out Natural;
PIXEL_ON : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC);
end component;
component clk_wiz_0
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic
);
end component;
component Ecran is
Generic ( HEIGHT : Natural;
WIDTH : Natural
);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in Natural;
X : in Natural;
Y : in Natural;
OUT_ON : out STD_LOGIC);
end component;
signal my_X : Natural := 0;
signal my_Y : Natural := 0;
signal my_PIXEL_ON : STD_LOGIC := '0';
signal compteur : natural := 0;
signal my_CLK : STD_LOGIC := '0';
signal RST : STD_LOGIC;
begin
instanceVGA : VGAControler
-- generic map( HEIGHT => 480,
-- WIDTH => 640,
-- X_PulseWidth => 96,
-- X_FrontPorch => 16,
-- X_BackPorch => 48,
-- Y_PulseWidth => 2,
-- Y_FrontPorch => 10,
-- Y_BackPorch => 33)
generic map( HEIGHT => 1024,
WIDTH => 1280,
X_PulseWidth => 112,
X_FrontPorch => 48,
X_BackPorch => 248,
Y_PulseWidth => 3,
Y_FrontPorch => 1,
Y_BackPorch => 38)
port map( VGA_RED => vgaRed,
VGA_BLUE => vgaBlue,
VGA_GREEN => vgaGreen,
VGA_HS => Hsync,
VGA_VS => Vsync,
X => my_X,
Y => my_Y,
PIXEL_ON => my_PIXEL_ON,
CLK => my_CLK,
RST => RST);
clk_wiz_0_inst : clk_wiz_0
port map (
clk_in1 => CLK,
clk_out1 => my_CLK
);
-- process
-- begin
-- wait until CLK'event and CLK = '1';
-- compteur <= (compteur + 1) mod 4;
-- if (compteur = 0) then
-- my_CLK <= '1';
-- elsif (compteur = 2) then
-- my_CLK <= '0';
-- end if;
-- end process;
instance_Ecran : Ecran
generic map ( HEIGHT => 1024,
WIDTH => 1280
)
port map ( CLK => CLK,
RST => RST,
Data_Av => '0',
Data_IN => 0,
X => my_X,
Y => my_Y,
OUT_ON => my_PIXEL_ON);
-- Gestion du RST (inversion d'état)
RST <= '1' when btnC = '0' else
'0';
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.06.2021 09:20:00
-- Design Name:
-- Module Name: TableASCII - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
use work.font.all;
entity TableASCII is
Port ( CodeASCII : Natural;
Font : out font_T);
end TableASCII;
architecture Behavioral of TableASCII is
type FontMemory_T is array (0 to 127) of font_T;
signal FontMemory : FontMemory_T := (
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0000 (nul)
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0001
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0002
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0003
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0004
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0005
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0006
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0007
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0008
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0009
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+000A
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+000B
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+000C
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+000D
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+000E
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+000F
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0010
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0011
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0012
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0013
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0014
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0015
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0016
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0017
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0018
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0019
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+001A
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+001B
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+001C
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+001D
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+001E
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+001F
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0020 (space)
( x"18", x"3C", x"3C", x"18", x"18", x"00", x"18", x"00"), -- U+0021 (!)
( x"36", x"36", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+0022 (")
( x"36", x"36", x"7F", x"36", x"7F", x"36", x"36", x"00"), -- U+0023 (#)
( x"0C", x"3E", x"03", x"1E", x"30", x"1F", x"0C", x"00"), -- U+0024 ($)
( x"00", x"63", x"33", x"18", x"0C", x"66", x"63", x"00"), -- U+0025 (%)
( x"1C", x"36", x"1C", x"6E", x"3B", x"33", x"6E", x"00"), -- U+0026 (&)
( x"06", x"06", x"03", x"00", x"00", x"00", x"00", x"00"), -- U+0027 (')
( x"18", x"0C", x"06", x"06", x"06", x"0C", x"18", x"00"), -- U+0028 (()
( x"06", x"0C", x"18", x"18", x"18", x"0C", x"06", x"00"), -- U+0029 ())
( x"00", x"66", x"3C", x"FF", x"3C", x"66", x"00", x"00"), -- U+002A (*)
( x"00", x"0C", x"0C", x"3F", x"0C", x"0C", x"00", x"00"), -- U+002B (+)
( x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"06"), -- U+002C (,)
( x"00", x"00", x"00", x"3F", x"00", x"00", x"00", x"00"), -- U+002D (-)
( x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"00"), -- U+002E (.)
( x"60", x"30", x"18", x"0C", x"06", x"03", x"01", x"00"), -- U+002F (/)
( x"3E", x"63", x"73", x"7B", x"6F", x"67", x"3E", x"00"), -- U+0030 (0)
( x"0C", x"0E", x"0C", x"0C", x"0C", x"0C", x"3F", x"00"), -- U+0031 (1)
( x"1E", x"33", x"30", x"1C", x"06", x"33", x"3F", x"00"), -- U+0032 (2)
( x"1E", x"33", x"30", x"1C", x"30", x"33", x"1E", x"00"), -- U+0033 (3)
( x"38", x"3C", x"36", x"33", x"7F", x"30", x"78", x"00"), -- U+0034 (4)
( x"3F", x"03", x"1F", x"30", x"30", x"33", x"1E", x"00"), -- U+0035 (5)
( x"1C", x"06", x"03", x"1F", x"33", x"33", x"1E", x"00"), -- U+0036 (6)
( x"3F", x"33", x"30", x"18", x"0C", x"0C", x"0C", x"00"), -- U+0037 (7)
( x"1E", x"33", x"33", x"1E", x"33", x"33", x"1E", x"00"), -- U+0038 (8)
( x"1E", x"33", x"33", x"3E", x"30", x"18", x"0E", x"00"), -- U+0039 (9)
( x"00", x"0C", x"0C", x"00", x"00", x"0C", x"0C", x"00"), -- U+003A (:)
( x"00", x"0C", x"0C", x"00", x"00", x"0C", x"0C", x"06"), -- U+003B (--)
( x"18", x"0C", x"06", x"03", x"06", x"0C", x"18", x"00"), -- U+003C (<)
( x"00", x"00", x"3F", x"00", x"00", x"3F", x"00", x"00"), -- U+003D (=)
( x"06", x"0C", x"18", x"30", x"18", x"0C", x"06", x"00"), -- U+003E (>)
( x"1E", x"33", x"30", x"18", x"0C", x"00", x"0C", x"00"), -- U+003F (?)
( x"3E", x"63", x"7B", x"7B", x"7B", x"03", x"1E", x"00"), -- U+0040 (@)
( x"0C", x"1E", x"33", x"33", x"3F", x"33", x"33", x"00"), -- U+0041 (A)
( x"3F", x"66", x"66", x"3E", x"66", x"66", x"3F", x"00"), -- U+0042 (B)
( x"3C", x"66", x"03", x"03", x"03", x"66", x"3C", x"00"), -- U+0043 (C)
( x"1F", x"36", x"66", x"66", x"66", x"36", x"1F", x"00"), -- U+0044 (D)
( x"7F", x"46", x"16", x"1E", x"16", x"46", x"7F", x"00"), -- U+0045 (E)
( x"7F", x"46", x"16", x"1E", x"16", x"06", x"0F", x"00"), -- U+0046 (F)
( x"3C", x"66", x"03", x"03", x"73", x"66", x"7C", x"00"), -- U+0047 (G)
( x"33", x"33", x"33", x"3F", x"33", x"33", x"33", x"00"), -- U+0048 (H)
( x"1E", x"0C", x"0C", x"0C", x"0C", x"0C", x"1E", x"00"), -- U+0049 (I)
( x"78", x"30", x"30", x"30", x"33", x"33", x"1E", x"00"), -- U+004A (J)
( x"67", x"66", x"36", x"1E", x"36", x"66", x"67", x"00"), -- U+004B (K)
( x"0F", x"06", x"06", x"06", x"46", x"66", x"7F", x"00"), -- U+004C (L)
( x"63", x"77", x"7F", x"7F", x"6B", x"63", x"63", x"00"), -- U+004D (M)
( x"63", x"67", x"6F", x"7B", x"73", x"63", x"63", x"00"), -- U+004E (N)
( x"1C", x"36", x"63", x"63", x"63", x"36", x"1C", x"00"), -- U+004F (O)
( x"3F", x"66", x"66", x"3E", x"06", x"06", x"0F", x"00"), -- U+0050 (P)
( x"1E", x"33", x"33", x"33", x"3B", x"1E", x"38", x"00"), -- U+0051 (Q)
( x"3F", x"66", x"66", x"3E", x"36", x"66", x"67", x"00"), -- U+0052 (R)
( x"1E", x"33", x"07", x"0E", x"38", x"33", x"1E", x"00"), -- U+0053 (S)
( x"3F", x"2D", x"0C", x"0C", x"0C", x"0C", x"1E", x"00"), -- U+0054 (T)
( x"33", x"33", x"33", x"33", x"33", x"33", x"3F", x"00"), -- U+0055 (U)
( x"33", x"33", x"33", x"33", x"33", x"1E", x"0C", x"00"), -- U+0056 (V)
( x"63", x"63", x"63", x"6B", x"7F", x"77", x"63", x"00"), -- U+0057 (W)
( x"63", x"63", x"36", x"1C", x"1C", x"36", x"63", x"00"), -- U+0058 (X)
( x"33", x"33", x"33", x"1E", x"0C", x"0C", x"1E", x"00"), -- U+0059 (Y)
( x"7F", x"63", x"31", x"18", x"4C", x"66", x"7F", x"00"), -- U+005A (Z)
( x"1E", x"06", x"06", x"06", x"06", x"06", x"1E", x"00"), -- U+005B ([)
( x"03", x"06", x"0C", x"18", x"30", x"60", x"40", x"00"), -- U+005C (\)
( x"1E", x"18", x"18", x"18", x"18", x"18", x"1E", x"00"), -- U+005D (])
( x"08", x"1C", x"36", x"63", x"00", x"00", x"00", x"00"), -- U+005E (^)
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"FF"), -- U+005F (_)
( x"0C", x"0C", x"18", x"00", x"00", x"00", x"00", x"00"), -- U+0060 (`)
( x"00", x"00", x"1E", x"30", x"3E", x"33", x"6E", x"00"), -- U+0061 (a)
( x"07", x"06", x"06", x"3E", x"66", x"66", x"3B", x"00"), -- U+0062 (b)
( x"00", x"00", x"1E", x"33", x"03", x"33", x"1E", x"00"), -- U+0063 (c)
( x"38", x"30", x"30", x"3e", x"33", x"33", x"6E", x"00"), -- U+0064 (d)
( x"00", x"00", x"1E", x"33", x"3f", x"03", x"1E", x"00"), -- U+0065 (e)
( x"1C", x"36", x"06", x"0f", x"06", x"06", x"0F", x"00"), -- U+0066 (f)
( x"00", x"00", x"6E", x"33", x"33", x"3E", x"30", x"1F"), -- U+0067 (g)
( x"07", x"06", x"36", x"6E", x"66", x"66", x"67", x"00"), -- U+0068 (h)
( x"0C", x"00", x"0E", x"0C", x"0C", x"0C", x"1E", x"00"), -- U+0069 (i)
( x"30", x"00", x"30", x"30", x"30", x"33", x"33", x"1E"), -- U+006A (j)
( x"07", x"06", x"66", x"36", x"1E", x"36", x"67", x"00"), -- U+006B (k)
( x"0E", x"0C", x"0C", x"0C", x"0C", x"0C", x"1E", x"00"), -- U+006C (l)
( x"00", x"00", x"33", x"7F", x"7F", x"6B", x"63", x"00"), -- U+006D (m)
( x"00", x"00", x"1F", x"33", x"33", x"33", x"33", x"00"), -- U+006E (n)
( x"00", x"00", x"1E", x"33", x"33", x"33", x"1E", x"00"), -- U+006F (o)
( x"00", x"00", x"3B", x"66", x"66", x"3E", x"06", x"0F"), -- U+0070 (p)
( x"00", x"00", x"6E", x"33", x"33", x"3E", x"30", x"78"), -- U+0071 (q)
( x"00", x"00", x"3B", x"6E", x"66", x"06", x"0F", x"00"), -- U+0072 (r)
( x"00", x"00", x"3E", x"03", x"1E", x"30", x"1F", x"00"), -- U+0073 (s)
( x"08", x"0C", x"3E", x"0C", x"0C", x"2C", x"18", x"00"), -- U+0074 (t)
( x"00", x"00", x"33", x"33", x"33", x"33", x"6E", x"00"), -- U+0075 (u)
( x"00", x"00", x"33", x"33", x"33", x"1E", x"0C", x"00"), -- U+0076 (v)
( x"00", x"00", x"63", x"6B", x"7F", x"7F", x"36", x"00"), -- U+0077 (w)
( x"00", x"00", x"63", x"36", x"1C", x"36", x"63", x"00"), -- U+0078 (x)
( x"00", x"00", x"33", x"33", x"33", x"3E", x"30", x"1F"), -- U+0079 (y)
( x"00", x"00", x"3F", x"19", x"0C", x"26", x"3F", x"00"), -- U+007A (z)
( x"38", x"0C", x"0C", x"07", x"0C", x"0C", x"38", x"00"), -- U+007B (()
( x"18", x"18", x"18", x"00", x"18", x"18", x"18", x"00"), -- U+007C (|)
( x"07", x"0C", x"0C", x"38", x"0C", x"0C", x"07", x"00"), -- U+007D ())
( x"6E", x"3B", x"00", x"00", x"00", x"00", x"00", x"00"), -- U+007E (~)
( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00") -- U+007F
);
begin
Font <= FontMemory(CodeASCII);
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.06.2021 09:20:00
-- Design Name:
-- Module Name: VGAControler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGAControler is
Generic ( HEIGHT : Natural;
WIDTH : Natural;
X_PulseWidth : Natural;
X_FrontPorch : Natural;
X_BackPorch : Natural;
Y_PulseWidth : Natural;
Y_FrontPorch : Natural;
Y_BackPorch : Natural
);
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
X : out Natural;
Y : out Natural;
PIXEL_ON : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC);
end VGAControler;
architecture Behavioral of VGAControler is
component Compteur is
Generic (Min : Natural;
Max : Natural
);
Port (CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out Natural;
Carry : out STD_LOGIC);
end component;
signal X_pos : Natural := 0;
signal Y_pos : Natural := 0;
signal Y_CLK : STD_LOGIC := '0';
signal Screen_CLK : STD_LOGIC := '0';
signal active : BOOLEAN := false;
begin
X_Compteur : Compteur
generic map (Min => 0,
Max => WIDTH + X_PulseWidth + X_FrontPorch + X_BackPorch - 1)
port map (CLK => CLK,
RST => RST,
Value => X_pos,
Carry => Y_CLK);
Y_Compteur : Compteur
generic map (Min => 0,
Max => HEIGHT + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1)
port map (CLK => Y_CLK,
RST => RST,
Value => Y_pos,
Carry => Screen_CLK);
active <= ((X_pos < WIDTH) and (Y_pos < HEIGHT));
VGA_RED <= "0000" when (RST = '0') else
"1000" when ((PIXEL_ON = '0') or (not active)) else
"1111";
VGA_BLUE <= "0000" when (RST = '0') else
"1000" when ((PIXEL_ON = '0') or (not active)) else
"1111";
VGA_GREEN <= "0000" when (RST = '0') else
"1000" when ((PIXEL_ON = '0') or (not active)) else
"1111";
VGA_HS <= '0' when ((RST = '0') or (X_pos < WIDTH + X_FrontPorch) or (X_pos >= WIDTH + X_FrontPorch + X_PulseWidth)) else
'1';
VGA_VS <= '0' when ((RST = '0') or (Y_pos < HEIGHT + Y_FrontPorch) or (Y_pos >= HEIGHT + Y_FrontPorch + Y_PulseWidth)) else
'1';
X <= X_pos;
Y <= Y_pos;
end Behavioral;

107
Processeur.srcs/sources_1/new/clk_wiz_0.vhd Normal file
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@ -0,0 +1,107 @@
-- file: clk_wiz_0.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_0 is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic
);
end clk_wiz_0;
architecture xilinx of clk_wiz_0 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_wiz_0_clk_wiz
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic
);
end component;
begin
U0: clk_wiz_0_clk_wiz
port map (
-- Clock in ports
clk_in1 => clk_in1,
-- Clock out ports
clk_out1 => clk_out1
);
end xilinx;

201
Processeur.srcs/sources_1/new/clk_wiz_0_clk_wiz.vhd Normal file
View file

@ -0,0 +1,201 @@
-- file: clk_wiz_0_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_0_clk_wiz is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic
);
end clk_wiz_0_clk_wiz;
architecture xilinx of clk_wiz_0_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_in1_clk_wiz_0 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_wiz_0 : std_logic;
signal clkfbout_buf_clk_wiz_0 : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_out1_clk_wiz_0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clk_in1_clk_wiz_0 <= clk_in1;
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.125,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 9.375,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_wiz_0,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_wiz_0,
CLKIN1 => clk_in1_clk_wiz_0,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_wiz_0,
I => clkfbout_clk_wiz_0);
clkout1_buf : BUFG
port map
(O => clk_out1,
I => clk_out1_clk_wiz_0);
end xilinx;

11
Processeur.srcs/sources_1/new/font.vhd Normal file
View file

@ -0,0 +1,11 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package font is
constant font_width : natural := 8;
constant font_height : natural := 8;
type font_T is array (0 to font_height - 1, 0 to font_width - 1) of STD_LOGIC;
end package;

162
Processeur.xpr
View file

@ -32,20 +32,20 @@
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/> <Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="16"/> <Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="339"/> <Option Name="WTXSimLaunchSim" Val="420"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/> <Option Name="WTXSimExportSim" Val="2"/>
<Option Name="WTModelSimExportSim" Val="0"/> <Option Name="WTModelSimExportSim" Val="2"/>
<Option Name="WTQuestaExportSim" Val="0"/> <Option Name="WTQuestaExportSim" Val="2"/>
<Option Name="WTIesExportSim" Val="0"/> <Option Name="WTIesExportSim" Val="2"/>
<Option Name="WTVcsExportSim" Val="0"/> <Option Name="WTVcsExportSim" Val="2"/>
<Option Name="WTRivieraExportSim" Val="0"/> <Option Name="WTRivieraExportSim" Val="2"/>
<Option Name="WTActivehdlExportSim" Val="0"/> <Option Name="WTActivehdlExportSim" Val="2"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/> <Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/> <Option Name="XSimTimeUnit" Val="ns"/>
@ -61,12 +61,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/System.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/BancRegistres.vhd"> <File Path="$PSRCDIR/sources_1/new/BancRegistres.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@ -103,6 +97,18 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd"> <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@ -115,43 +121,85 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd"> <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Pipeline_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd"> <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd"> <File Path="$PSRCDIR/sources_1/new/Pipeline_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/clk_wiz_0_clk_wiz.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/clk_wiz_0.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/VGAControler.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/font.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/TableASCII.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Ecran.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/System.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="simulation"/>
<Attr Name="UsedIn" Val="synthesis"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ScreenSystem.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
@ -159,8 +207,7 @@
</File> </File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="System"/> <Option Name="TopModule" Val="ScreenSystem"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
@ -256,12 +303,37 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sim_1/new/Test_Ecran.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_VGAControler.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_ScreenSystem.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TestTableASCII.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Test_Pipeline"/> <Option Name="TopModule" Val="TestTableASCII"/>
<Option Name="TopLib" Val="xil_defaultlib"/> <Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/>
<Option Name="SimMode" Val="post-implementation"/>
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
@ -292,15 +364,14 @@
</Simulator> </Simulator>
</Simulators> </Simulators>
<Runs Version="1" Minor="10"> <Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/> <Step Id="init_design"/>
@ -313,7 +384,6 @@
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/> <Step Id="write_bitstream"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run> </Run>
</Runs> </Runs>