foussats/projet_systeme
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

Tests processeur OK

Browse source
This commit is contained in:
Foussats Morgane 2021-05-11 16:36:35 +02:00
parent c06ce09028
commit 9b69ceadef
41 changed files with 809 additions and 286 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
xilinx/ALU/ALU.gise
View file

@ -49,9 +49,13 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620641821"> <transform xil_pn:end_ts="1620740667" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620740667">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="alu.vhd"/> <outfile xil_pn:name="alu.vhd"/>
<outfile xil_pn:name="alu_test.vhd"/> <outfile xil_pn:name="alu_test.vhd"/>
<outfile xil_pn:name="bm.vhd"/> <outfile xil_pn:name="bm.vhd"/>
@ -76,9 +80,14 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620641821"> <transform xil_pn:end_ts="1620740667" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620740667">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="alu.vhd"/> <outfile xil_pn:name="alu.vhd"/>
<outfile xil_pn:name="alu_test.vhd"/> <outfile xil_pn:name="alu_test.vhd"/>
<outfile xil_pn:name="bm.vhd"/> <outfile xil_pn:name="bm.vhd"/>
@ -91,9 +100,15 @@
<outfile xil_pn:name="process_test.vhd"/> <outfile xil_pn:name="process_test.vhd"/>
<outfile xil_pn:name="processeur.vhd"/> <outfile xil_pn:name="processeur.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1620641822" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1620641821"> <transform xil_pn:end_ts="1620740670" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1620740667">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/> <outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/> <outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/> <outfile xil_pn:name="isim.log"/>
@ -101,9 +116,13 @@
<outfile xil_pn:name="process_test_isim_beh.exe"/> <outfile xil_pn:name="process_test_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/> <outfile xil_pn:name="xilinxsim.ini"/>
</transform> </transform>
<transform xil_pn:end_ts="1620641823" xil_pn:in_ck="482655878171119177" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1620641822"> <transform xil_pn:end_ts="1620740670" xil_pn:in_ck="482655878171119177" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1620740670">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/> <outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/> <outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="process_test_isim_beh.wdb"/> <outfile xil_pn:name="process_test_isim_beh.wdb"/>

6
xilinx/ALU/ALU.xise
View file

@ -311,8 +311,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/process_test" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/process_test/uut/data_memory" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.process_test" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.bm_data" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -330,7 +330,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.process_test" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.bm_data" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>

2
xilinx/ALU/_xmsgs/pn_parser.xmsgs
View file

@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd&quot; into library work</arg>
</msg> </msg>
</messages> </messages>

14
xilinx/ALU/bm_instr.vhd
View file

@ -37,9 +37,21 @@ type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
--signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000"); --signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
--test afc cop --test afc cop
signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000"); --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
--test add --test add
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000"); --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
--test sub
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000011000000110000000100000010", others =>"00000000000000000000000000000000");
--test mul
signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000010000000110000000100000010", others =>"00000000000000000000000000000000");
--test store
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
--test load
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", 15 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000");
begin begin
OUT_data <= instr_memory(to_integer(unsigned(IN_addr))); OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));

12
xilinx/ALU/fuse.log
View file

@ -1,7 +1,7 @@
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test" Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test"
ISim O.87xd (signature 0x8ddf5b5d) ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 12 Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 24 Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files Determining compilation order of HDL files
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work
@ -13,7 +13,7 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU
Starting static elaboration Starting static elaboration
Completed static elaboration Completed static elaboration
Fuse Memory Usage: 98520 KB Fuse Memory Usage: 98520 KB
Fuse CPU Usage: 760 ms Fuse CPU Usage: 880 ms
Compiling package standard Compiling package standard
Compiling package std_logic_1164 Compiling package std_logic_1164
Compiling package std_logic_arith Compiling package std_logic_arith
@ -30,6 +30,6 @@ Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish... Waiting for 1 sub-compilation(s) to finish...
Compiled 18 VHDL Units Compiled 18 VHDL Units
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe
Fuse Memory Usage: 1723208 KB Fuse Memory Usage: 1198916 KB
Fuse CPU Usage: 850 ms Fuse CPU Usage: 1010 ms
GCC CPU Usage: 120 ms GCC CPU Usage: 140 ms

45
xilinx/ALU/iseconfig/ALU.projectmgr
View file

@ -9,13 +9,13 @@
<ClosedNodesVersion>2</ClosedNodesVersion> <ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem> <SelectedItem>addr_instructions - bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001c5000000020000000000000000000000000200000064ffffffff000000810000000300000002000001c50000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem> <CurrentItem>addr_instructions - bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</CurrentItem>
</ItemView> </ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes> <ClosedNodes>
@ -23,13 +23,13 @@
<ClosedNode>Design Utilities</ClosedNode> <ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem></SelectedItem> <SelectedItem/>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem> <CurrentItem/>
</ItemView> </ItemView>
<ItemView guiview="File" > <ItemView guiview="File" >
<ClosedNodes> <ClosedNodes>
@ -50,7 +50,7 @@
<SelectedItems/> <SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000148000000010001000100000000000000000000000064ffffffff000000810000000000000001000001480000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000132000000010001000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem> <CurrentItem>work</CurrentItem>
</ItemView> </ItemView>
@ -79,17 +79,31 @@
<ClosedNode>/bm_data_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_data_test.vhd</ClosedNode> <ClosedNode>/bm_data_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_data_test.vhd</ClosedNode>
<ClosedNode>/bm_instr_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_instr_test.vhd</ClosedNode> <ClosedNode>/bm_instr_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_instr_test.vhd</ClosedNode>
<ClosedNode>/br_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|br_test.vhd</ClosedNode> <ClosedNode>/br_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|br_test.vhd</ClosedNode>
<ClosedNode>/processeur - Behavioral |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|processeur.vhd</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem> <SelectedItem>data_memory - bm_data - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd)</SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001d9000000020000000000000000000000000200000064ffffffff000000810000000300000002000001d90000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem> <CurrentItem>data_memory - bm_data - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd)</CurrentItem>
</ItemView> </ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" > <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes> <ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion> <ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes> </ClosedNodes>
@ -102,19 +116,6 @@
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem> <CurrentItem></CurrentItem>
</ItemView> </ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Simulate Behavioral Model</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes> <ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion> <ClosedNodesVersion>1</ClosedNodesVersion>

4
xilinx/ALU/iseconfig/processeur.xreport
View file

@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2021-05-10T10:47:06</DateModified> <DateModified>2021-05-11T15:38:05</DateModified>
<ModuleName>processeur</ModuleName> <ModuleName>processeur</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp> <SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath> <SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU</ImplementationReportsDirectory> <ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/</ImplementationReportsDirectory>
<DateInitialized>2021-05-10T09:34:56</DateInitialized> <DateInitialized>2021-05-10T09:34:56</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering> <EnableMessageFiltering>false</EnableMessageFiltering>
</header> </header>

127
xilinx/ALU/isim.log
View file

@ -45,4 +45,129 @@ at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_IN
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
# exit 0 ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

13
xilinx/ALU/isim/isim_usage_statistics.html
View file

@ -2,15 +2,4 @@
<xtag-section name="ISimStatistics"> <xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>850 ms, 1723208 KB</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1010 ms, 1198916 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>109</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10695</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>14</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>31</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.04 sec, 264146 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>
</TABLE>

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
View file

Binary file not shown.

25
xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log
View file

@ -2,28 +2,9 @@ Command line:
process_test_isim_beh.exe process_test_isim_beh.exe
-simmode gui -simmode gui
-simrunnum 0 -simrunnum 0
-socket 43981 -socket 54129
Mon May 10 12:31:07 2021 Tue May 11 16:30:48 2021
Elaboration Time: 0.01 sec Elaboration Time: 0.02 sec
Current Memory Usage: 189.698 Meg
Total Signals : 109
Total Nets : 10695
Total Signal Drivers : 44
Total Blocks : 14
Total Primitive Blocks : 12
Total Processes : 31
Total Traceable Variables : 16
Total Scalar Nets and Variables : 11197
Total Line Count : 66
Total Simulation Time: 0.04 sec
Current Memory Usage: 265.2 Meg
Mon May 10 12:32:41 2021

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe
View file

Binary file not shown.

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1
View file

Binary file not shown.

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat
View file

Binary file not shown.

2
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c
View file

@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0)
char *t14; char *t14;
char *t15; char *t15;
LAB0: xsi_set_current_line(45, ng0); LAB0: xsi_set_current_line(57, ng0);
LAB3: t1 = (t0 + 1512U); LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1); t2 = *((char **)t1);

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o
View file

Binary file not shown.

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat
View file

Binary file not shown.

476
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c
View file

@ -298,193 +298,223 @@ LAB24: goto LAB2;
static void work_a_4150868852_3212880686_p_1(char *t0) static void work_a_4150868852_3212880686_p_1(char *t0)
{ {
char t9[16]; char t10[16];
char t18[16]; char t19[16];
char t26[16]; char t27[16];
char t34[16]; char t35[16];
char t42[16]; char t43[16];
char t51[16];
unsigned char t1; unsigned char t1;
unsigned char t2; unsigned char t2;
unsigned char t3; unsigned char t3;
unsigned char t4; unsigned char t4;
char *t5; unsigned char t5;
char *t6; char *t6;
char *t7; char *t7;
char *t10; char *t8;
char *t11; char *t11;
int t12; char *t12;
unsigned int t13; int t13;
unsigned char t14; unsigned int t14;
char *t15; unsigned char t15;
char *t16; char *t16;
char *t19; char *t17;
char *t20; char *t20;
int t21; char *t21;
unsigned char t22; int t22;
char *t23; unsigned char t23;
char *t24; char *t24;
char *t27; char *t25;
char *t28; char *t28;
int t29; char *t29;
unsigned char t30; int t30;
char *t31; unsigned char t31;
char *t32; char *t32;
char *t35; char *t33;
char *t36; char *t36;
int t37; char *t37;
unsigned char t38; int t38;
char *t39; unsigned char t39;
char *t40; char *t40;
char *t43; char *t41;
char *t44; char *t44;
int t45; char *t45;
unsigned char t46; int t46;
char *t47; unsigned char t47;
char *t48; char *t48;
char *t49; char *t49;
char *t50;
char *t51;
char *t52; char *t52;
char *t53; char *t53;
char *t54; int t54;
char *t55; unsigned char t55;
char *t56; char *t56;
char *t57; char *t57;
char *t58; char *t58;
char *t59;
char *t60;
char *t61;
char *t62;
char *t63;
char *t64;
char *t65;
char *t66;
char *t67;
LAB0: xsi_set_current_line(181, ng0); LAB0: xsi_set_current_line(181, ng0);
t5 = (t0 + 2152U); t6 = (t0 + 2152U);
t6 = *((char **)t5); t7 = *((char **)t6);
t5 = (t0 + 17640U); t6 = (t0 + 17640U);
t7 = (t0 + 18323); t8 = (t0 + 18323);
t10 = (t9 + 0U);
t11 = (t10 + 0U); t11 = (t10 + 0U);
*((int *)t11) = 0; t12 = (t11 + 0U);
t11 = (t10 + 4U); *((int *)t12) = 0;
*((int *)t11) = 7; t12 = (t11 + 4U);
t11 = (t10 + 8U); *((int *)t12) = 7;
*((int *)t11) = 1; t12 = (t11 + 8U);
t12 = (7 - 0); *((int *)t12) = 1;
t13 = (t12 * 1); t13 = (7 - 0);
t13 = (t13 + 1); t14 = (t13 * 1);
t11 = (t10 + 12U); t14 = (t14 + 1);
*((unsigned int *)t11) = t13; t12 = (t11 + 12U);
t14 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t6, t5, t7, t9); *((unsigned int *)t12) = t14;
if (t14 == 1) t15 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t7, t6, t8, t10);
if (t15 == 1)
goto LAB17;
LAB18: t12 = (t0 + 2152U);
t16 = *((char **)t12);
t12 = (t0 + 17640U);
t17 = (t0 + 18331);
t20 = (t19 + 0U);
t21 = (t20 + 0U);
*((int *)t21) = 0;
t21 = (t20 + 4U);
*((int *)t21) = 7;
t21 = (t20 + 8U);
*((int *)t21) = 1;
t22 = (7 - 0);
t14 = (t22 * 1);
t14 = (t14 + 1);
t21 = (t20 + 12U);
*((unsigned int *)t21) = t14;
t23 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t16, t12, t17, t19);
t5 = t23;
LAB19: if (t5 == 1)
goto LAB14; goto LAB14;
LAB15: t11 = (t0 + 2152U); LAB15: t21 = (t0 + 2152U);
t15 = *((char **)t11); t24 = *((char **)t21);
t11 = (t0 + 17640U); t21 = (t0 + 17640U);
t16 = (t0 + 18331); t25 = (t0 + 18339);
t19 = (t18 + 0U); t28 = (t27 + 0U);
t20 = (t19 + 0U); t29 = (t28 + 0U);
*((int *)t20) = 0; *((int *)t29) = 0;
t20 = (t19 + 4U); t29 = (t28 + 4U);
*((int *)t20) = 7; *((int *)t29) = 7;
t20 = (t19 + 8U); t29 = (t28 + 8U);
*((int *)t20) = 1; *((int *)t29) = 1;
t21 = (7 - 0); t30 = (7 - 0);
t13 = (t21 * 1); t14 = (t30 * 1);
t13 = (t13 + 1); t14 = (t14 + 1);
t20 = (t19 + 12U); t29 = (t28 + 12U);
*((unsigned int *)t20) = t13; *((unsigned int *)t29) = t14;
t22 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t15, t11, t16, t18); t31 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t24, t21, t25, t27);
t4 = t22; t4 = t31;
LAB16: if (t4 == 1) LAB16: if (t4 == 1)
goto LAB11; goto LAB11;
LAB12: t20 = (t0 + 2152U); LAB12: t29 = (t0 + 2152U);
t23 = *((char **)t20); t32 = *((char **)t29);
t20 = (t0 + 17640U); t29 = (t0 + 17640U);
t24 = (t0 + 18339); t33 = (t0 + 18347);
t27 = (t26 + 0U); t36 = (t35 + 0U);
t28 = (t27 + 0U); t37 = (t36 + 0U);
*((int *)t28) = 0; *((int *)t37) = 0;
t28 = (t27 + 4U); t37 = (t36 + 4U);
*((int *)t28) = 7; *((int *)t37) = 7;
t28 = (t27 + 8U); t37 = (t36 + 8U);
*((int *)t28) = 1; *((int *)t37) = 1;
t29 = (7 - 0); t38 = (7 - 0);
t13 = (t29 * 1); t14 = (t38 * 1);
t13 = (t13 + 1); t14 = (t14 + 1);
t28 = (t27 + 12U); t37 = (t36 + 12U);
*((unsigned int *)t28) = t13; *((unsigned int *)t37) = t14;
t30 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t23, t20, t24, t26); t39 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t32, t29, t33, t35);
t3 = t30; t3 = t39;
LAB13: if (t3 == 1) LAB13: if (t3 == 1)
goto LAB8; goto LAB8;
LAB9: t28 = (t0 + 2152U); LAB9: t37 = (t0 + 2152U);
t31 = *((char **)t28); t40 = *((char **)t37);
t28 = (t0 + 17640U); t37 = (t0 + 17640U);
t32 = (t0 + 18347); t41 = (t0 + 18355);
t35 = (t34 + 0U); t44 = (t43 + 0U);
t36 = (t35 + 0U); t45 = (t44 + 0U);
*((int *)t36) = 0; *((int *)t45) = 0;
t36 = (t35 + 4U); t45 = (t44 + 4U);
*((int *)t36) = 7; *((int *)t45) = 7;
t36 = (t35 + 8U); t45 = (t44 + 8U);
*((int *)t36) = 1; *((int *)t45) = 1;
t37 = (7 - 0); t46 = (7 - 0);
t13 = (t37 * 1); t14 = (t46 * 1);
t13 = (t13 + 1); t14 = (t14 + 1);
t36 = (t35 + 12U); t45 = (t44 + 12U);
*((unsigned int *)t36) = t13; *((unsigned int *)t45) = t14;
t38 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t31, t28, t32, t34); t47 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t40, t37, t41, t43);
t2 = t38; t2 = t47;
LAB10: if (t2 == 1) LAB10: if (t2 == 1)
goto LAB5; goto LAB5;
LAB6: t36 = (t0 + 2152U); LAB6: t45 = (t0 + 2152U);
t39 = *((char **)t36); t48 = *((char **)t45);
t36 = (t0 + 17640U); t45 = (t0 + 17640U);
t40 = (t0 + 18355); t49 = (t0 + 18363);
t43 = (t42 + 0U); t52 = (t51 + 0U);
t44 = (t43 + 0U); t53 = (t52 + 0U);
*((int *)t44) = 0; *((int *)t53) = 0;
t44 = (t43 + 4U); t53 = (t52 + 4U);
*((int *)t44) = 7; *((int *)t53) = 7;
t44 = (t43 + 8U); t53 = (t52 + 8U);
*((int *)t44) = 1; *((int *)t53) = 1;
t45 = (7 - 0); t54 = (7 - 0);
t13 = (t45 * 1); t14 = (t54 * 1);
t13 = (t13 + 1); t14 = (t14 + 1);
t44 = (t43 + 12U); t53 = (t52 + 12U);
*((unsigned int *)t44) = t13; *((unsigned int *)t53) = t14;
t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t39, t36, t40, t42); t55 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t48, t45, t49, t51);
t1 = t46; t1 = t55;
LAB7: if (t1 != 0) LAB7: if (t1 != 0)
goto LAB3; goto LAB3;
LAB4: LAB4:
LAB17: t52 = (t0 + 2472U); LAB20: t61 = (t0 + 2472U);
t53 = *((char **)t52); t62 = *((char **)t61);
t52 = (t0 + 10360); t61 = (t0 + 10360);
t54 = (t52 + 56U); t63 = (t61 + 56U);
t55 = *((char **)t54); t64 = *((char **)t63);
t56 = (t55 + 56U); t65 = (t64 + 56U);
t57 = *((char **)t56); t66 = *((char **)t65);
memcpy(t57, t53, 8U); memcpy(t66, t62, 8U);
xsi_driver_first_trans_fast(t52); xsi_driver_first_trans_fast(t61);
LAB2: t58 = (t0 + 10104); LAB2: t67 = (t0 + 10104);
*((int *)t58) = 1; *((int *)t67) = 1;
LAB1: return; LAB1: return;
LAB3: t44 = (t0 + 1512U); LAB3: t53 = (t0 + 1512U);
t47 = *((char **)t44); t56 = *((char **)t53);
t44 = (t0 + 10360); t53 = (t0 + 10360);
t48 = (t44 + 56U); t57 = (t53 + 56U);
t49 = *((char **)t48); t58 = *((char **)t57);
t50 = (t49 + 56U); t59 = (t58 + 56U);
t51 = *((char **)t50); t60 = *((char **)t59);
memcpy(t51, t47, 8U); memcpy(t60, t56, 8U);
xsi_driver_first_trans_fast(t44); xsi_driver_first_trans_fast(t53);
goto LAB2; goto LAB2;
LAB5: t1 = (unsigned char)1; LAB5: t1 = (unsigned char)1;
@ -499,7 +529,10 @@ LAB11: t3 = (unsigned char)1;
LAB14: t4 = (unsigned char)1; LAB14: t4 = (unsigned char)1;
goto LAB16; goto LAB16;
LAB18: goto LAB2; LAB17: t5 = (unsigned char)1;
goto LAB19;
LAB21: goto LAB2;
} }
@ -557,7 +590,7 @@ LAB0: xsi_set_current_line(197, ng0);
t1 = (t0 + 2792U); t1 = (t0 + 2792U);
t2 = *((char **)t1); t2 = *((char **)t1);
t1 = (t0 + 17704U); t1 = (t0 + 17704U);
t3 = (t0 + 18363); t3 = (t0 + 18371);
t6 = (t5 + 0U); t6 = (t5 + 0U);
t7 = (t6 + 0U); t7 = (t6 + 0U);
*((int *)t7) = 0; *((int *)t7) = 0;
@ -577,7 +610,7 @@ LAB0: xsi_set_current_line(197, ng0);
LAB4: t17 = (t0 + 2792U); LAB4: t17 = (t0 + 2792U);
t18 = *((char **)t17); t18 = *((char **)t17);
t17 = (t0 + 17704U); t17 = (t0 + 17704U);
t19 = (t0 + 18374); t19 = (t0 + 18382);
t22 = (t21 + 0U); t22 = (t21 + 0U);
t23 = (t22 + 0U); t23 = (t22 + 0U);
*((int *)t23) = 0; *((int *)t23) = 0;
@ -597,7 +630,7 @@ LAB4: t17 = (t0 + 2792U);
LAB6: t32 = (t0 + 2792U); LAB6: t32 = (t0 + 2792U);
t33 = *((char **)t32); t33 = *((char **)t32);
t32 = (t0 + 17704U); t32 = (t0 + 17704U);
t34 = (t0 + 18385); t34 = (t0 + 18393);
t37 = (t36 + 0U); t37 = (t36 + 0U);
t38 = (t37 + 0U); t38 = (t37 + 0U);
*((int *)t38) = 0; *((int *)t38) = 0;
@ -615,7 +648,7 @@ LAB6: t32 = (t0 + 2792U);
goto LAB7; goto LAB7;
LAB8: LAB8:
LAB9: t47 = (t0 + 18396); LAB9: t47 = (t0 + 18404);
t49 = (t0 + 10424); t49 = (t0 + 10424);
t50 = (t49 + 56U); t50 = (t49 + 56U);
t51 = *((char **)t50); t51 = *((char **)t50);
@ -628,7 +661,7 @@ LAB2: t54 = (t0 + 10120);
*((int *)t54) = 1; *((int *)t54) = 1;
LAB1: return; LAB1: return;
LAB3: t7 = (t0 + 18371); LAB3: t7 = (t0 + 18379);
t12 = (t0 + 10424); t12 = (t0 + 10424);
t13 = (t12 + 56U); t13 = (t12 + 56U);
t14 = *((char **)t13); t14 = *((char **)t13);
@ -638,7 +671,7 @@ LAB3: t7 = (t0 + 18371);
xsi_driver_first_trans_fast(t12); xsi_driver_first_trans_fast(t12);
goto LAB2; goto LAB2;
LAB5: t23 = (t0 + 18382); LAB5: t23 = (t0 + 18390);
t27 = (t0 + 10424); t27 = (t0 + 10424);
t28 = (t27 + 56U); t28 = (t27 + 56U);
t29 = *((char **)t28); t29 = *((char **)t28);
@ -648,7 +681,7 @@ LAB5: t23 = (t0 + 18382);
xsi_driver_first_trans_fast(t27); xsi_driver_first_trans_fast(t27);
goto LAB2; goto LAB2;
LAB7: t38 = (t0 + 18393); LAB7: t38 = (t0 + 18401);
t42 = (t0 + 10424); t42 = (t0 + 10424);
t43 = (t42 + 56U); t43 = (t42 + 56U);
t44 = *((char **)t43); t44 = *((char **)t43);
@ -706,7 +739,7 @@ LAB0: xsi_set_current_line(214, ng0);
t3 = (t0 + 2792U); t3 = (t0 + 2792U);
t4 = *((char **)t3); t4 = *((char **)t3);
t3 = (t0 + 17704U); t3 = (t0 + 17704U);
t5 = (t0 + 18399); t5 = (t0 + 18407);
t8 = (t7 + 0U); t8 = (t7 + 0U);
t9 = (t8 + 0U); t9 = (t8 + 0U);
*((int *)t9) = 0; *((int *)t9) = 0;
@ -726,7 +759,7 @@ LAB0: xsi_set_current_line(214, ng0);
LAB9: t9 = (t0 + 2792U); LAB9: t9 = (t0 + 2792U);
t13 = *((char **)t9); t13 = *((char **)t9);
t9 = (t0 + 17704U); t9 = (t0 + 17704U);
t14 = (t0 + 18407); t14 = (t0 + 18415);
t17 = (t16 + 0U); t17 = (t16 + 0U);
t18 = (t17 + 0U); t18 = (t17 + 0U);
*((int *)t18) = 0; *((int *)t18) = 0;
@ -748,7 +781,7 @@ LAB10: if (t2 == 1)
LAB6: t18 = (t0 + 2792U); LAB6: t18 = (t0 + 2792U);
t21 = *((char **)t18); t21 = *((char **)t18);
t18 = (t0 + 17704U); t18 = (t0 + 17704U);
t22 = (t0 + 18415); t22 = (t0 + 18423);
t25 = (t24 + 0U); t25 = (t24 + 0U);
t26 = (t25 + 0U); t26 = (t25 + 0U);
*((int *)t26) = 0; *((int *)t26) = 0;
@ -829,7 +862,7 @@ LAB0: xsi_set_current_line(231, ng0);
t1 = (t0 + 4392U); t1 = (t0 + 4392U);
t2 = *((char **)t1); t2 = *((char **)t1);
t1 = (t0 + 17800U); t1 = (t0 + 17800U);
t3 = (t0 + 18423); t3 = (t0 + 18431);
t6 = (t5 + 0U); t6 = (t5 + 0U);
t7 = (t6 + 0U); t7 = (t6 + 0U);
*((int *)t7) = 0; *((int *)t7) = 0;
@ -900,7 +933,7 @@ LAB0: xsi_set_current_line(233, ng0);
t1 = (t0 + 4392U); t1 = (t0 + 4392U);
t2 = *((char **)t1); t2 = *((char **)t1);
t1 = (t0 + 17800U); t1 = (t0 + 17800U);
t3 = (t0 + 18431); t3 = (t0 + 18439);
t6 = (t5 + 0U); t6 = (t5 + 0U);
t7 = (t6 + 0U); t7 = (t6 + 0U);
*((int *)t7) = 0; *((int *)t7) = 0;
@ -969,7 +1002,7 @@ LAB0: xsi_set_current_line(235, ng0);
t1 = (t0 + 4392U); t1 = (t0 + 4392U);
t2 = *((char **)t1); t2 = *((char **)t1);
t1 = (t0 + 17800U); t1 = (t0 + 17800U);
t3 = (t0 + 18439); t3 = (t0 + 18447);
t6 = (t5 + 0U); t6 = (t5 + 0U);
t7 = (t6 + 0U); t7 = (t6 + 0U);
*((int *)t7) = 0; *((int *)t7) = 0;
@ -1006,76 +1039,109 @@ LAB3: t7 = (t0 + 4232U);
static void work_a_4150868852_3212880686_p_7(char *t0) static void work_a_4150868852_3212880686_p_7(char *t0)
{ {
char t5[16]; char t6[16];
char *t1; char t15[16];
unsigned char t1;
char *t2; char *t2;
char *t3; char *t3;
char *t6; char *t4;
char *t7; char *t7;
int t8; char *t8;
unsigned int t9; int t9;
unsigned char t10; unsigned int t10;
char *t11; unsigned char t11;
char *t12; char *t12;
char *t13; char *t13;
char *t14;
char *t15;
char *t16; char *t16;
char *t17; char *t17;
char *t18; int t18;
char *t19; unsigned char t19;
char *t20; char *t20;
char *t21; char *t21;
char *t22; char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
char *t31;
LAB0: xsi_set_current_line(236, ng0); LAB0: xsi_set_current_line(236, ng0);
t1 = (t0 + 4392U); t2 = (t0 + 4392U);
t2 = *((char **)t1); t3 = *((char **)t2);
t1 = (t0 + 17800U); t2 = (t0 + 17800U);
t3 = (t0 + 18447); t4 = (t0 + 18455);
t6 = (t5 + 0U);
t7 = (t6 + 0U); t7 = (t6 + 0U);
*((int *)t7) = 0; t8 = (t7 + 0U);
t7 = (t6 + 4U); *((int *)t8) = 0;
*((int *)t7) = 7; t8 = (t7 + 4U);
t7 = (t6 + 8U); *((int *)t8) = 7;
*((int *)t7) = 1; t8 = (t7 + 8U);
t8 = (7 - 0); *((int *)t8) = 1;
t9 = (t8 * 1); t9 = (7 - 0);
t9 = (t9 + 1); t10 = (t9 * 1);
t7 = (t6 + 12U); t10 = (t10 + 1);
*((unsigned int *)t7) = t9; t8 = (t7 + 12U);
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); *((unsigned int *)t8) = t10;
if (t10 != 0) t11 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t3, t2, t4, t6);
if (t11 == 1)
goto LAB5;
LAB6: t8 = (t0 + 4392U);
t12 = *((char **)t8);
t8 = (t0 + 17800U);
t13 = (t0 + 18463);
t16 = (t15 + 0U);
t17 = (t16 + 0U);
*((int *)t17) = 0;
t17 = (t16 + 4U);
*((int *)t17) = 7;
t17 = (t16 + 8U);
*((int *)t17) = 1;
t18 = (7 - 0);
t10 = (t18 * 1);
t10 = (t10 + 1);
t17 = (t16 + 12U);
*((unsigned int *)t17) = t10;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t12, t8, t13, t15);
t1 = t19;
LAB7: if (t1 != 0)
goto LAB3; goto LAB3;
LAB4: LAB4:
LAB5: t16 = (t0 + 4232U); LAB8: t25 = (t0 + 4232U);
t17 = *((char **)t16); t26 = *((char **)t25);
t16 = (t0 + 10744); t25 = (t0 + 10744);
t18 = (t16 + 56U); t27 = (t25 + 56U);
t19 = *((char **)t18); t28 = *((char **)t27);
t20 = (t19 + 56U); t29 = (t28 + 56U);
t21 = *((char **)t20); t30 = *((char **)t29);
memcpy(t21, t17, 8U); memcpy(t30, t26, 8U);
xsi_driver_first_trans_fast(t16); xsi_driver_first_trans_fast(t25);
LAB2: t22 = (t0 + 10200); LAB2: t31 = (t0 + 10200);
*((int *)t22) = 1; *((int *)t31) = 1;
LAB1: return; LAB1: return;
LAB3: t7 = (t0 + 5672U); LAB3: t17 = (t0 + 5672U);
t11 = *((char **)t7); t20 = *((char **)t17);
t7 = (t0 + 10744); t17 = (t0 + 10744);
t12 = (t7 + 56U); t21 = (t17 + 56U);
t13 = *((char **)t12); t22 = *((char **)t21);
t14 = (t13 + 56U); t23 = (t22 + 56U);
t15 = *((char **)t14); t24 = *((char **)t23);
memcpy(t15, t11, 8U); memcpy(t24, t20, 8U);
xsi_driver_first_trans_fast(t7); xsi_driver_first_trans_fast(t17);
goto LAB2; goto LAB2;
LAB6: goto LAB2; LAB5: t1 = (unsigned char)1;
goto LAB7;
LAB9: goto LAB2;
} }
@ -1130,7 +1196,7 @@ LAB10: xsi_set_current_line(266, ng0);
t2 = (t0 + 1352U); t2 = (t0 + 1352U);
t3 = *((char **)t2); t3 = *((char **)t2);
t2 = (t0 + 17560U); t2 = (t0 + 17560U);
t5 = (t0 + 18463); t5 = (t0 + 18479);
t8 = (t13 + 0U); t8 = (t13 + 0U);
t9 = (t8 + 0U); t9 = (t8 + 0U);
*((int *)t9) = 0; *((int *)t9) = 0;
@ -1171,7 +1237,7 @@ LAB5: t3 = (t0 + 992U);
LAB7: goto LAB5; LAB7: goto LAB5;
LAB8: xsi_set_current_line(264, ng0); LAB8: xsi_set_current_line(264, ng0);
t2 = (t0 + 18455); t2 = (t0 + 18471);
t7 = (t0 + 10808); t7 = (t0 + 10808);
t8 = (t7 + 56U); t8 = (t7 + 56U);
t9 = *((char **)t8); t9 = *((char **)t8);

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o
View file

Binary file not shown.

BIN
xilinx/ALU/isim/work/alu.vdb
View file

Binary file not shown.

BIN
xilinx/ALU/isim/work/bm_data.vdb
View file

Binary file not shown.

BIN
xilinx/ALU/isim/work/bm_instr.vdb
View file

Binary file not shown.

BIN
xilinx/ALU/isim/work/br.vdb
View file

Binary file not shown.

BIN
xilinx/ALU/isim/work/pipeline.vdb
View file

Binary file not shown.

BIN
xilinx/ALU/isim/work/process_test.vdb
View file

Binary file not shown.

BIN
xilinx/ALU/isim/work/processeur.vdb
View file

Binary file not shown.

BIN
xilinx/ALU/process_test_isim_beh.wdb
View file

Binary file not shown.

8
xilinx/ALU/processeur.vhd
View file

@ -178,7 +178,7 @@ begin
QB => C_DIEX_IN QB => C_DIEX_IN
); );
B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ; B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" or OP_LIDI_OUT = x"08" else B_LIDI_OUT ;
-- Instantiate pipeline DI_EX -- Instantiate pipeline DI_EX
@ -233,12 +233,12 @@ begin
addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
A_EXMem_OUT; A_EXMem_OUT;
in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08"; in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08";
B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" else B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" or OP_EXMem_OUT = x"07" else
B_EXMem_OUT; B_EXMem_OUT;
-- Instantiate banc de données -- Instantiate banc de données
data_memory: bm_data PORT MAP ( data_memory: bm_data PORT MAP (
IN_addr => addr_dm_MUX, IN_addr => addr_dm_MUX,
IN_data => B_MemRE_IN, IN_data => in_dm_MUX,
RW => RW_LC, RW => RW_LC,
RST => RST, RST => RST,
CLK => CLK, CLK => CLK,
@ -249,7 +249,7 @@ begin
Mem_RE : pipeline PORT MAP ( Mem_RE : pipeline PORT MAP (
OP_IN => OP_EXMem_OUT, OP_IN => OP_EXMem_OUT,
A_IN => A_EXMem_OUT, A_IN => A_EXMem_OUT,
B_IN => B_EXMem_OUT, B_IN => B_MemRE_IN,
C_IN => x"00", C_IN => x"00",
CLK => CLK, CLK => CLK,
A_OUT => A_MemRE_OUT, A_OUT => A_MemRE_OUT,

4
xilinx/ALU/processeur_summary.html
View file

@ -72,9 +72,9 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lun. mai 10 10:45:43 2021</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>lun. mai 10 12:32:42 2021</TD></TR>
</TABLE> </TABLE>
<br><center><b>Date Generated:</b> 05/10/2021 - 10:47:06</center> <br><center><b>Date Generated:</b> 05/11/2021 - 15:38:05</center>
</BODY></HTML> </BODY></HTML>

165
xilinx/ALU/tests/test_load.wcfg Normal file
View file

@ -0,0 +1,165 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="process_test" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="37" />
<wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[31:0]</obj_property>
<obj_property name="ObjectShortName">out_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/in_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_addr[7:0]</obj_property>
<obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/in_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_data[7:0]</obj_property>
<obj_property name="ObjectShortName">in_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/rw" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rw</obj_property>
<obj_property name="ObjectShortName">rw</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[7:0]</obj_property>
<obj_property name="ObjectShortName">out_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/data_memory" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_memory[0:255]</obj_property>
<obj_property name="ObjectShortName">data_memory[0:255]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
<obj_property name="ElementShortName">registres[0:15]</obj_property>
<obj_property name="ObjectShortName">registres[0:15]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">w_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">w</obj_property>
<obj_property name="ObjectShortName">w</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data[7:0]</obj_property>
<obj_property name="ObjectShortName">data[7:0]</obj_property>
</wvobject>
</wave_config>

165
xilinx/ALU/tests/test_store.wcfg Normal file
View file

@ -0,0 +1,165 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="process_test" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="37" />
<wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[31:0]</obj_property>
<obj_property name="ObjectShortName">out_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/in_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_addr[7:0]</obj_property>
<obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/in_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_data[7:0]</obj_property>
<obj_property name="ObjectShortName">in_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/rw" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rw</obj_property>
<obj_property name="ObjectShortName">rw</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[7:0]</obj_property>
<obj_property name="ObjectShortName">out_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/data_memory" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_memory[0:255]</obj_property>
<obj_property name="ObjectShortName">data_memory[0:255]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
<obj_property name="ElementShortName">registres[0:15]</obj_property>
<obj_property name="ObjectShortName">registres[0:15]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">w_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">w</obj_property>
<obj_property name="ObjectShortName">w</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data[7:0]</obj_property>
<obj_property name="ObjectShortName">data[7:0]</obj_property>
</wvobject>
</wave_config>