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Test ALU + COP + AFC ok

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This commit is contained in:
Foussats Morgane 2021-05-10 12:34:10 +02:00
parent dfdcf2feb4
commit c06ce09028
66 changed files with 3855 additions and 246 deletions
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BIN
interpreter/interpreter
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35
xilinx/ALU/ALU.gise
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@ -34,6 +34,9 @@
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="process_test_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="process_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="process_test_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
</files>
@ -46,7 +49,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1620134567" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620134567">
<transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620641821">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="alu.vhd"/>
@ -58,13 +61,14 @@
<outfile xil_pn:name="br.vhd"/>
<outfile xil_pn:name="br_test.vhd"/>
<outfile xil_pn:name="pipeline.vhd"/>
<outfile xil_pn:name="process_test.vhd"/>
<outfile xil_pn:name="processeur.vhd"/>
</transform>
<transform xil_pn:end_ts="1620134030" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-182187785304845874" xil_pn:start_ts="1620134030">
<transform xil_pn:end_ts="1620632845" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6971558793754694324" xil_pn:start_ts="1620632845">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1620134030" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-5858825779926760884" xil_pn:start_ts="1620134030">
<transform xil_pn:end_ts="1620632845" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7480952545073688782" xil_pn:start_ts="1620632845">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
@ -72,7 +76,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1620134567" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620134567">
<transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620641821">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="alu.vhd"/>
@ -84,20 +88,25 @@
<outfile xil_pn:name="br.vhd"/>
<outfile xil_pn:name="br_test.vhd"/>
<outfile xil_pn:name="pipeline.vhd"/>
<outfile xil_pn:name="process_test.vhd"/>
<outfile xil_pn:name="processeur.vhd"/>
</transform>
<transform xil_pn:end_ts="1620134568" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6599872206167540207" xil_pn:start_ts="1620134567">
<status xil_pn:value="FailedRun"/>
<transform xil_pn:end_ts="1620641822" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1620641821">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="process_test_beh.prj"/>
<outfile xil_pn:name="process_test_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1620126600" xil_pn:in_ck="7979285750144170844" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7763494978879218253" xil_pn:start_ts="1620126600">
<status xil_pn:value="AbortedRun"/>
<transform xil_pn:end_ts="1620641823" xil_pn:in_ck="482655878171119177" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1620641822">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForced"/>
<status xil_pn:value="InputRemoved"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="process_test_isim_beh.wdb"/>
</transform>
</transforms>

14
xilinx/ALU/ALU.xise
View file

@ -63,6 +63,12 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="process_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="24"/>
</file>
</files>
<properties>
@ -305,8 +311,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/processeur" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.processeur" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/process_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.process_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -324,7 +330,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.processeur" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.process_test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -374,7 +380,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|processeur|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|process_test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="ALU" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

8
xilinx/ALU/bm_instr.vhd
View file

@ -32,8 +32,14 @@ end bm_instr;
architecture Behavioral of bm_instr is
type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
-- instruction "00000110 00000001 00000110 00000000"
--test afc
--signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
--test afc cop
signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
--test add
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
begin
OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));

46
xilinx/ALU/fuse.log
View file

@ -1,4 +1,4 @@
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_beh.prj work.processeur
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test"
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 12
Turning on mult-threading, number of parallel sub-compilation jobs: 24
@ -9,23 +9,27 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work
ERROR:HDLCompiler:32 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: <rst> is already declared in this region.
ERROR:HDLCompiler:32 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: <clk> is already declared in this region.
ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic <ip> is not declared in <bm_instr>
ERROR:HDLCompiler:432 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal <in_addr> has no actual or default value.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: <op_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: <a_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: <b_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: <c_in> is not declared.
ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic <clk> is not declared in <pipeline>
ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic <b_lidi_out> is not declared in <br>
ERROR:HDLCompiler:432 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal <a_addr> has no actual or default value.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: <op_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: <a_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: <b_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: <c_in> is not declared.
ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic <clk> is not declared in <pipeline>
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: <a> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: <b> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: <ctrl_alu> is not declared.
Sorry, too many errors..
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 98520 KB
Fuse CPU Usage: 760 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package numeric_std
Compiling architecture behavioral of entity bm_instr [bm_instr_default]
Compiling architecture behavioral of entity pipeline [pipeline_default]
Compiling architecture behavioral of entity br [br_default]
Compiling architecture behavioral of entity alu [alu_default]
Compiling architecture behavioral of entity bm_data [bm_data_default]
Compiling architecture behavioral of entity processeur [processeur_default]
Compiling architecture behavior of entity process_test
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 18 VHDL Units
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe
Fuse Memory Usage: 1723208 KB
Fuse CPU Usage: 850 ms
GCC CPU Usage: 120 ms

57
xilinx/ALU/fuse.xmsgs
View file

@ -5,62 +5,5 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="error" file="HDLCompiler" num="32" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: &lt;<arg fmt="%s" index="1">rst</arg>&gt; is already declared in this region.
</msg>
<msg type="error" file="HDLCompiler" num="32" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: &lt;<arg fmt="%s" index="1">clk</arg>&gt; is already declared in this region.
</msg>
<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic &lt;<arg fmt="%s" index="1">ip</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">bm_instr</arg>&gt;
</msg>
<msg type="error" file="HDLCompiler" num="432" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal &lt;<arg fmt="%s" index="1">in_addr</arg>&gt; has no actual or default value.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: &lt;<arg fmt="%s" index="1">op_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: &lt;<arg fmt="%s" index="1">a_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: &lt;<arg fmt="%s" index="1">b_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: &lt;<arg fmt="%s" index="1">c_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic &lt;<arg fmt="%s" index="1">clk</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">pipeline</arg>&gt;
</msg>
<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic &lt;<arg fmt="%s" index="1">b_lidi_out</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">br</arg>&gt;
</msg>
<msg type="error" file="HDLCompiler" num="432" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal &lt;<arg fmt="%s" index="1">a_addr</arg>&gt; has no actual or default value.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: &lt;<arg fmt="%s" index="1">op_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: &lt;<arg fmt="%s" index="1">a_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: &lt;<arg fmt="%s" index="1">b_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: &lt;<arg fmt="%s" index="1">c_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic &lt;<arg fmt="%s" index="1">clk</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">pipeline</arg>&gt;
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: &lt;<arg fmt="%s" index="1">a</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: &lt;<arg fmt="%s" index="1">b</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: &lt;<arg fmt="%s" index="1">ctrl_alu</arg>&gt; is not declared.
</msg>
</messages>

2
xilinx/ALU/fuseRelaunch.cmd
View file

@ -1 +1 @@
-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_beh.prj" "work.processeur"
-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test"

215
xilinx/ALU/iseconfig/processeur.xreport Normal file
View file

@ -0,0 +1,215 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2021-05-10T10:47:06</DateModified>
<ModuleName>processeur</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU</ImplementationReportsDirectory>
<DateInitialized>2021-05-10T09:34:56</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="processeur_summary.html" label="Summary" >
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<toc-item title="Performance Summary" target="Performance Summary" />
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<toc-item title="Detailed Reports" target="Detailed Reports" />
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<viewgroup label="Errors and Warnings" >
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<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
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<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
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<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
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<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="processeur.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
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<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
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<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
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<toc-item title="Performance Summary" target="Performance Summary:" />
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<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
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<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
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<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/processeur_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/processeur_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="processeur_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/processeur_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="processeur_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="processeur.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/processeur_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="processeur.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
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<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/processeur_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
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</body>
</report-views>

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xilinx/ALU/isim.log
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@ -1,5 +1,5 @@
ISim log file
Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.wdb
Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
@ -10,7 +10,13 @@ Time resolution is 1 ps
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
@ -18,5 +24,25 @@ WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
# exit 0

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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
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29
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log
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@ -1,29 +0,0 @@
Command line:
bm_instr_test_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 58939
Tue May 4 13:10:22 2021
Elaboration Time: 0.01 sec
Current Memory Usage: 187.593 Meg
Total Signals : 7
Total Nets : 8233
Total Signal Drivers : 3
Total Blocks : 6
Total Primitive Blocks : 5
Total Processes : 3
Total Traceable Variables : 16
Total Scalar Nets and Variables : 8735
Total Line Count : 11
Total Simulation Time: 0.03 sec
Current Memory Usage: 263.094 Meg
Tue May 4 13:11:03 2021

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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat
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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat
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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o
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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.lin64.o
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xilinx/ALU/isim/isim_usage_statistics.html
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<xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>840 ms, 1722812 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>850 ms, 1723208 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>7</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>8233</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>6</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>109</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10695</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>14</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>31</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 262041 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.04 sec, 264146 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>

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xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat
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xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat
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xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat
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xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat
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xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Normal file
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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimcrash.log → xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimcrash.log
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xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log Normal file
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Command line:
process_test_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 43981
Mon May 10 12:31:07 2021
Elaboration Time: 0.01 sec
Current Memory Usage: 189.698 Meg
Total Signals : 109
Total Nets : 10695
Total Signal Drivers : 44
Total Blocks : 14
Total Primitive Blocks : 12
Total Processes : 31
Total Traceable Variables : 16
Total Scalar Nets and Variables : 11197
Total Line Count : 66
Total Simulation Time: 0.04 sec
Current Memory Usage: 265.2 Meg
Mon May 10 12:32:41 2021

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xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat Normal file
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xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe Executable file
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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/tmp_save/_1 → xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1
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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd";
extern char *IEEE_P_2592010699;
extern char *IEEE_P_3620187407;
unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533613331_3965413181(char *, char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533721142_3965413181(char *, char *, char *, char *, char *, char *);
static void work_a_0832606739_3212880686_p_0(char *t0)
{
char t5[16];
char t7[16];
char *t1;
char *t3;
char *t4;
char *t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(54, ng0);
LAB3: t1 = (t0 + 11471);
t3 = (t0 + 1032U);
t4 = *((char **)t3);
t6 = ((IEEE_P_2592010699) + 4000);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
t9 = (t8 + 4U);
*((int *)t9) = 0;
t9 = (t8 + 8U);
*((int *)t9) = 1;
t10 = (0 - 0);
t11 = (t10 * 1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11224U);
t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
t11 = (1U + 8U);
t12 = (9U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 7304);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t3, 9U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 7064);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t11, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_1(char *t0)
{
char t5[16];
char t7[16];
char *t1;
char *t3;
char *t4;
char *t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(55, ng0);
LAB3: t1 = (t0 + 11472);
t3 = (t0 + 1192U);
t4 = *((char **)t3);
t6 = ((IEEE_P_2592010699) + 4000);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
t9 = (t8 + 4U);
*((int *)t9) = 0;
t9 = (t8 + 8U);
*((int *)t9) = 1;
t10 = (0 - 0);
t11 = (t10 * 1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11240U);
t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
t11 = (1U + 8U);
t12 = (9U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 7368);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t3, 9U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 7080);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t11, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_2(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(56, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 11288U);
t4 = (t0 + 2472U);
t5 = *((char **)t4);
t4 = (t0 + 11304U);
t6 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (9U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7432);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 9U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7096);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t9, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_3(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(57, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 11288U);
t4 = (t0 + 2472U);
t5 = *((char **)t4);
t4 = (t0 + 11304U);
t6 = ieee_p_3620187407_sub_1496620905533721142_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (9U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7496);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 9U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7112);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t9, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_4(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(58, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 11224U);
t4 = (t0 + 1192U);
t5 = *((char **)t4);
t4 = (t0 + 11240U);
t6 = ieee_p_3620187407_sub_1496620905533613331_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (16U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7560);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 16U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7128);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(16U, t9, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_5(char *t0)
{
char t5[16];
char t23[16];
char t41[16];
char *t1;
char *t2;
char *t3;
char *t6;
char *t7;
int t8;
unsigned int t9;
unsigned char t10;
char *t11;
unsigned int t12;
unsigned int t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t24;
char *t25;
int t26;
unsigned int t27;
unsigned char t28;
char *t29;
unsigned int t30;
unsigned int t31;
char *t32;
char *t33;
char *t34;
char *t35;
char *t36;
char *t37;
char *t38;
char *t39;
char *t42;
char *t43;
int t44;
unsigned int t45;
unsigned char t46;
char *t47;
unsigned int t48;
unsigned int t49;
char *t50;
char *t51;
char *t52;
char *t53;
char *t54;
char *t55;
char *t56;
char *t57;
char *t58;
char *t59;
char *t60;
char *t61;
char *t62;
LAB0: xsi_set_current_line(60, ng0);
t1 = (t0 + 1352U);
t2 = *((char **)t1);
t1 = (t0 + 11256U);
t3 = (t0 + 11473);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
t7 = (t6 + 4U);
*((int *)t7) = 2;
t7 = (t6 + 8U);
*((int *)t7) = 1;
t8 = (2 - 0);
t9 = (t8 * 1);
t9 = (t9 + 1);
t7 = (t6 + 12U);
*((unsigned int *)t7) = t9;
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
if (t10 != 0)
goto LAB3;
LAB4: t19 = (t0 + 1352U);
t20 = *((char **)t19);
t19 = (t0 + 11256U);
t21 = (t0 + 11476);
t24 = (t23 + 0U);
t25 = (t24 + 0U);
*((int *)t25) = 0;
t25 = (t24 + 4U);
*((int *)t25) = 2;
t25 = (t24 + 8U);
*((int *)t25) = 1;
t26 = (2 - 0);
t27 = (t26 * 1);
t27 = (t27 + 1);
t25 = (t24 + 12U);
*((unsigned int *)t25) = t27;
t28 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t20, t19, t21, t23);
if (t28 != 0)
goto LAB5;
LAB6: t37 = (t0 + 1352U);
t38 = *((char **)t37);
t37 = (t0 + 11256U);
t39 = (t0 + 11479);
t42 = (t41 + 0U);
t43 = (t42 + 0U);
*((int *)t43) = 0;
t43 = (t42 + 4U);
*((int *)t43) = 2;
t43 = (t42 + 8U);
*((int *)t43) = 1;
t44 = (2 - 0);
t45 = (t44 * 1);
t45 = (t45 + 1);
t43 = (t42 + 12U);
*((unsigned int *)t43) = t45;
t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t38, t37, t39, t41);
if (t46 != 0)
goto LAB7;
LAB8:
LAB9: t55 = xsi_get_transient_memory(8U);
memset(t55, 0, 8U);
t56 = t55;
memset(t56, (unsigned char)2, 8U);
t57 = (t0 + 7624);
t58 = (t57 + 56U);
t59 = *((char **)t58);
t60 = (t59 + 56U);
t61 = *((char **)t60);
memcpy(t61, t55, 8U);
xsi_driver_first_trans_fast(t57);
LAB2: t62 = (t0 + 7144);
*((int *)t62) = 1;
LAB1: return;
LAB3: t7 = (t0 + 2632U);
t11 = *((char **)t7);
t9 = (8 - 7);
t12 = (t9 * 1U);
t13 = (0 + t12);
t7 = (t11 + t13);
t14 = (t0 + 7624);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t18 = *((char **)t17);
memcpy(t18, t7, 8U);
xsi_driver_first_trans_fast(t14);
goto LAB2;
LAB5: t25 = (t0 + 2792U);
t29 = *((char **)t25);
t27 = (8 - 7);
t30 = (t27 * 1U);
t31 = (0 + t30);
t25 = (t29 + t31);
t32 = (t0 + 7624);
t33 = (t32 + 56U);
t34 = *((char **)t33);
t35 = (t34 + 56U);
t36 = *((char **)t35);
memcpy(t36, t25, 8U);
xsi_driver_first_trans_fast(t32);
goto LAB2;
LAB7: t43 = (t0 + 2952U);
t47 = *((char **)t43);
t45 = (15 - 7);
t48 = (t45 * 1U);
t49 = (0 + t48);
t43 = (t47 + t49);
t50 = (t0 + 7624);
t51 = (t50 + 56U);
t52 = *((char **)t51);
t53 = (t52 + 56U);
t54 = *((char **)t53);
memcpy(t54, t43, 8U);
xsi_driver_first_trans_fast(t50);
goto LAB2;
LAB10: goto LAB2;
}
static void work_a_0832606739_3212880686_p_6(char *t0)
{
char t7[16];
char t13[16];
char t21[16];
unsigned char t1;
char *t2;
char *t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
char *t14;
char *t15;
int t16;
unsigned char t17;
char *t18;
char *t19;
char *t22;
char *t23;
int t24;
unsigned char t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
char *t31;
char *t32;
char *t33;
char *t34;
char *t35;
LAB0: xsi_set_current_line(64, ng0);
t2 = (t0 + 2952U);
t3 = *((char **)t2);
t4 = (15 - 15);
t5 = (t4 * 1U);
t6 = (0 + t5);
t2 = (t3 + t6);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 15;
t9 = (t8 + 4U);
*((int *)t9) = 8;
t9 = (t8 + 8U);
*((int *)t9) = -1;
t10 = (8 - 15);
t11 = (t10 * -1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11482);
t14 = (t13 + 0U);
t15 = (t14 + 0U);
*((int *)t15) = 0;
t15 = (t14 + 4U);
*((int *)t15) = 7;
t15 = (t14 + 8U);
*((int *)t15) = 1;
t16 = (7 - 0);
t11 = (t16 * 1);
t11 = (t11 + 1);
t15 = (t14 + 12U);
*((unsigned int *)t15) = t11;
t17 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t2, t7, t9, t13);
if (t17 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t30 = (t0 + 7688);
t31 = (t30 + 56U);
t32 = *((char **)t31);
t33 = (t32 + 56U);
t34 = *((char **)t33);
*((unsigned char *)t34) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t30);
LAB2: t35 = (t0 + 7160);
*((int *)t35) = 1;
LAB1: return;
LAB3: t23 = (t0 + 7688);
t26 = (t23 + 56U);
t27 = *((char **)t26);
t28 = (t27 + 56U);
t29 = *((char **)t28);
*((unsigned char *)t29) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t23);
goto LAB2;
LAB5: t15 = (t0 + 1352U);
t18 = *((char **)t15);
t15 = (t0 + 11256U);
t19 = (t0 + 11490);
t22 = (t21 + 0U);
t23 = (t22 + 0U);
*((int *)t23) = 0;
t23 = (t22 + 4U);
*((int *)t23) = 2;
t23 = (t22 + 8U);
*((int *)t23) = 1;
t24 = (2 - 0);
t11 = (t24 * 1);
t11 = (t11 + 1);
t23 = (t22 + 12U);
*((unsigned int *)t23) = t11;
t25 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t18, t15, t19, t21);
t1 = t25;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_0832606739_3212880686_p_7(char *t0)
{
char t14[16];
unsigned char t1;
char *t2;
char *t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t15;
char *t16;
int t17;
unsigned int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(66, ng0);
t2 = (t0 + 2632U);
t3 = *((char **)t2);
t4 = (8 - 8);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t2 = (t3 + t7);
t8 = *((unsigned char *)t2);
t9 = (t8 == (unsigned char)3);
if (t9 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7752);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7176);
*((int *)t29) = 1;
LAB1: return;
LAB3: t16 = (t0 + 7752);
t20 = (t16 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t16);
goto LAB2;
LAB5: t10 = (t0 + 1352U);
t11 = *((char **)t10);
t10 = (t0 + 11256U);
t12 = (t0 + 11493);
t15 = (t14 + 0U);
t16 = (t15 + 0U);
*((int *)t16) = 0;
t16 = (t15 + 4U);
*((int *)t16) = 2;
t16 = (t15 + 8U);
*((int *)t16) = 1;
t17 = (2 - 0);
t18 = (t17 * 1);
t18 = (t18 + 1);
t16 = (t15 + 12U);
*((unsigned int *)t16) = t18;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_0832606739_3212880686_p_8(char *t0)
{
char t14[16];
unsigned char t1;
char *t2;
char *t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t15;
char *t16;
int t17;
unsigned int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(68, ng0);
t2 = (t0 + 2792U);
t3 = *((char **)t2);
t4 = (8 - 8);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t2 = (t3 + t7);
t8 = *((unsigned char *)t2);
t9 = (t8 == (unsigned char)3);
if (t9 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7816);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7192);
*((int *)t29) = 1;
LAB1: return;
LAB3: t16 = (t0 + 7816);
t20 = (t16 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t16);
goto LAB2;
LAB5: t10 = (t0 + 1352U);
t11 = *((char **)t10);
t10 = (t0 + 11256U);
t12 = (t0 + 11496);
t15 = (t14 + 0U);
t16 = (t15 + 0U);
*((int *)t16) = 0;
t16 = (t15 + 4U);
*((int *)t16) = 2;
t16 = (t15 + 8U);
*((int *)t16) = 1;
t17 = (2 - 0);
t18 = (t17 * 1);
t18 = (t18 + 1);
t16 = (t15 + 12U);
*((unsigned int *)t16) = t18;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_0832606739_3212880686_p_9(char *t0)
{
char t6[16];
char t15[16];
unsigned char t1;
char *t2;
char *t3;
char *t4;
char *t7;
char *t8;
int t9;
unsigned int t10;
unsigned char t11;
char *t12;
char *t13;
char *t16;
char *t17;
int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(70, ng0);
t2 = (t0 + 3112U);
t3 = *((char **)t2);
t2 = (t0 + 11368U);
t4 = (t0 + 11499);
t7 = (t6 + 0U);
t8 = (t7 + 0U);
*((int *)t8) = 0;
t8 = (t7 + 4U);
*((int *)t8) = 7;
t8 = (t7 + 8U);
*((int *)t8) = 1;
t9 = (7 - 0);
t10 = (t9 * 1);
t10 = (t10 + 1);
t8 = (t7 + 12U);
*((unsigned int *)t8) = t10;
t11 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t3, t2, t4, t6);
if (t11 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7880);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7208);
*((int *)t29) = 1;
LAB1: return;
LAB3: t17 = (t0 + 7880);
t20 = (t17 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t17);
goto LAB2;
LAB5: t8 = (t0 + 1352U);
t12 = *((char **)t8);
t8 = (t0 + 11256U);
t13 = (t0 + 11507);
t16 = (t15 + 0U);
t17 = (t16 + 0U);
*((int *)t17) = 0;
t17 = (t16 + 4U);
*((int *)t17) = 2;
t17 = (t16 + 8U);
*((int *)t17) = 1;
t18 = (2 - 0);
t10 = (t18 * 1);
t10 = (t10 + 1);
t17 = (t16 + 12U);
*((unsigned int *)t17) = t10;
t19 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t12, t8, t13, t15);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_0832606739_3212880686_p_10(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(72, ng0);
LAB3: t1 = (t0 + 3112U);
t2 = *((char **)t1);
t1 = (t0 + 7944);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 7224);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_0832606739_3212880686_init()
{
static char *pe[] = {(void *)work_a_0832606739_3212880686_p_0,(void *)work_a_0832606739_3212880686_p_1,(void *)work_a_0832606739_3212880686_p_2,(void *)work_a_0832606739_3212880686_p_3,(void *)work_a_0832606739_3212880686_p_4,(void *)work_a_0832606739_3212880686_p_5,(void *)work_a_0832606739_3212880686_p_6,(void *)work_a_0832606739_3212880686_p_7,(void *)work_a_0832606739_3212880686_p_8,(void *)work_a_0832606739_3212880686_p_9,(void *)work_a_0832606739_3212880686_p_10};
xsi_register_didat("work_a_0832606739_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat");
xsi_register_executes(pe);
}

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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat Normal file
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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.lin64.o Normal file
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86
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c → xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.c
View file

@ -21,11 +21,11 @@
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd";
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd";
static void work_a_4060154216_2372691052_p_0(char *t0)
static void work_a_1229531095_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
@ -36,46 +36,46 @@ static void work_a_4060154216_2372691052_p_0(char *t0)
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 2624U);
LAB0: t1 = (t0 + 2464U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(73, ng0);
t2 = (t0 + 3256);
LAB2: xsi_set_current_line(68, ng0);
t2 = (t0 + 3096);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(74, ng0);
t2 = (t0 + 1648U);
xsi_set_current_line(69, ng0);
t2 = (t0 + 1488U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2432);
t2 = (t0 + 2272);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(75, ng0);
t2 = (t0 + 3256);
LAB4: xsi_set_current_line(70, ng0);
t2 = (t0 + 3096);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(76, ng0);
t2 = (t0 + 1648U);
xsi_set_current_line(71, ng0);
t2 = (t0 + 1488U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2432);
t2 = (t0 + 2272);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
@ -93,7 +93,7 @@ LAB11: goto LAB9;
}
static void work_a_4060154216_2372691052_p_1(char *t0)
static void work_a_1229531095_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
@ -103,30 +103,28 @@ static void work_a_4060154216_2372691052_p_1(char *t0)
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
LAB0: t1 = (t0 + 2872U);
LAB0: t1 = (t0 + 2712U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(84, ng0);
LAB2: xsi_set_current_line(79, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 2680);
t2 = (t0 + 2520);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(86, ng0);
t2 = (t0 + 1648U);
LAB4: xsi_set_current_line(81, ng0);
t2 = (t0 + 1488U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 2680);
t2 = (t0 + 2520);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
@ -136,19 +134,15 @@ LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(88, ng0);
t2 = (t0 + 5568);
t6 = (t0 + 3320);
LAB8: xsi_set_current_line(86, ng0);
t2 = (t0 + 3160);
t4 = (t2 + 56U);
t6 = *((char **)t4);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(89, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 2680);
xsi_process_wait(t2, t3);
*((unsigned char *)t8) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(90, ng0);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
@ -157,36 +151,18 @@ LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: xsi_set_current_line(91, ng0);
t2 = (t0 + 5576);
t6 = (t0 + 3320);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(94, ng0);
LAB18: *((char **)t1) = &&LAB19;
goto LAB1;
LAB12: goto LAB2;
LAB13: goto LAB12;
LAB15: goto LAB13;
LAB16: goto LAB2;
LAB17: goto LAB16;
LAB19: goto LAB17;
}
extern void work_a_4060154216_2372691052_init()
extern void work_a_1229531095_2372691052_init()
{
static char *pe[] = {(void *)work_a_4060154216_2372691052_p_0,(void *)work_a_4060154216_2372691052_p_1};
xsi_register_didat("work_a_4060154216_2372691052", "isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat");
static char *pe[] = {(void *)work_a_1229531095_2372691052_p_0,(void *)work_a_1229531095_2372691052_p_1};
xsi_register_didat("work_a_1229531095_2372691052", "isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat Normal file
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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.lin64.o Normal file
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181
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.c Normal file
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@ -0,0 +1,181 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd";
extern char *IEEE_P_2592010699;
extern char *IEEE_P_1242562249;
int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
static void work_a_1466808984_3212880686_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
unsigned char t4;
char *t5;
unsigned char t6;
char *t7;
int t8;
int t9;
unsigned int t10;
unsigned int t11;
unsigned int t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
unsigned char t19;
LAB0: t1 = (t0 + 3144U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(42, ng0);
LAB6: t2 = (t0 + 3464);
*((int *)t2) = 1;
*((char **)t1) = &&LAB7;
LAB1: return;
LAB4: t5 = (t0 + 3464);
*((int *)t5) = 0;
xsi_set_current_line(43, ng0);
t2 = (t0 + 1352U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t6 = (t4 == (unsigned char)3);
if (t6 != 0)
goto LAB8;
LAB10: xsi_set_current_line(46, ng0);
t2 = (t0 + 1192U);
t3 = *((char **)t2);
t2 = (t0 + 1032U);
t5 = *((char **)t2);
t2 = (t0 + 5968U);
t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t5, t2);
t9 = (t8 - 0);
t10 = (t9 * 1);
t11 = (8U * t10);
t12 = (0U + t11);
t7 = (t0 + 3608);
t13 = (t7 + 56U);
t14 = *((char **)t13);
t15 = (t14 + 56U);
t16 = *((char **)t15);
memcpy(t16, t3, 8U);
xsi_driver_first_trans_delta(t7, t12, 8U, 0LL);
LAB9: xsi_set_current_line(48, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t6 = (t4 == (unsigned char)2);
if (t6 != 0)
goto LAB11;
LAB13:
LAB12: goto LAB2;
LAB5: t3 = (t0 + 1632U);
t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
if (t4 == 1)
goto LAB4;
else
goto LAB6;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(44, ng0);
t2 = (t0 + 1992U);
t5 = *((char **)t2);
t2 = (t0 + 1032U);
t7 = *((char **)t2);
t2 = (t0 + 5968U);
t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2);
t9 = (t8 - 0);
t10 = (t9 * 1);
xsi_vhdl_check_range_of_index(0, 255, 1, t8);
t11 = (8U * t10);
t12 = (0 + t11);
t13 = (t5 + t12);
t14 = (t0 + 3544);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t18 = *((char **)t17);
memcpy(t18, t13, 8U);
xsi_driver_first_trans_fast_port(t14);
goto LAB9;
LAB11: xsi_set_current_line(49, ng0);
t2 = xsi_get_transient_memory(2048U);
memset(t2, 0, 2048U);
t5 = t2;
t7 = (t0 + 8123);
t19 = (8U != 0);
if (t19 == 1)
goto LAB14;
LAB15: t14 = (t0 + 3608);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t18 = *((char **)t17);
memcpy(t18, t2, 2048U);
xsi_driver_first_trans_fast(t14);
xsi_set_current_line(50, ng0);
t2 = xsi_get_transient_memory(8U);
memset(t2, 0, 8U);
t3 = t2;
memset(t3, (unsigned char)2, 8U);
t5 = (t0 + 3544);
t7 = (t5 + 56U);
t13 = *((char **)t7);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t2, 8U);
xsi_driver_first_trans_fast_port(t5);
goto LAB12;
LAB14: t10 = (2048U / 8U);
xsi_mem_set_data(t5, t7, 8U, t10);
goto LAB15;
}
extern void work_a_1466808984_3212880686_init()
{
static char *pe[] = {(void *)work_a_1466808984_3212880686_p_0};
xsi_register_didat("work_a_1466808984_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat");
xsi_register_executes(pe);
}

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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat Normal file
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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.lin64.o Normal file
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4
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c → xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c
View file

@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0)
char *t14;
char *t15;
LAB0: xsi_set_current_line(39, ng0);
LAB0: xsi_set_current_line(45, ng0);
LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1);
@ -79,6 +79,6 @@ LAB4: goto LAB2;
extern void work_a_1802466774_3212880686_init()
{
static char *pe[] = {(void *)work_a_1802466774_3212880686_p_0};
xsi_register_didat("work_a_1802466774_3212880686", "isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat");
xsi_register_didat("work_a_1802466774_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat → xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat
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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o → xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o
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116
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c Normal file
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@ -0,0 +1,116 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
static void work_a_3650175700_3212880686_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
unsigned char t4;
char *t5;
char *t6;
char *t7;
char *t8;
LAB0: t1 = (t0 + 3464U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(49, ng0);
LAB6: t2 = (t0 + 3784);
*((int *)t2) = 1;
*((char **)t1) = &&LAB7;
LAB1: return;
LAB4: t5 = (t0 + 3784);
*((int *)t5) = 0;
xsi_set_current_line(50, ng0);
t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 3864);
t5 = (t2 + 56U);
t6 = *((char **)t5);
t7 = (t6 + 56U);
t8 = *((char **)t7);
memcpy(t8, t3, 8U);
xsi_driver_first_trans_fast_port(t2);
xsi_set_current_line(51, ng0);
t2 = (t0 + 1192U);
t3 = *((char **)t2);
t2 = (t0 + 3928);
t5 = (t2 + 56U);
t6 = *((char **)t5);
t7 = (t6 + 56U);
t8 = *((char **)t7);
memcpy(t8, t3, 8U);
xsi_driver_first_trans_fast_port(t2);
xsi_set_current_line(52, ng0);
t2 = (t0 + 1352U);
t3 = *((char **)t2);
t2 = (t0 + 3992);
t5 = (t2 + 56U);
t6 = *((char **)t5);
t7 = (t6 + 56U);
t8 = *((char **)t7);
memcpy(t8, t3, 8U);
xsi_driver_first_trans_fast_port(t2);
xsi_set_current_line(53, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t2 = (t0 + 4056);
t5 = (t2 + 56U);
t6 = *((char **)t5);
t7 = (t6 + 56U);
t8 = *((char **)t7);
memcpy(t8, t3, 8U);
xsi_driver_first_trans_fast_port(t2);
goto LAB2;
LAB5: t3 = (t0 + 1632U);
t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
if (t4 == 1)
goto LAB4;
else
goto LAB6;
LAB7: goto LAB5;
}
extern void work_a_3650175700_3212880686_init()
{
static char *pe[] = {(void *)work_a_3650175700_3212880686_p_0};
xsi_register_didat("work_a_3650175700_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat");
xsi_register_executes(pe);
}

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343
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.c Normal file
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@ -0,0 +1,343 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd";
extern char *IEEE_P_2592010699;
extern char *IEEE_P_1242562249;
extern char *IEEE_P_3620187407;
int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
static void work_a_3998322972_3212880686_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
unsigned char t4;
char *t5;
unsigned char t6;
char *t7;
int t8;
int t9;
unsigned int t10;
unsigned int t11;
unsigned int t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
unsigned char t18;
char *t19;
LAB0: t1 = (t0 + 3624U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(47, ng0);
LAB6: t2 = (t0 + 4440);
*((int *)t2) = 1;
*((char **)t1) = &&LAB7;
LAB1: return;
LAB4: t5 = (t0 + 4440);
*((int *)t5) = 0;
xsi_set_current_line(48, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t6 = (t4 == (unsigned char)3);
if (t6 != 0)
goto LAB8;
LAB10:
LAB9: xsi_set_current_line(51, ng0);
t2 = (t0 + 1832U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t6 = (t4 == (unsigned char)2);
if (t6 != 0)
goto LAB11;
LAB13:
LAB12: goto LAB2;
LAB5: t3 = (t0 + 1952U);
t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
if (t4 == 1)
goto LAB4;
else
goto LAB6;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(49, ng0);
t2 = (t0 + 1672U);
t5 = *((char **)t2);
t2 = (t0 + 1352U);
t7 = *((char **)t2);
t2 = (t0 + 7424U);
t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2);
t9 = (t8 - 0);
t10 = (t9 * 1);
t11 = (8U * t10);
t12 = (0U + t11);
t13 = (t0 + 4552);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t5, 8U);
xsi_driver_first_trans_delta(t13, t12, 8U, 0LL);
goto LAB9;
LAB11: xsi_set_current_line(52, ng0);
t2 = xsi_get_transient_memory(128U);
memset(t2, 0, 128U);
t5 = t2;
t7 = (t0 + 7679);
t18 = (8U != 0);
if (t18 == 1)
goto LAB14;
LAB15: t14 = (t0 + 4552);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t19 = *((char **)t17);
memcpy(t19, t2, 128U);
xsi_driver_first_trans_fast(t14);
goto LAB12;
LAB14: t10 = (128U / 8U);
xsi_mem_set_data(t5, t7, 8U, t10);
goto LAB15;
}
static void work_a_3998322972_3212880686_p_1(char *t0)
{
unsigned char t1;
char *t2;
char *t3;
unsigned char t4;
unsigned char t5;
char *t6;
char *t7;
char *t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
int t13;
int t14;
unsigned int t15;
unsigned int t16;
unsigned int t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
LAB0: xsi_set_current_line(55, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t5 = (t4 == (unsigned char)2);
if (t5 == 1)
goto LAB5;
LAB6: t2 = (t0 + 1032U);
t6 = *((char **)t2);
t2 = (t0 + 7392U);
t7 = (t0 + 1352U);
t8 = *((char **)t7);
t7 = (t0 + 7424U);
t9 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t6, t2, t8, t7);
t1 = t9;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 1672U);
t25 = *((char **)t24);
t24 = (t0 + 4616);
t26 = (t24 + 56U);
t27 = *((char **)t26);
t28 = (t27 + 56U);
t29 = *((char **)t28);
memcpy(t29, t25, 8U);
xsi_driver_first_trans_fast_port(t24);
LAB2: t30 = (t0 + 4456);
*((int *)t30) = 1;
LAB1: return;
LAB3: t10 = (t0 + 2472U);
t11 = *((char **)t10);
t10 = (t0 + 1032U);
t12 = *((char **)t10);
t10 = (t0 + 7392U);
t13 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t12, t10);
t14 = (t13 - 0);
t15 = (t14 * 1);
xsi_vhdl_check_range_of_index(0, 15, 1, t13);
t16 = (8U * t15);
t17 = (0 + t16);
t18 = (t11 + t17);
t19 = (t0 + 4616);
t20 = (t19 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
memcpy(t23, t18, 8U);
xsi_driver_first_trans_fast_port(t19);
goto LAB2;
LAB5: t1 = (unsigned char)1;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_3998322972_3212880686_p_2(char *t0)
{
unsigned char t1;
char *t2;
char *t3;
unsigned char t4;
unsigned char t5;
char *t6;
char *t7;
char *t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
int t13;
int t14;
unsigned int t15;
unsigned int t16;
unsigned int t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
LAB0: xsi_set_current_line(57, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t5 = (t4 == (unsigned char)2);
if (t5 == 1)
goto LAB5;
LAB6: t2 = (t0 + 1192U);
t6 = *((char **)t2);
t2 = (t0 + 7408U);
t7 = (t0 + 1352U);
t8 = *((char **)t7);
t7 = (t0 + 7424U);
t9 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t6, t2, t8, t7);
t1 = t9;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 1672U);
t25 = *((char **)t24);
t24 = (t0 + 4680);
t26 = (t24 + 56U);
t27 = *((char **)t26);
t28 = (t27 + 56U);
t29 = *((char **)t28);
memcpy(t29, t25, 8U);
xsi_driver_first_trans_fast_port(t24);
LAB2: t30 = (t0 + 4472);
*((int *)t30) = 1;
LAB1: return;
LAB3: t10 = (t0 + 2472U);
t11 = *((char **)t10);
t10 = (t0 + 1192U);
t12 = *((char **)t10);
t10 = (t0 + 7408U);
t13 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t12, t10);
t14 = (t13 - 0);
t15 = (t14 * 1);
xsi_vhdl_check_range_of_index(0, 15, 1, t13);
t16 = (8U * t15);
t17 = (0 + t16);
t18 = (t11 + t17);
t19 = (t0 + 4680);
t20 = (t19 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
memcpy(t23, t18, 8U);
xsi_driver_first_trans_fast_port(t19);
goto LAB2;
LAB5: t1 = (unsigned char)1;
goto LAB7;
LAB9: goto LAB2;
}
extern void work_a_3998322972_3212880686_init()
{
static char *pe[] = {(void *)work_a_3998322972_3212880686_p_0,(void *)work_a_3998322972_3212880686_p_1,(void *)work_a_3998322972_3212880686_p_2};
xsi_register_didat("work_a_3998322972_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat");
xsi_register_executes(pe);
}

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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c Normal file
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9
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.c → xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/process_test_isim_beh.exe_main.c
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@ -32,10 +32,15 @@ int main(int argc, char **argv)
ieee_p_3620187407_init();
ieee_p_1242562249_init();
work_a_1802466774_3212880686_init();
work_a_4060154216_2372691052_init();
work_a_3650175700_3212880686_init();
work_a_3998322972_3212880686_init();
work_a_0832606739_3212880686_init();
work_a_1466808984_3212880686_init();
work_a_4150868852_3212880686_init();
work_a_1229531095_2372691052_init();
xsi_register_tops("work_a_4060154216_2372691052");
xsi_register_tops("work_a_1229531095_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);

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93
xilinx/ALU/process_test.vhd Normal file
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@ -0,0 +1,93 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:37:50 05/10/2021
-- Design Name:
-- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: processeur
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY process_test IS
END process_test;
ARCHITECTURE behavior OF process_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT processeur
PORT(
CLK : IN std_logic;
RST : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: processeur PORT MAP (
CLK => CLK,
RST => RST
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
-- AFC test
RST<='1';
wait;
end process;
END;

7
xilinx/ALU/process_test_beh.prj Normal file
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@ -0,0 +1,7 @@
vhdl work "pipeline.vhd"
vhdl work "br.vhd"
vhdl work "bm_instr.vhd"
vhdl work "bm.vhd"
vhdl work "alu.vhd"
vhdl work "processeur.vhd"
vhdl work "process_test.vhd"

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99
xilinx/ALU/processeur.vhd
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@ -19,6 +19,9 @@
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
@ -38,7 +41,7 @@ architecture Behavioral of processeur is
COMPONENT bm_instr
PORT(
IN_addr : IN std_logic_vector(7 downto 0);
OUT_data : OUT std_logic_vector(7 downto 0);
OUT_data : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
@ -48,6 +51,7 @@ architecture Behavioral of processeur is
A_IN : in STD_LOGIC_VECTOR (7 downto 0);
B_IN : in STD_LOGIC_VECTOR (7 downto 0);
C_IN : in STD_LOGIC_VECTOR (7 downto 0);
CLK : IN std_logic;
OP_OUT : out STD_LOGIC_VECTOR (7 downto 0);
A_OUT : out STD_LOGIC_VECTOR (7 downto 0);
B_OUT : out STD_LOGIC_VECTOR (7 downto 0);
@ -92,13 +96,7 @@ architecture Behavioral of processeur is
OUT_data : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal RST : std_logic := '0';
signal CLK : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
--Inputs
signal IP : std_logic_vector(7 downto 0) := (others => '0');
signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0');
@ -107,7 +105,7 @@ architecture Behavioral of processeur is
signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal OUT_data : std_logic_vector(7 downto 0);
signal OUT_data : std_logic_vector(31 downto 0);
signal OP_LIDI_OUT : std_logic_vector(7 downto 0);
signal A_LIDI_OUT : std_logic_vector(7 downto 0);
@ -139,53 +137,56 @@ architecture Behavioral of processeur is
signal addr_dm_MUX : std_logic_vector(7 downto 0);
signal in_dm_MUX : std_logic_vector(7 downto 0);
signal out_dm_MUX : std_logic_vector(7 downto 0);
signal B_EXMem_IN : std_logic_vector(7 downto 0);
signal W_br_LC : std_logic;
signal S_IN_MUX : std_logic_vector(7 downto 0);
signal B_MemRE_IN : std_logic_vector(7 downto 0);
begin
-- Instantiate adresse des instructions
addr_instructions: bm_instr PORT MAP (
IP => IN_addr,
IN_addr => IP,
OUT_data => OUT_data,
CLK => CLK
);
-- Instantiate pipeline LI_LD
LI_LD : pipeline PORT MAP (
OP_IN <= OUT_data(31 downto 24),
A_IN <= OUT_data(23 downto 16),
B_IN <= OUT_data(15 downto 8),
C_IN <= OUT_data(7 downto 0),
OP_IN => OUT_data(31 downto 24),
A_IN => OUT_data(23 downto 16),
B_IN => OUT_data(15 downto 8),
C_IN => OUT_data(7 downto 0),
CLK => CLK,
A_OUT => A_LIDI_OUT,
B_OUT => B_LIDI_OUT,
C_OUT => C_LIDI_OUT,
OP_OUT => OP_LIDI_OUT
);
W_br_LC <= '1' when OP_MemRE_OUT = x"07" else
W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else
'0';
-- Instanciate banc de registre
banc_registres : br PORT MAP (
B_LIDI_OUT => A_addr,
C_LIDI_OUT => B_addr,
A_MemRE_OUT => W_addr,
W_br_LC => W, --ATTENTION LC
B_MemRE_OUT => Data,
A_addr => B_LIDI_OUT(3 downto 0),
B_addr => C_LIDI_OUT(3 downto 0),
W_addr => A_MemRE_OUT(3 downto 0),
W => W_br_LC, --ATTENTION LC
Data => B_MemRE_OUT,
RST => RST,
CLK => CLK,
QA => QA_IN_MUX,
QB => C_DIEX_IN
);
B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" else B_LIDI_OUT ;
B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ;
-- Instantiate pipeline DI_EX
DI_EX : pipeline PORT MAP (
OP_IN <= OP_LIDI_OUT,
A_IN <= A_LIDI_OUT,
B_IN <= B_DIEX_IN,
C_IN <= C_DIEX_IN,
OP_IN => OP_LIDI_OUT,
A_IN => A_LIDI_OUT,
B_IN => B_DIEX_IN,
C_IN => C_DIEX_IN,
CLK => CLK,
A_OUT => A_DIEX_OUT,
B_OUT => B_DIEX_OUT,
@ -200,9 +201,9 @@ begin
-- Instantiate alu
UAL : alu PORT MAP (
A <= B_DIEX_OUT,
B <= C_DIEX_OUT,
Ctrl_Alu <= Ctr_AlU_LC,
A => B_DIEX_OUT,
B => C_DIEX_OUT,
Ctrl_Alu =>Ctr_AlU_LC,
N => N_ALU_OUT,
O => O_ALU_OUT,
Z => Z_ALU_OUT,
@ -216,10 +217,10 @@ begin
-- Instantiate pipeline EX_Mem
EX_Mem : pipeline PORT MAP (
OP_IN <= OP_DIEX_OUT,
A_IN <= A_DIEX_OUT,
B_IN <= B_EXMem_IN,
C_IN <= x"00",
OP_IN => OP_DIEX_OUT,
A_IN => A_DIEX_OUT,
B_IN => B_EXMem_IN,
C_IN => x"00",
CLK => CLK,
A_OUT => A_EXMem_OUT,
B_OUT => B_EXMem_OUT,
@ -236,9 +237,9 @@ begin
B_EXMem_OUT;
-- Instantiate banc de données
data_memory: bm_data PORT MAP (
addr_dm_MUX => IN_addr,
B_MemRE_IN => IN_data,
RW_LC => RW,
IN_addr => addr_dm_MUX,
IN_data => B_MemRE_IN,
RW => RW_LC,
RST => RST,
CLK => CLK,
OUT_data => out_dm_MUX
@ -246,29 +247,25 @@ begin
-- Instantiate pipeline Mem_RE
Mem_RE : pipeline PORT MAP (
OP_IN <= OP_EXMem_OUT,
A_IN <= A_EXMem_OUT,
B_IN <= OUT_data(15 downto 8),
C_IN <= x"00",
OP_IN => OP_EXMem_OUT,
A_IN => A_EXMem_OUT,
B_IN => B_EXMem_OUT,
C_IN => x"00",
CLK => CLK,
A_OUT => A_MemRE_OUT,
B_OUT => B_MemRE_OUT,
C_OUT => open,
OP_OUT => OP_MemRE_OUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
IP <= IP + "00000001";
process
begin
wait until rising_edge(CLK);
if rst = '0' then
IP <= x"00";
else
IP <= IP + "00000001";
end if;
end process;
end Behavioral;

6
xilinx/ALU/processeur_summary.html
View file

@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>alu Project Status</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>processeur Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>ALU.xise</TD>
@ -72,9 +72,9 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>mar. mai 4 13:11:04 2021</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lun. mai 10 10:45:43 2021</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 05/04/2021 - 15:22:09</center>
<br><center><b>Date Generated:</b> 05/10/2021 - 10:47:06</center>
</BODY></HTML>

149
xilinx/ALU/tests/test_afc.wcfg Normal file
View file

@ -0,0 +1,149 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="process_test" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="33" />
<wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/addr_instructions/in_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_addr[7:0]</obj_property>
<obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[31:0]</obj_property>
<obj_property name="ObjectShortName">out_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">w_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">w</obj_property>
<obj_property name="ObjectShortName">w</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data[7:0]</obj_property>
<obj_property name="ObjectShortName">data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
<obj_property name="ElementShortName">registres[0:15]</obj_property>
<obj_property name="ObjectShortName">registres[0:15]</obj_property>
</wvobject>
</wave_config>

209
xilinx/ALU/tests/test_alu.wcfg Normal file
View file

@ -0,0 +1,209 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="process_test" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="48" />
<wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/addr_instructions/in_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_addr[7:0]</obj_property>
<obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[31:0]</obj_property>
<obj_property name="ObjectShortName">out_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/c_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_in[7:0]</obj_property>
<obj_property name="ObjectShortName">c_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/c_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_out[7:0]</obj_property>
<obj_property name="ObjectShortName">c_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/c_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_in[7:0]</obj_property>
<obj_property name="ObjectShortName">c_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/c_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_out[7:0]</obj_property>
<obj_property name="ObjectShortName">c_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/UAL/a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a[7:0]</obj_property>
<obj_property name="ObjectShortName">a[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/UAL/b" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b[7:0]</obj_property>
<obj_property name="ObjectShortName">b[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/UAL/ctrl_alu" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_alu[2:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_alu[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/UAL/s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s[7:0]</obj_property>
<obj_property name="ObjectShortName">s[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/c_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_in[7:0]</obj_property>
<obj_property name="ObjectShortName">c_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/c_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_out[7:0]</obj_property>
<obj_property name="ObjectShortName">c_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/c_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_in[7:0]</obj_property>
<obj_property name="ObjectShortName">c_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/c_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_out[7:0]</obj_property>
<obj_property name="ObjectShortName">c_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/a_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">a_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/b_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">b_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">w</obj_property>
<obj_property name="ObjectShortName">w</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/qa" type="array" db_ref_id="1">
<obj_property name="ElementShortName">qa[7:0]</obj_property>
<obj_property name="ObjectShortName">qa[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">w_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data[7:0]</obj_property>
<obj_property name="ObjectShortName">data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
<obj_property name="ElementShortName">registres[0:15]</obj_property>
<obj_property name="ObjectShortName">registres[0:15]</obj_property>
</wvobject>
</wave_config>

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xilinx/ALU/tests/test_cop.wcfg Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="process_test" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="37" />
<wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/addr_instructions/in_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_addr[7:0]</obj_property>
<obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[31:0]</obj_property>
<obj_property name="ObjectShortName">out_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/a_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">a_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">w_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/b_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">b_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">w</obj_property>
<obj_property name="ObjectShortName">w</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data[7:0]</obj_property>
<obj_property name="ObjectShortName">data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/qa" type="array" db_ref_id="1">
<obj_property name="ElementShortName">qa[7:0]</obj_property>
<obj_property name="ObjectShortName">qa[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
<obj_property name="ElementShortName">registres[0:15]</obj_property>
<obj_property name="ObjectShortName">registres[0:15]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/qb" type="array" db_ref_id="1">
<obj_property name="ElementShortName">qb[7:0]</obj_property>
<obj_property name="ObjectShortName">qb[7:0]</obj_property>
</wvobject>
</wave_config>