Browse Source

Test ALU + COP + AFC ok

Foussats Morgane 6 months ago
parent
commit
c06ce09028
66 changed files with 3856 additions and 247 deletions
  1. BIN
      interpreter/interpreter
  2. 22
    13
      xilinx/ALU/ALU.gise
  3. 10
    4
      xilinx/ALU/ALU.xise
  4. 8
    2
      xilinx/ALU/bm_instr.vhd
  5. 25
    21
      xilinx/ALU/fuse.log
  6. 0
    57
      xilinx/ALU/fuse.xmsgs
  7. 1
    1
      xilinx/ALU/fuseRelaunch.cmd
  8. 215
    0
      xilinx/ALU/iseconfig/processeur.xreport
  9. 27
    1
      xilinx/ALU/isim.log
  10. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
  11. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe
  12. 0
    29
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log
  13. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat
  14. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat
  15. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o
  16. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.lin64.o
  17. 6
    6
      xilinx/ALU/isim/isim_usage_statistics.html
  18. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat
  19. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat
  20. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat
  21. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat
  22. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
  23. 0
    0
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimcrash.log
  24. 29
    0
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log
  25. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat
  26. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe
  27. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1
  28. 964
    0
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.c
  29. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat
  30. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.lin64.o
  31. 31
    55
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.c
  32. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat
  33. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.lin64.o
  34. 181
    0
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.c
  35. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat
  36. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.lin64.o
  37. 2
    2
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c
  38. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat
  39. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o
  40. 116
    0
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c
  41. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat
  42. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.lin64.o
  43. 343
    0
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.c
  44. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat
  45. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.lin64.o
  46. 1195
    0
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c
  47. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat
  48. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o
  49. 7
    2
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/process_test_isim_beh.exe_main.c
  50. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/process_test_isim_beh.exe_main.lin64.o
  51. BIN
      xilinx/ALU/isim/work/alu.vdb
  52. BIN
      xilinx/ALU/isim/work/bm_data.vdb
  53. BIN
      xilinx/ALU/isim/work/bm_instr.vdb
  54. BIN
      xilinx/ALU/isim/work/br.vdb
  55. BIN
      xilinx/ALU/isim/work/pipeline.vdb
  56. BIN
      xilinx/ALU/isim/work/process_test.vdb
  57. BIN
      xilinx/ALU/isim/work/processeur.vdb
  58. 93
    0
      xilinx/ALU/process_test.vhd
  59. 7
    0
      xilinx/ALU/process_test_beh.prj
  60. BIN
      xilinx/ALU/process_test_isim_beh.exe
  61. BIN
      xilinx/ALU/process_test_isim_beh.wdb
  62. 48
    51
      xilinx/ALU/processeur.vhd
  63. 3
    3
      xilinx/ALU/processeur_summary.html
  64. 149
    0
      xilinx/ALU/tests/test_afc.wcfg
  65. 209
    0
      xilinx/ALU/tests/test_alu.wcfg
  66. 165
    0
      xilinx/ALU/tests/test_cop.wcfg

BIN
interpreter/interpreter View File


+ 22
- 13
xilinx/ALU/ALU.gise View File

@@ -34,6 +34,9 @@
34 34
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
35 35
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
36 36
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
37
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="process_test_beh.prj"/>
38
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="process_test_isim_beh.exe"/>
39
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="process_test_isim_beh.wdb"/>
37 40
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
38 41
   </files>
39 42
 
@@ -46,7 +49,7 @@
46 49
       <status xil_pn:value="SuccessfullyRun"/>
47 50
       <status xil_pn:value="ReadyToRun"/>
48 51
     </transform>
49
-    <transform xil_pn:end_ts="1620134567" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620134567">
52
+    <transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620641821">
50 53
       <status xil_pn:value="SuccessfullyRun"/>
51 54
       <status xil_pn:value="ReadyToRun"/>
52 55
       <outfile xil_pn:name="alu.vhd"/>
@@ -58,13 +61,14 @@
58 61
       <outfile xil_pn:name="br.vhd"/>
59 62
       <outfile xil_pn:name="br_test.vhd"/>
60 63
       <outfile xil_pn:name="pipeline.vhd"/>
64
+      <outfile xil_pn:name="process_test.vhd"/>
61 65
       <outfile xil_pn:name="processeur.vhd"/>
62 66
     </transform>
63
-    <transform xil_pn:end_ts="1620134030" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-182187785304845874" xil_pn:start_ts="1620134030">
67
+    <transform xil_pn:end_ts="1620632845" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6971558793754694324" xil_pn:start_ts="1620632845">
64 68
       <status xil_pn:value="SuccessfullyRun"/>
65 69
       <status xil_pn:value="ReadyToRun"/>
66 70
     </transform>
67
-    <transform xil_pn:end_ts="1620134030" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-5858825779926760884" xil_pn:start_ts="1620134030">
71
+    <transform xil_pn:end_ts="1620632845" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7480952545073688782" xil_pn:start_ts="1620632845">
68 72
       <status xil_pn:value="SuccessfullyRun"/>
69 73
       <status xil_pn:value="ReadyToRun"/>
70 74
     </transform>
@@ -72,7 +76,7 @@
72 76
       <status xil_pn:value="SuccessfullyRun"/>
73 77
       <status xil_pn:value="ReadyToRun"/>
74 78
     </transform>
75
-    <transform xil_pn:end_ts="1620134567" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620134567">
79
+    <transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620641821">
76 80
       <status xil_pn:value="SuccessfullyRun"/>
77 81
       <status xil_pn:value="ReadyToRun"/>
78 82
       <outfile xil_pn:name="alu.vhd"/>
@@ -84,20 +88,25 @@
84 88
       <outfile xil_pn:name="br.vhd"/>
85 89
       <outfile xil_pn:name="br_test.vhd"/>
86 90
       <outfile xil_pn:name="pipeline.vhd"/>
91
+      <outfile xil_pn:name="process_test.vhd"/>
87 92
       <outfile xil_pn:name="processeur.vhd"/>
88 93
     </transform>
89
-    <transform xil_pn:end_ts="1620134568" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6599872206167540207" xil_pn:start_ts="1620134567">
90
-      <status xil_pn:value="FailedRun"/>
94
+    <transform xil_pn:end_ts="1620641822" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1620641821">
95
+      <status xil_pn:value="SuccessfullyRun"/>
91 96
       <status xil_pn:value="ReadyToRun"/>
97
+      <outfile xil_pn:name="fuse.log"/>
98
+      <outfile xil_pn:name="isim"/>
99
+      <outfile xil_pn:name="isim.log"/>
100
+      <outfile xil_pn:name="process_test_beh.prj"/>
101
+      <outfile xil_pn:name="process_test_isim_beh.exe"/>
102
+      <outfile xil_pn:name="xilinxsim.ini"/>
92 103
     </transform>
93
-    <transform xil_pn:end_ts="1620126600" xil_pn:in_ck="7979285750144170844" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7763494978879218253" xil_pn:start_ts="1620126600">
94
-      <status xil_pn:value="AbortedRun"/>
104
+    <transform xil_pn:end_ts="1620641823" xil_pn:in_ck="482655878171119177" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1620641822">
105
+      <status xil_pn:value="SuccessfullyRun"/>
95 106
       <status xil_pn:value="ReadyToRun"/>
96
-      <status xil_pn:value="OutOfDateForInputs"/>
97
-      <status xil_pn:value="OutOfDateForProperties"/>
98
-      <status xil_pn:value="OutOfDateForPredecessor"/>
99
-      <status xil_pn:value="OutOfDateForced"/>
100
-      <status xil_pn:value="InputRemoved"/>
107
+      <outfile xil_pn:name="isim.cmd"/>
108
+      <outfile xil_pn:name="isim.log"/>
109
+      <outfile xil_pn:name="process_test_isim_beh.wdb"/>
101 110
     </transform>
102 111
   </transforms>
103 112
 

+ 10
- 4
xilinx/ALU/ALU.xise View File

@@ -63,6 +63,12 @@
63 63
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
64 64
       <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
65 65
     </file>
66
+    <file xil_pn:name="process_test.vhd" xil_pn:type="FILE_VHDL">
67
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
68
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="24"/>
69
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="24"/>
70
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="24"/>
71
+    </file>
66 72
   </files>
67 73
 
68 74
   <properties>
@@ -305,8 +311,8 @@
305 311
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
306 312
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
307 313
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
308
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/processeur" xil_pn:valueState="non-default"/>
309
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.processeur" xil_pn:valueState="non-default"/>
314
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/process_test" xil_pn:valueState="non-default"/>
315
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.process_test" xil_pn:valueState="non-default"/>
310 316
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
311 317
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
312 318
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -324,7 +330,7 @@
324 330
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
325 331
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
326 332
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
327
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.processeur" xil_pn:valueState="default"/>
333
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.process_test" xil_pn:valueState="default"/>
328 334
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
329 335
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
330 336
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -374,7 +380,7 @@
374 380
     <!--                                                                                  -->
375 381
     <!-- The following properties are for internal use only. These should not be modified.-->
376 382
     <!--                                                                                  -->
377
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|processeur|Behavioral" xil_pn:valueState="non-default"/>
383
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|process_test|behavior" xil_pn:valueState="non-default"/>
378 384
     <property xil_pn:name="PROP_DesignName" xil_pn:value="ALU" xil_pn:valueState="non-default"/>
379 385
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
380 386
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

+ 8
- 2
xilinx/ALU/bm_instr.vhd View File

@@ -32,8 +32,14 @@ end bm_instr;
32 32
 architecture Behavioral of bm_instr is
33 33
 
34 34
 type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
35
-signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
36
-
35
+-- instruction "00000110 00000001 00000110 00000000"
36
+--test afc
37
+--signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
38
+
39
+--test afc cop
40
+signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
41
+--test add
42
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
37 43
 begin
38 44
 
39 45
 		OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));

+ 25
- 21
xilinx/ALU/fuse.log View File

@@ -1,4 +1,4 @@
1
-Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_beh.prj work.processeur 
1
+Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test" 
2 2
 ISim O.87xd (signature 0x8ddf5b5d)
3 3
 Number of CPUs detected in this system: 12
4 4
 Turning on mult-threading, number of parallel sub-compilation jobs: 24 
@@ -9,23 +9,27 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU
9 9
 Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work
10 10
 Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
11 11
 Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work
12
-ERROR:HDLCompiler:32 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: <rst> is already declared in this region.
13
-ERROR:HDLCompiler:32 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: <clk> is already declared in this region.
14
-ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic <ip> is not declared in <bm_instr>
15
-ERROR:HDLCompiler:432 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal <in_addr> has no actual or default value.
16
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: <op_in> is not declared.
17
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: <a_in> is not declared.
18
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: <b_in> is not declared.
19
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: <c_in> is not declared.
20
-ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic <clk> is not declared in <pipeline>
21
-ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic <b_lidi_out> is not declared in <br>
22
-ERROR:HDLCompiler:432 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal <a_addr> has no actual or default value.
23
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: <op_in> is not declared.
24
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: <a_in> is not declared.
25
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: <b_in> is not declared.
26
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: <c_in> is not declared.
27
-ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic <clk> is not declared in <pipeline>
28
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: <a> is not declared.
29
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: <b> is not declared.
30
-ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: <ctrl_alu> is not declared.
31
-Sorry, too many errors..
12
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd" into library work
13
+Starting static elaboration
14
+Completed static elaboration
15
+Fuse Memory Usage: 98520 KB
16
+Fuse CPU Usage: 760 ms
17
+Compiling package standard
18
+Compiling package std_logic_1164
19
+Compiling package std_logic_arith
20
+Compiling package std_logic_unsigned
21
+Compiling package numeric_std
22
+Compiling architecture behavioral of entity bm_instr [bm_instr_default]
23
+Compiling architecture behavioral of entity pipeline [pipeline_default]
24
+Compiling architecture behavioral of entity br [br_default]
25
+Compiling architecture behavioral of entity alu [alu_default]
26
+Compiling architecture behavioral of entity bm_data [bm_data_default]
27
+Compiling architecture behavioral of entity processeur [processeur_default]
28
+Compiling architecture behavior of entity process_test
29
+Time Resolution for simulation is 1ps.
30
+Waiting for 1 sub-compilation(s) to finish...
31
+Compiled 18 VHDL Units
32
+Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe
33
+Fuse Memory Usage: 1723208 KB
34
+Fuse CPU Usage: 850 ms
35
+GCC CPU Usage: 120 ms

+ 0
- 57
xilinx/ALU/fuse.xmsgs View File

@@ -5,62 +5,5 @@
5 5
      behavior or data corruption.  It is strongly advised that
6 6
      users do not edit the contents of this file. -->
7 7
 <messages>
8
-<msg type="error" file="HDLCompiler" num="32" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: &lt;<arg fmt="%s" index="1">rst</arg>&gt; is already declared in this region.
9
-</msg>
10
-
11
-<msg type="error" file="HDLCompiler" num="32" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: &lt;<arg fmt="%s" index="1">clk</arg>&gt; is already declared in this region.
12
-</msg>
13
-
14
-<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic &lt;<arg fmt="%s" index="1">ip</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">bm_instr</arg>&gt;
15
-</msg>
16
-
17
-<msg type="error" file="HDLCompiler" num="432" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal &lt;<arg fmt="%s" index="1">in_addr</arg>&gt; has no actual or default value.
18
-</msg>
19
-
20
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: &lt;<arg fmt="%s" index="1">op_in</arg>&gt; is not declared.
21
-</msg>
22
-
23
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: &lt;<arg fmt="%s" index="1">a_in</arg>&gt; is not declared.
24
-</msg>
25
-
26
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: &lt;<arg fmt="%s" index="1">b_in</arg>&gt; is not declared.
27
-</msg>
28
-
29
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: &lt;<arg fmt="%s" index="1">c_in</arg>&gt; is not declared.
30
-</msg>
31
-
32
-<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic &lt;<arg fmt="%s" index="1">clk</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">pipeline</arg>&gt;
33
-</msg>
34
-
35
-<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic &lt;<arg fmt="%s" index="1">b_lidi_out</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">br</arg>&gt;
36
-</msg>
37
-
38
-<msg type="error" file="HDLCompiler" num="432" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal &lt;<arg fmt="%s" index="1">a_addr</arg>&gt; has no actual or default value.
39
-</msg>
40
-
41
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: &lt;<arg fmt="%s" index="1">op_in</arg>&gt; is not declared.
42
-</msg>
43
-
44
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: &lt;<arg fmt="%s" index="1">a_in</arg>&gt; is not declared.
45
-</msg>
46
-
47
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: &lt;<arg fmt="%s" index="1">b_in</arg>&gt; is not declared.
48
-</msg>
49
-
50
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: &lt;<arg fmt="%s" index="1">c_in</arg>&gt; is not declared.
51
-</msg>
52
-
53
-<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic &lt;<arg fmt="%s" index="1">clk</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">pipeline</arg>&gt;
54
-</msg>
55
-
56
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: &lt;<arg fmt="%s" index="1">a</arg>&gt; is not declared.
57
-</msg>
58
-
59
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: &lt;<arg fmt="%s" index="1">b</arg>&gt; is not declared.
60
-</msg>
61
-
62
-<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: &lt;<arg fmt="%s" index="1">ctrl_alu</arg>&gt; is not declared.
63
-</msg>
64
-
65 8
 </messages>
66 9
 

+ 1
- 1
xilinx/ALU/fuseRelaunch.cmd View File

@@ -1 +1 @@
1
--intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_beh.prj" "work.processeur" 
1
+-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test" 

+ 215
- 0
xilinx/ALU/iseconfig/processeur.xreport View File

@@ -0,0 +1,215 @@
1
+<?xml version='1.0' encoding='UTF-8'?>
2
+<report-views version="2.0" >
3
+ <header>
4
+  <DateModified>2021-05-10T10:47:06</DateModified>
5
+  <ModuleName>processeur</ModuleName>
6
+  <SummaryTimeStamp>Unknown</SummaryTimeStamp>
7
+  <SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath>
8
+  <ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU</ImplementationReportsDirectory>
9
+  <DateInitialized>2021-05-10T09:34:56</DateInitialized>
10
+  <EnableMessageFiltering>false</EnableMessageFiltering>
11
+ </header>
12
+ <body>
13
+  <viewgroup label="Design Overview" >
14
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="processeur_summary.html" label="Summary" >
15
+    <toc-item title="Design Overview" target="Design Overview" />
16
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
17
+    <toc-item title="Performance Summary" target="Performance Summary" />
18
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
19
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
20
+   </view>
21
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="processeur_envsettings.html" label="System Settings" />
22
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="processeur_map.xrpt" label="IOB Properties" />
23
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="processeur_map.xrpt" label="Control Set Information" />
24
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="processeur_map.xrpt" label="Module Level Utilization" />
25
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="processeur.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
26
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="processeur_par.xrpt" label="Pinout Report" />
27
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="processeur_par.xrpt" label="Clock Report" />
28
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="processeur.twx" label="Static Timing" />
29
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="processeur_html/fit/report.htm" label="CPLD Fitter Report" />
30
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="processeur_html/tim/report.htm" label="CPLD Timing Report" />
31
+  </viewgroup>
32
+  <viewgroup label="XPS Errors and Warnings" >
33
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
34
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
35
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
36
+  </viewgroup>
37
+  <viewgroup label="XPS Reports" >
38
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
39
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
40
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
41
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="processeur.log" label="System Log File" />
42
+  </viewgroup>
43
+  <viewgroup label="Errors and Warnings" >
44
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
45
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
46
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
47
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
48
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
49
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
50
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
51
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
52
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
53
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
54
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
55
+  </viewgroup>
56
+  <viewgroup label="Detailed Reports" >
57
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="processeur.syr" label="Synthesis Report" >
58
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
59
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
60
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
61
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
62
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
63
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
64
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
65
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
66
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
67
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
68
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
69
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
70
+    <toc-item title="Partition Report" target="   Partition Report     " />
71
+    <toc-item title="Final Report" target="   Final Report   " />
72
+    <toc-item title="Design Summary" target="   Design Summary   " />
73
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
74
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
75
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
76
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
77
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
78
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
79
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
80
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
81
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
82
+   </view>
83
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="processeur.srr" label="Synplify Report" />
84
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="processeur.prec_log" label="Precision Report" />
85
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="processeur.bld" label="Translation Report" >
86
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
87
+    <toc-item title="Command Line" target="Command Line:" />
88
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
89
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
90
+   </view>
91
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="processeur_map.mrp" label="Map Report" >
92
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
93
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
94
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
95
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
96
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
97
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
98
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
99
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
100
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
101
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
102
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
103
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
104
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
105
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
106
+   </view>
107
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="processeur.par" label="Place and Route Report" >
108
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
109
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
110
+    <toc-item title="Router Information" target="Starting Router" />
111
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
112
+    <toc-item title="Clock Report" target="Generating Clock Report" />
113
+    <toc-item title="Timing Results" target="Timing Score:" />
114
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
115
+   </view>
116
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="processeur.twr" label="Post-PAR Static Timing Report" >
117
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
118
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
119
+    <toc-item title="Informational Messages" target="INFO:" />
120
+    <toc-item title="Warning Messages" target="WARNING:" />
121
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
122
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
123
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
124
+    <toc-item title="Timing Summary" target="Timing summary:" />
125
+    <toc-item title="Trace Settings" target="Trace Settings:" />
126
+   </view>
127
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128
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
129
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
130
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131
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132
+   </view>
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134
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135
+    <toc-item title="Performance Summary" target="Performance Summary:" />
136
+   </view>
137
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="processeur.pwr" label="Power Report" >
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139
+    <toc-item title="Power summary" target="Power summary" />
140
+    <toc-item title="Thermal summary" target="Thermal summary" />
141
+   </view>
142
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143
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
144
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
145
+    <toc-item title="Final Summary" target="DRC detected" />
146
+   </view>
147
+  </viewgroup>
148
+  <viewgroup label="Secondary Reports" >
149
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
150
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151
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
152
+   </view>
153
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/processeur_translate.nlf" label="Post-Translate Simulation Model Report" >
154
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
155
+   </view>
156
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
157
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158
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
159
+    <toc-item title="Design Information" target="Design Information" />
160
+    <toc-item title="Design Summary" target="Design Summary" />
161
+   </view>
162
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163
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164
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
165
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
166
+    <toc-item title="Informational Messages" target="INFO:" />
167
+    <toc-item title="Warning Messages" target="WARNING:" />
168
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
169
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
170
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
171
+    <toc-item title="Timing Summary" target="Timing summary:" />
172
+    <toc-item title="Trace Settings" target="Trace Settings:" />
173
+   </view>
174
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175
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_map.psr" label="Physical Synthesis Report" >
176
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
177
+   </view>
178
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="processeur_pad.txt" label="Pad Report" >
179
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
180
+   </view>
181
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="processeur.unroutes" label="Unroutes Report" >
182
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
183
+   </view>
184
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_preroute.tsi" label="Post-Map Constraints Interaction Report" >
185
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
186
+   </view>
187
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.grf" label="Guide Results Report" />
188
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.dly" label="Asynchronous Delay Report" />
189
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.clk_rgn" label="Clock Region Report" />
190
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.tsi" label="Post-Place and Route Constraints Interaction Report" >
191
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
192
+   </view>
193
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
194
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/processeur_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
195
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_sta.nlf" label="Primetime Netlist Report" >
196
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
197
+   </view>
198
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="processeur.ibs" label="IBIS Model" >
199
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
200
+    <toc-item title="Component" target="Component " />
201
+   </view>
202
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.lck" label="Back-annotate Pin Report" >
203
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
204
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
205
+   </view>
206
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.lpc" label="Locked Pin Constraints" >
207
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
208
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
209
+   </view>
210
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/processeur_timesim.nlf" label="Post-Fit Simulation Model Report" />
211
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
212
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
213
+  </viewgroup>
214
+ </body>
215
+</report-views>

+ 27
- 1
xilinx/ALU/isim.log View File

@@ -1,5 +1,5 @@
1 1
 ISim log file
2
-Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.wdb 
2
+Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb 
3 3
 ISim O.87xd (signature 0x8ddf5b5d)
4 4
 WARNING: A WEBPACK license was found.
5 5
 WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
@@ -10,7 +10,13 @@ Time resolution is 1 ps
10 10
 # wave add /
11 11
 # run 1000 ns
12 12
 Simulator is doing circuit initialization process.
13
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
13 14
 Finished circuit initialization process.
15
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
16
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
17
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
18
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
19
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
14 20
 ISim O.87xd (signature 0x8ddf5b5d)
15 21
 WARNING: A WEBPACK license was found.
16 22
 WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
@@ -18,5 +24,25 @@ WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for
18 24
 This is a Lite version of ISim.
19 25
 # run 1000 ns
20 26
 Simulator is doing circuit initialization process.
27
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
21 28
 Finished circuit initialization process.
29
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
30
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
31
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
32
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
33
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
34
+ISim O.87xd (signature 0x8ddf5b5d)
35
+WARNING: A WEBPACK license was found.
36
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
37
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
38
+This is a Lite version of ISim.
39
+# run 1000 ns
40
+Simulator is doing circuit initialization process.
41
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
42
+Finished circuit initialization process.
43
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
44
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
45
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
46
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
47
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
22 48
 # exit 0

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe View File


+ 0
- 29
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log View File

@@ -1,29 +0,0 @@
1
-Command line:
2
-   bm_instr_test_isim_beh.exe
3
-     -simmode  gui
4
-     -simrunnum  0
5
-     -socket  58939
6
-
7
-Tue May  4 13:10:22 2021
8
-
9
-
10
- Elaboration Time: 0.01 sec
11
-
12
- Current Memory Usage: 187.593 Meg
13
-
14
- Total Signals          : 7
15
- Total Nets             : 8233
16
- Total Signal Drivers   : 3
17
- Total Blocks           : 6
18
- Total Primitive Blocks : 5
19
- Total Processes        : 3
20
- Total Traceable Variables  : 16
21
- Total Scalar Nets and Variables : 8735
22
-Total Line Count : 11
23
-
24
- Total Simulation Time: 0.03 sec
25
-
26
- Current Memory Usage: 263.094 Meg
27
-
28
-Tue May  4 13:11:03 2021
29
-

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat View File


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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat View File


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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o View File


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+ 6
- 6
xilinx/ALU/isim/isim_usage_statistics.html View File

@@ -2,14 +2,14 @@
2 2
 <xtag-section name="ISimStatistics">
3 3
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
4 4
 <TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
5
-<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>840 ms, 1722812 KB</xtag-isim-property-value></TD></TR>
5
+<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>850 ms, 1723208 KB</xtag-isim-property-value></TD></TR>
6 6
 
7
-<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>7</xtag-isim-property-value></TD></TR>
8
-<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>8233</xtag-isim-property-value></TD></TR>
9
-<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>6</xtag-isim-property-value></TD></TR>
10
-<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
7
+<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>109</xtag-isim-property-value></TD></TR>
8
+<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10695</xtag-isim-property-value></TD></TR>
9
+<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>14</xtag-isim-property-value></TD></TR>
10
+<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>31</xtag-isim-property-value></TD></TR>
11 11
 <TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
12
-<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 262041 KB</xtag-isim-property-value></TD></TR>
12
+<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.04 sec, 264146 KB</xtag-isim-property-value></TD></TR>
13 13
 <TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
14 14
 <TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
15 15
 </xtag-section>

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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimcrash.log → xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimcrash.log View File


+ 29
- 0
xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log View File

@@ -0,0 +1,29 @@
1
+Command line:
2
+   process_test_isim_beh.exe
3
+     -simmode  gui
4
+     -simrunnum  0
5
+     -socket  43981
6
+
7
+Mon May 10 12:31:07 2021
8
+
9
+
10
+ Elaboration Time: 0.01 sec
11
+
12
+ Current Memory Usage: 189.698 Meg
13
+
14
+ Total Signals          : 109
15
+ Total Nets             : 10695
16
+ Total Signal Drivers   : 44
17
+ Total Blocks           : 14
18
+ Total Primitive Blocks : 12
19
+ Total Processes        : 31
20
+ Total Traceable Variables  : 16
21
+ Total Scalar Nets and Variables : 11197
22
+Total Line Count : 66
23
+
24
+ Total Simulation Time: 0.04 sec
25
+
26
+ Current Memory Usage: 265.2 Meg
27
+
28
+Mon May 10 12:32:41 2021
29
+

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat View File


BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/tmp_save/_1 → xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1 View File


+ 964
- 0
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.c View File

@@ -0,0 +1,964 @@
1
+/**********************************************************************/
2
+/*   ____  ____                                                       */
3
+/*  /   /\/   /                                                       */
4
+/* /___/  \  /                                                        */
5
+/* \   \   \/                                                       */
6
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
+/*  /   /          All Right Reserved.                                 */
8
+/* /---/   /\                                                         */
9
+/* \   \  /  \                                                      */
10
+/*  \___\/\___\                                                    */
11
+/***********************************************************************/
12
+
13
+/* This file is designed for use with ISim build 0x8ddf5b5d */
14
+
15
+#define XSI_HIDE_SYMBOL_SPEC true
16
+#include "xsi.h"
17
+#include <memory.h>
18
+#ifdef __GNUC__
19
+#include <stdlib.h>
20
+#else
21
+#include <malloc.h>
22
+#define alloca _alloca
23
+#endif
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd";
25
+extern char *IEEE_P_2592010699;
26
+extern char *IEEE_P_3620187407;
27
+
28
+unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
29
+char *ieee_p_3620187407_sub_1496620905533613331_3965413181(char *, char *, char *, char *, char *, char *);
30
+char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *);
31
+char *ieee_p_3620187407_sub_1496620905533721142_3965413181(char *, char *, char *, char *, char *, char *);
32
+
33
+
34
+static void work_a_0832606739_3212880686_p_0(char *t0)
35
+{
36
+    char t5[16];
37
+    char t7[16];
38
+    char *t1;
39
+    char *t3;
40
+    char *t4;
41
+    char *t6;
42
+    char *t8;
43
+    char *t9;
44
+    int t10;
45
+    unsigned int t11;
46
+    unsigned char t12;
47
+    char *t13;
48
+    char *t14;
49
+    char *t15;
50
+    char *t16;
51
+    char *t17;
52
+    char *t18;
53
+
54
+LAB0:    xsi_set_current_line(54, ng0);
55
+
56
+LAB3:    t1 = (t0 + 11471);
57
+    t3 = (t0 + 1032U);
58
+    t4 = *((char **)t3);
59
+    t6 = ((IEEE_P_2592010699) + 4000);
60
+    t8 = (t7 + 0U);
61
+    t9 = (t8 + 0U);
62
+    *((int *)t9) = 0;
63
+    t9 = (t8 + 4U);
64
+    *((int *)t9) = 0;
65
+    t9 = (t8 + 8U);
66
+    *((int *)t9) = 1;
67
+    t10 = (0 - 0);
68
+    t11 = (t10 * 1);
69
+    t11 = (t11 + 1);
70
+    t9 = (t8 + 12U);
71
+    *((unsigned int *)t9) = t11;
72
+    t9 = (t0 + 11224U);
73
+    t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
74
+    t11 = (1U + 8U);
75
+    t12 = (9U != t11);
76
+    if (t12 == 1)
77
+        goto LAB5;
78
+
79
+LAB6:    t13 = (t0 + 7304);
80
+    t14 = (t13 + 56U);
81
+    t15 = *((char **)t14);
82
+    t16 = (t15 + 56U);
83
+    t17 = *((char **)t16);
84
+    memcpy(t17, t3, 9U);
85
+    xsi_driver_first_trans_fast(t13);
86
+
87
+LAB2:    t18 = (t0 + 7064);
88
+    *((int *)t18) = 1;
89
+
90
+LAB1:    return;
91
+LAB4:    goto LAB2;
92
+
93
+LAB5:    xsi_size_not_matching(9U, t11, 0);
94
+    goto LAB6;
95
+
96
+}
97
+
98
+static void work_a_0832606739_3212880686_p_1(char *t0)
99
+{
100
+    char t5[16];
101
+    char t7[16];
102
+    char *t1;
103
+    char *t3;
104
+    char *t4;
105
+    char *t6;
106
+    char *t8;
107
+    char *t9;
108
+    int t10;
109
+    unsigned int t11;
110
+    unsigned char t12;
111
+    char *t13;
112
+    char *t14;
113
+    char *t15;
114
+    char *t16;
115
+    char *t17;
116
+    char *t18;
117
+
118
+LAB0:    xsi_set_current_line(55, ng0);
119
+
120
+LAB3:    t1 = (t0 + 11472);
121
+    t3 = (t0 + 1192U);
122
+    t4 = *((char **)t3);
123
+    t6 = ((IEEE_P_2592010699) + 4000);
124
+    t8 = (t7 + 0U);
125
+    t9 = (t8 + 0U);
126
+    *((int *)t9) = 0;
127
+    t9 = (t8 + 4U);
128
+    *((int *)t9) = 0;
129
+    t9 = (t8 + 8U);
130
+    *((int *)t9) = 1;
131
+    t10 = (0 - 0);
132
+    t11 = (t10 * 1);
133
+    t11 = (t11 + 1);
134
+    t9 = (t8 + 12U);
135
+    *((unsigned int *)t9) = t11;
136
+    t9 = (t0 + 11240U);
137
+    t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
138
+    t11 = (1U + 8U);
139
+    t12 = (9U != t11);
140
+    if (t12 == 1)
141
+        goto LAB5;
142
+
143
+LAB6:    t13 = (t0 + 7368);
144
+    t14 = (t13 + 56U);
145
+    t15 = *((char **)t14);
146
+    t16 = (t15 + 56U);
147
+    t17 = *((char **)t16);
148
+    memcpy(t17, t3, 9U);
149
+    xsi_driver_first_trans_fast(t13);
150
+
151
+LAB2:    t18 = (t0 + 7080);
152
+    *((int *)t18) = 1;
153
+
154
+LAB1:    return;
155
+LAB4:    goto LAB2;
156
+
157
+LAB5:    xsi_size_not_matching(9U, t11, 0);
158
+    goto LAB6;
159
+
160
+}
161
+
162
+static void work_a_0832606739_3212880686_p_2(char *t0)
163
+{
164
+    char t1[16];
165
+    char *t2;
166
+    char *t3;
167
+    char *t4;
168
+    char *t5;
169
+    char *t6;
170
+    char *t7;
171
+    unsigned int t8;
172
+    unsigned int t9;
173
+    unsigned char t10;
174
+    char *t11;
175
+    char *t12;
176
+    char *t13;
177
+    char *t14;
178
+    char *t15;
179
+    char *t16;
180
+
181
+LAB0:    xsi_set_current_line(56, ng0);
182
+
183
+LAB3:    t2 = (t0 + 2312U);
184
+    t3 = *((char **)t2);
185
+    t2 = (t0 + 11288U);
186
+    t4 = (t0 + 2472U);
187
+    t5 = *((char **)t4);
188
+    t4 = (t0 + 11304U);
189
+    t6 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
190
+    t7 = (t1 + 12U);
191
+    t8 = *((unsigned int *)t7);
192
+    t9 = (1U * t8);
193
+    t10 = (9U != t9);
194
+    if (t10 == 1)
195
+        goto LAB5;
196
+
197
+LAB6:    t11 = (t0 + 7432);
198
+    t12 = (t11 + 56U);
199
+    t13 = *((char **)t12);
200
+    t14 = (t13 + 56U);
201
+    t15 = *((char **)t14);
202
+    memcpy(t15, t6, 9U);
203
+    xsi_driver_first_trans_fast(t11);
204
+
205
+LAB2:    t16 = (t0 + 7096);
206
+    *((int *)t16) = 1;
207
+
208
+LAB1:    return;
209
+LAB4:    goto LAB2;
210
+
211
+LAB5:    xsi_size_not_matching(9U, t9, 0);
212
+    goto LAB6;
213
+
214
+}
215
+
216
+static void work_a_0832606739_3212880686_p_3(char *t0)
217
+{
218
+    char t1[16];
219
+    char *t2;
220
+    char *t3;
221
+    char *t4;
222
+    char *t5;
223
+    char *t6;
224
+    char *t7;
225
+    unsigned int t8;
226
+    unsigned int t9;
227
+    unsigned char t10;
228
+    char *t11;
229
+    char *t12;
230
+    char *t13;
231
+    char *t14;
232
+    char *t15;
233
+    char *t16;
234
+
235
+LAB0:    xsi_set_current_line(57, ng0);
236
+
237
+LAB3:    t2 = (t0 + 2312U);
238
+    t3 = *((char **)t2);
239
+    t2 = (t0 + 11288U);
240
+    t4 = (t0 + 2472U);
241
+    t5 = *((char **)t4);
242
+    t4 = (t0 + 11304U);
243
+    t6 = ieee_p_3620187407_sub_1496620905533721142_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
244
+    t7 = (t1 + 12U);
245
+    t8 = *((unsigned int *)t7);
246
+    t9 = (1U * t8);
247
+    t10 = (9U != t9);
248
+    if (t10 == 1)
249
+        goto LAB5;
250
+
251
+LAB6:    t11 = (t0 + 7496);
252
+    t12 = (t11 + 56U);
253
+    t13 = *((char **)t12);
254
+    t14 = (t13 + 56U);
255
+    t15 = *((char **)t14);
256
+    memcpy(t15, t6, 9U);
257
+    xsi_driver_first_trans_fast(t11);
258
+
259
+LAB2:    t16 = (t0 + 7112);
260
+    *((int *)t16) = 1;
261
+
262
+LAB1:    return;
263
+LAB4:    goto LAB2;
264
+
265
+LAB5:    xsi_size_not_matching(9U, t9, 0);
266
+    goto LAB6;
267
+
268
+}
269
+
270
+static void work_a_0832606739_3212880686_p_4(char *t0)
271
+{
272
+    char t1[16];
273
+    char *t2;
274
+    char *t3;
275
+    char *t4;
276
+    char *t5;
277
+    char *t6;
278
+    char *t7;
279
+    unsigned int t8;
280
+    unsigned int t9;
281
+    unsigned char t10;
282
+    char *t11;
283
+    char *t12;
284
+    char *t13;
285
+    char *t14;
286
+    char *t15;
287
+    char *t16;
288
+
289
+LAB0:    xsi_set_current_line(58, ng0);
290
+
291
+LAB3:    t2 = (t0 + 1032U);
292
+    t3 = *((char **)t2);
293
+    t2 = (t0 + 11224U);
294
+    t4 = (t0 + 1192U);
295
+    t5 = *((char **)t4);
296
+    t4 = (t0 + 11240U);
297
+    t6 = ieee_p_3620187407_sub_1496620905533613331_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
298
+    t7 = (t1 + 12U);
299
+    t8 = *((unsigned int *)t7);
300
+    t9 = (1U * t8);
301
+    t10 = (16U != t9);
302
+    if (t10 == 1)
303
+        goto LAB5;
304
+
305
+LAB6:    t11 = (t0 + 7560);
306
+    t12 = (t11 + 56U);
307
+    t13 = *((char **)t12);
308
+    t14 = (t13 + 56U);
309
+    t15 = *((char **)t14);
310
+    memcpy(t15, t6, 16U);
311
+    xsi_driver_first_trans_fast(t11);
312
+
313
+LAB2:    t16 = (t0 + 7128);
314
+    *((int *)t16) = 1;
315
+
316
+LAB1:    return;
317
+LAB4:    goto LAB2;
318
+
319
+LAB5:    xsi_size_not_matching(16U, t9, 0);
320
+    goto LAB6;
321
+
322
+}
323
+
324
+static void work_a_0832606739_3212880686_p_5(char *t0)
325
+{
326
+    char t5[16];
327
+    char t23[16];
328
+    char t41[16];
329
+    char *t1;
330
+    char *t2;
331
+    char *t3;
332
+    char *t6;
333
+    char *t7;
334
+    int t8;
335
+    unsigned int t9;
336
+    unsigned char t10;
337
+    char *t11;
338
+    unsigned int t12;
339
+    unsigned int t13;
340
+    char *t14;
341
+    char *t15;
342
+    char *t16;
343
+    char *t17;
344
+    char *t18;
345
+    char *t19;
346
+    char *t20;
347
+    char *t21;
348
+    char *t24;
349
+    char *t25;
350
+    int t26;
351
+    unsigned int t27;
352
+    unsigned char t28;
353
+    char *t29;
354
+    unsigned int t30;
355
+    unsigned int t31;
356
+    char *t32;
357
+    char *t33;
358
+    char *t34;
359
+    char *t35;
360
+    char *t36;
361
+    char *t37;
362
+    char *t38;
363
+    char *t39;
364
+    char *t42;
365
+    char *t43;
366
+    int t44;
367
+    unsigned int t45;
368
+    unsigned char t46;
369
+    char *t47;
370
+    unsigned int t48;
371
+    unsigned int t49;
372
+    char *t50;
373
+    char *t51;
374
+    char *t52;
375
+    char *t53;
376
+    char *t54;
377
+    char *t55;
378
+    char *t56;
379
+    char *t57;
380
+    char *t58;
381
+    char *t59;
382
+    char *t60;
383
+    char *t61;
384
+    char *t62;
385
+
386
+LAB0:    xsi_set_current_line(60, ng0);
387
+    t1 = (t0 + 1352U);
388
+    t2 = *((char **)t1);
389
+    t1 = (t0 + 11256U);
390
+    t3 = (t0 + 11473);
391
+    t6 = (t5 + 0U);
392
+    t7 = (t6 + 0U);
393
+    *((int *)t7) = 0;
394
+    t7 = (t6 + 4U);
395
+    *((int *)t7) = 2;
396
+    t7 = (t6 + 8U);
397
+    *((int *)t7) = 1;
398
+    t8 = (2 - 0);
399
+    t9 = (t8 * 1);
400
+    t9 = (t9 + 1);
401
+    t7 = (t6 + 12U);
402
+    *((unsigned int *)t7) = t9;
403
+    t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
404
+    if (t10 != 0)
405
+        goto LAB3;
406
+
407
+LAB4:    t19 = (t0 + 1352U);
408
+    t20 = *((char **)t19);
409
+    t19 = (t0 + 11256U);
410
+    t21 = (t0 + 11476);
411
+    t24 = (t23 + 0U);
412
+    t25 = (t24 + 0U);
413
+    *((int *)t25) = 0;
414
+    t25 = (t24 + 4U);
415
+    *((int *)t25) = 2;
416
+    t25 = (t24 + 8U);
417
+    *((int *)t25) = 1;
418
+    t26 = (2 - 0);
419
+    t27 = (t26 * 1);
420
+    t27 = (t27 + 1);
421
+    t25 = (t24 + 12U);
422
+    *((unsigned int *)t25) = t27;
423
+    t28 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t20, t19, t21, t23);
424
+    if (t28 != 0)
425
+        goto LAB5;
426
+
427
+LAB6:    t37 = (t0 + 1352U);
428
+    t38 = *((char **)t37);
429
+    t37 = (t0 + 11256U);
430
+    t39 = (t0 + 11479);
431
+    t42 = (t41 + 0U);
432
+    t43 = (t42 + 0U);
433
+    *((int *)t43) = 0;
434
+    t43 = (t42 + 4U);
435
+    *((int *)t43) = 2;
436
+    t43 = (t42 + 8U);
437
+    *((int *)t43) = 1;
438
+    t44 = (2 - 0);
439
+    t45 = (t44 * 1);
440
+    t45 = (t45 + 1);
441
+    t43 = (t42 + 12U);
442
+    *((unsigned int *)t43) = t45;
443
+    t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t38, t37, t39, t41);
444
+    if (t46 != 0)
445
+        goto LAB7;
446
+
447
+LAB8:
448
+LAB9:    t55 = xsi_get_transient_memory(8U);
449
+    memset(t55, 0, 8U);
450
+    t56 = t55;
451
+    memset(t56, (unsigned char)2, 8U);
452
+    t57 = (t0 + 7624);
453
+    t58 = (t57 + 56U);
454
+    t59 = *((char **)t58);
455
+    t60 = (t59 + 56U);
456
+    t61 = *((char **)t60);
457
+    memcpy(t61, t55, 8U);
458
+    xsi_driver_first_trans_fast(t57);
459
+
460
+LAB2:    t62 = (t0 + 7144);
461
+    *((int *)t62) = 1;
462
+
463
+LAB1:    return;
464
+LAB3:    t7 = (t0 + 2632U);
465
+    t11 = *((char **)t7);
466
+    t9 = (8 - 7);
467
+    t12 = (t9 * 1U);
468
+    t13 = (0 + t12);
469
+    t7 = (t11 + t13);
470
+    t14 = (t0 + 7624);
471
+    t15 = (t14 + 56U);
472
+    t16 = *((char **)t15);
473
+    t17 = (t16 + 56U);
474
+    t18 = *((char **)t17);
475
+    memcpy(t18, t7, 8U);
476
+    xsi_driver_first_trans_fast(t14);
477
+    goto LAB2;
478
+
479
+LAB5:    t25 = (t0 + 2792U);
480
+    t29 = *((char **)t25);
481
+    t27 = (8 - 7);
482
+    t30 = (t27 * 1U);
483
+    t31 = (0 + t30);
484
+    t25 = (t29 + t31);
485
+    t32 = (t0 + 7624);
486
+    t33 = (t32 + 56U);
487
+    t34 = *((char **)t33);
488
+    t35 = (t34 + 56U);
489
+    t36 = *((char **)t35);
490
+    memcpy(t36, t25, 8U);
491
+    xsi_driver_first_trans_fast(t32);
492
+    goto LAB2;
493
+
494
+LAB7:    t43 = (t0 + 2952U);
495
+    t47 = *((char **)t43);
496
+    t45 = (15 - 7);
497
+    t48 = (t45 * 1U);
498
+    t49 = (0 + t48);
499
+    t43 = (t47 + t49);
500
+    t50 = (t0 + 7624);
501
+    t51 = (t50 + 56U);
502
+    t52 = *((char **)t51);
503
+    t53 = (t52 + 56U);
504
+    t54 = *((char **)t53);
505
+    memcpy(t54, t43, 8U);
506
+    xsi_driver_first_trans_fast(t50);
507
+    goto LAB2;
508
+
509
+LAB10:    goto LAB2;
510
+
511
+}
512
+
513
+static void work_a_0832606739_3212880686_p_6(char *t0)
514
+{
515
+    char t7[16];
516
+    char t13[16];
517
+    char t21[16];
518
+    unsigned char t1;
519
+    char *t2;
520
+    char *t3;
521
+    unsigned int t4;
522
+    unsigned int t5;
523
+    unsigned int t6;
524
+    char *t8;
525
+    char *t9;
526
+    int t10;
527
+    unsigned int t11;
528
+    char *t14;
529
+    char *t15;
530
+    int t16;
531
+    unsigned char t17;
532
+    char *t18;
533
+    char *t19;
534
+    char *t22;
535
+    char *t23;
536
+    int t24;
537
+    unsigned char t25;
538
+    char *t26;
539
+    char *t27;
540
+    char *t28;
541
+    char *t29;
542
+    char *t30;
543
+    char *t31;
544
+    char *t32;
545
+    char *t33;
546
+    char *t34;
547
+    char *t35;
548
+
549
+LAB0:    xsi_set_current_line(64, ng0);
550
+    t2 = (t0 + 2952U);
551
+    t3 = *((char **)t2);
552
+    t4 = (15 - 15);
553
+    t5 = (t4 * 1U);
554
+    t6 = (0 + t5);
555
+    t2 = (t3 + t6);
556
+    t8 = (t7 + 0U);
557
+    t9 = (t8 + 0U);
558
+    *((int *)t9) = 15;
559
+    t9 = (t8 + 4U);
560
+    *((int *)t9) = 8;
561
+    t9 = (t8 + 8U);
562
+    *((int *)t9) = -1;
563
+    t10 = (8 - 15);
564
+    t11 = (t10 * -1);
565
+    t11 = (t11 + 1);
566
+    t9 = (t8 + 12U);
567
+    *((unsigned int *)t9) = t11;
568
+    t9 = (t0 + 11482);
569
+    t14 = (t13 + 0U);
570
+    t15 = (t14 + 0U);
571
+    *((int *)t15) = 0;
572
+    t15 = (t14 + 4U);
573
+    *((int *)t15) = 7;
574
+    t15 = (t14 + 8U);
575
+    *((int *)t15) = 1;
576
+    t16 = (7 - 0);
577
+    t11 = (t16 * 1);
578
+    t11 = (t11 + 1);
579
+    t15 = (t14 + 12U);
580
+    *((unsigned int *)t15) = t11;
581
+    t17 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t2, t7, t9, t13);
582
+    if (t17 == 1)
583
+        goto LAB5;
584
+
585
+LAB6:    t1 = (unsigned char)0;
586
+
587
+LAB7:    if (t1 != 0)
588
+        goto LAB3;
589
+
590
+LAB4:
591
+LAB8:    t30 = (t0 + 7688);
592
+    t31 = (t30 + 56U);
593
+    t32 = *((char **)t31);
594
+    t33 = (t32 + 56U);
595
+    t34 = *((char **)t33);
596
+    *((unsigned char *)t34) = (unsigned char)2;
597
+    xsi_driver_first_trans_fast_port(t30);
598
+
599
+LAB2:    t35 = (t0 + 7160);
600
+    *((int *)t35) = 1;
601
+
602
+LAB1:    return;
603
+LAB3:    t23 = (t0 + 7688);
604
+    t26 = (t23 + 56U);
605
+    t27 = *((char **)t26);
606
+    t28 = (t27 + 56U);
607
+    t29 = *((char **)t28);
608
+    *((unsigned char *)t29) = (unsigned char)3;
609
+    xsi_driver_first_trans_fast_port(t23);
610
+    goto LAB2;
611
+
612
+LAB5:    t15 = (t0 + 1352U);
613
+    t18 = *((char **)t15);
614
+    t15 = (t0 + 11256U);
615
+    t19 = (t0 + 11490);
616
+    t22 = (t21 + 0U);
617
+    t23 = (t22 + 0U);
618
+    *((int *)t23) = 0;
619
+    t23 = (t22 + 4U);
620
+    *((int *)t23) = 2;
621
+    t23 = (t22 + 8U);
622
+    *((int *)t23) = 1;
623
+    t24 = (2 - 0);
624
+    t11 = (t24 * 1);
625
+    t11 = (t11 + 1);
626
+    t23 = (t22 + 12U);
627
+    *((unsigned int *)t23) = t11;
628
+    t25 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t18, t15, t19, t21);
629
+    t1 = t25;
630
+    goto LAB7;
631
+
632
+LAB9:    goto LAB2;
633
+
634
+}
635
+
636
+static void work_a_0832606739_3212880686_p_7(char *t0)
637
+{
638
+    char t14[16];
639
+    unsigned char t1;
640
+    char *t2;
641
+    char *t3;
642
+    int t4;
643
+    unsigned int t5;
644
+    unsigned int t6;
645
+    unsigned int t7;
646
+    unsigned char t8;
647
+    unsigned char t9;
648
+    char *t10;
649
+    char *t11;
650
+    char *t12;
651
+    char *t15;
652
+    char *t16;
653
+    int t17;
654
+    unsigned int t18;
655
+    unsigned char t19;
656
+    char *t20;
657
+    char *t21;
658
+    char *t22;
659
+    char *t23;
660
+    char *t24;
661
+    char *t25;
662
+    char *t26;
663
+    char *t27;
664
+    char *t28;
665
+    char *t29;
666
+
667
+LAB0:    xsi_set_current_line(66, ng0);
668
+    t2 = (t0 + 2632U);
669
+    t3 = *((char **)t2);
670
+    t4 = (8 - 8);
671
+    t5 = (t4 * -1);
672
+    t6 = (1U * t5);
673
+    t7 = (0 + t6);
674
+    t2 = (t3 + t7);
675
+    t8 = *((unsigned char *)t2);
676
+    t9 = (t8 == (unsigned char)3);
677
+    if (t9 == 1)
678
+        goto LAB5;
679
+
680
+LAB6:    t1 = (unsigned char)0;
681
+
682
+LAB7:    if (t1 != 0)
683
+        goto LAB3;
684
+
685
+LAB4:
686
+LAB8:    t24 = (t0 + 7752);
687
+    t25 = (t24 + 56U);
688
+    t26 = *((char **)t25);
689
+    t27 = (t26 + 56U);
690
+    t28 = *((char **)t27);
691
+    *((unsigned char *)t28) = (unsigned char)2;
692
+    xsi_driver_first_trans_fast_port(t24);
693
+
694
+LAB2:    t29 = (t0 + 7176);
695
+    *((int *)t29) = 1;
696
+
697
+LAB1:    return;
698
+LAB3:    t16 = (t0 + 7752);
699
+    t20 = (t16 + 56U);
700
+    t21 = *((char **)t20);
701
+    t22 = (t21 + 56U);
702
+    t23 = *((char **)t22);
703
+    *((unsigned char *)t23) = (unsigned char)3;
704
+    xsi_driver_first_trans_fast_port(t16);
705
+    goto LAB2;
706
+
707
+LAB5:    t10 = (t0 + 1352U);
708
+    t11 = *((char **)t10);
709
+    t10 = (t0 + 11256U);
710
+    t12 = (t0 + 11493);
711
+    t15 = (t14 + 0U);
712
+    t16 = (t15 + 0U);
713
+    *((int *)t16) = 0;
714
+    t16 = (t15 + 4U);
715
+    *((int *)t16) = 2;
716
+    t16 = (t15 + 8U);
717
+    *((int *)t16) = 1;
718
+    t17 = (2 - 0);
719
+    t18 = (t17 * 1);
720
+    t18 = (t18 + 1);
721
+    t16 = (t15 + 12U);
722
+    *((unsigned int *)t16) = t18;
723
+    t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
724
+    t1 = t19;
725
+    goto LAB7;
726
+
727
+LAB9:    goto LAB2;
728
+
729
+}
730
+
731
+static void work_a_0832606739_3212880686_p_8(char *t0)
732
+{
733
+    char t14[16];
734
+    unsigned char t1;
735
+    char *t2;
736
+    char *t3;
737
+    int t4;
738
+    unsigned int t5;
739
+    unsigned int t6;
740
+    unsigned int t7;
741
+    unsigned char t8;
742
+    unsigned char t9;
743
+    char *t10;
744
+    char *t11;
745
+    char *t12;
746
+    char *t15;
747
+    char *t16;
748
+    int t17;
749
+    unsigned int t18;
750
+    unsigned char t19;
751
+    char *t20;
752
+    char *t21;
753
+    char *t22;
754
+    char *t23;
755
+    char *t24;
756
+    char *t25;
757
+    char *t26;
758
+    char *t27;
759
+    char *t28;
760
+    char *t29;
761
+
762
+LAB0:    xsi_set_current_line(68, ng0);
763
+    t2 = (t0 + 2792U);
764
+    t3 = *((char **)t2);
765
+    t4 = (8 - 8);
766
+    t5 = (t4 * -1);
767
+    t6 = (1U * t5);
768
+    t7 = (0 + t6);
769
+    t2 = (t3 + t7);
770
+    t8 = *((unsigned char *)t2);
771
+    t9 = (t8 == (unsigned char)3);
772
+    if (t9 == 1)
773
+        goto LAB5;
774
+
775
+LAB6:    t1 = (unsigned char)0;
776
+
777
+LAB7:    if (t1 != 0)
778
+        goto LAB3;
779
+
780
+LAB4:
781
+LAB8:    t24 = (t0 + 7816);
782
+    t25 = (t24 + 56U);
783
+    t26 = *((char **)t25);
784
+    t27 = (t26 + 56U);
785
+    t28 = *((char **)t27);
786
+    *((unsigned char *)t28) = (unsigned char)2;
787
+    xsi_driver_first_trans_fast_port(t24);
788
+
789
+LAB2:    t29 = (t0 + 7192);
790
+    *((int *)t29) = 1;
791
+
792
+LAB1:    return;
793
+LAB3:    t16 = (t0 + 7816);
794
+    t20 = (t16 + 56U);
795
+    t21 = *((char **)t20);
796
+    t22 = (t21 + 56U);
797
+    t23 = *((char **)t22);
798
+    *((unsigned char *)t23) = (unsigned char)3;
799
+    xsi_driver_first_trans_fast_port(t16);
800
+    goto LAB2;
801
+
802
+LAB5:    t10 = (t0 + 1352U);
803
+    t11 = *((char **)t10);
804
+    t10 = (t0 + 11256U);
805
+    t12 = (t0 + 11496);
806
+    t15 = (t14 + 0U);
807
+    t16 = (t15 + 0U);
808
+    *((int *)t16) = 0;
809
+    t16 = (t15 + 4U);
810
+    *((int *)t16) = 2;
811
+    t16 = (t15 + 8U);
812
+    *((int *)t16) = 1;
813
+    t17 = (2 - 0);
814
+    t18 = (t17 * 1);
815
+    t18 = (t18 + 1);
816
+    t16 = (t15 + 12U);
817
+    *((unsigned int *)t16) = t18;
818
+    t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
819
+    t1 = t19;
820
+    goto LAB7;
821
+
822
+LAB9:    goto LAB2;
823
+
824
+}
825
+
826
+static void work_a_0832606739_3212880686_p_9(char *t0)
827
+{
828
+    char t6[16];
829
+    char t15[16];
830
+    unsigned char t1;
831
+    char *t2;
832
+    char *t3;
833
+    char *t4;
834
+    char *t7;
835
+    char *t8;
836
+    int t9;
837
+    unsigned int t10;
838
+    unsigned char t11;
839
+    char *t12;
840
+    char *t13;
841
+    char *t16;
842
+    char *t17;
843
+    int t18;
844
+    unsigned char t19;
845
+    char *t20;
846
+    char *t21;
847
+    char *t22;
848
+    char *t23;
849
+    char *t24;
850
+    char *t25;
851
+    char *t26;
852
+    char *t27;
853
+    char *t28;
854
+    char *t29;
855
+
856
+LAB0:    xsi_set_current_line(70, ng0);
857
+    t2 = (t0 + 3112U);
858
+    t3 = *((char **)t2);
859
+    t2 = (t0 + 11368U);
860
+    t4 = (t0 + 11499);
861
+    t7 = (t6 + 0U);
862
+    t8 = (t7 + 0U);
863
+    *((int *)t8) = 0;
864
+    t8 = (t7 + 4U);
865
+    *((int *)t8) = 7;
866
+    t8 = (t7 + 8U);
867
+    *((int *)t8) = 1;
868
+    t9 = (7 - 0);
869
+    t10 = (t9 * 1);
870
+    t10 = (t10 + 1);
871
+    t8 = (t7 + 12U);
872
+    *((unsigned int *)t8) = t10;
873
+    t11 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t3, t2, t4, t6);
874
+    if (t11 == 1)
875
+        goto LAB5;
876
+
877
+LAB6:    t1 = (unsigned char)0;
878
+
879
+LAB7:    if (t1 != 0)
880
+        goto LAB3;
881
+
882
+LAB4:
883
+LAB8:    t24 = (t0 + 7880);
884
+    t25 = (t24 + 56U);
885
+    t26 = *((char **)t25);
886
+    t27 = (t26 + 56U);
887
+    t28 = *((char **)t27);
888
+    *((unsigned char *)t28) = (unsigned char)2;
889
+    xsi_driver_first_trans_fast_port(t24);
890
+
891
+LAB2:    t29 = (t0 + 7208);
892
+    *((int *)t29) = 1;
893
+
894
+LAB1:    return;
895
+LAB3:    t17 = (t0 + 7880);
896
+    t20 = (t17 + 56U);
897
+    t21 = *((char **)t20);
898
+    t22 = (t21 + 56U);
899
+    t23 = *((char **)t22);
900
+    *((unsigned char *)t23) = (unsigned char)3;
901
+    xsi_driver_first_trans_fast_port(t17);
902
+    goto LAB2;
903
+
904
+LAB5:    t8 = (t0 + 1352U);
905
+    t12 = *((char **)t8);
906
+    t8 = (t0 + 11256U);
907
+    t13 = (t0 + 11507);
908
+    t16 = (t15 + 0U);
909
+    t17 = (t16 + 0U);
910
+    *((int *)t17) = 0;
911
+    t17 = (t16 + 4U);
912
+    *((int *)t17) = 2;
913
+    t17 = (t16 + 8U);
914
+    *((int *)t17) = 1;
915
+    t18 = (2 - 0);
916
+    t10 = (t18 * 1);
917
+    t10 = (t10 + 1);
918
+    t17 = (t16 + 12U);
919
+    *((unsigned int *)t17) = t10;
920
+    t19 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t12, t8, t13, t15);
921
+    t1 = t19;
922
+    goto LAB7;
923
+
924
+LAB9:    goto LAB2;
925
+
926
+}
927
+
928
+static void work_a_0832606739_3212880686_p_10(char *t0)
929
+{
930
+    char *t1;
931
+    char *t2;
932
+    char *t3;
933
+    char *t4;
934
+    char *t5;
935
+    char *t6;
936
+    char *t7;
937
+
938
+LAB0:    xsi_set_current_line(72, ng0);
939
+
940
+LAB3:    t1 = (t0 + 3112U);
941
+    t2 = *((char **)t1);
942
+    t1 = (t0 + 7944);
943
+    t3 = (t1 + 56U);
944
+    t4 = *((char **)t3);
945
+    t5 = (t4 + 56U);
946
+    t6 = *((char **)t5);
947
+    memcpy(t6, t2, 8U);
948
+    xsi_driver_first_trans_fast_port(t1);
949
+
950
+LAB2:    t7 = (t0 + 7224);
951
+    *((int *)t7) = 1;
952
+
953
+LAB1:    return;
954
+LAB4:    goto LAB2;
955
+
956
+}
957
+
958
+
959
+extern void work_a_0832606739_3212880686_init()
960
+{
961
+	static char *pe[] = {(void *)work_a_0832606739_3212880686_p_0,(void *)work_a_0832606739_3212880686_p_1,(void *)work_a_0832606739_3212880686_p_2,(void *)work_a_0832606739_3212880686_p_3,(void *)work_a_0832606739_3212880686_p_4,(void *)work_a_0832606739_3212880686_p_5,(void *)work_a_0832606739_3212880686_p_6,(void *)work_a_0832606739_3212880686_p_7,(void *)work_a_0832606739_3212880686_p_8,(void *)work_a_0832606739_3212880686_p_9,(void *)work_a_0832606739_3212880686_p_10};
962
+	xsi_register_didat("work_a_0832606739_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat");
963
+	xsi_register_executes(pe);
964
+}

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat View File


BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.lin64.o View File


xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c → xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.c View File

@@ -21,11 +21,11 @@
21 21
 #include <malloc.h>
22 22
 #define alloca _alloca
23 23
 #endif
24
-static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd";
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd";
25 25
 
26 26
 
27 27
 
28
-static void work_a_4060154216_2372691052_p_0(char *t0)
28
+static void work_a_1229531095_2372691052_p_0(char *t0)
29 29
 {
30 30
     char *t1;
31 31
     char *t2;
@@ -36,46 +36,46 @@ static void work_a_4060154216_2372691052_p_0(char *t0)
36 36
     int64 t7;
37 37
     int64 t8;
38 38
 
39
-LAB0:    t1 = (t0 + 2624U);
39
+LAB0:    t1 = (t0 + 2464U);
40 40
     t2 = *((char **)t1);
41 41
     if (t2 == 0)
42 42
         goto LAB2;
43 43
 
44 44
 LAB3:    goto *t2;
45 45
 
46
-LAB2:    xsi_set_current_line(73, ng0);
47
-    t2 = (t0 + 3256);
46
+LAB2:    xsi_set_current_line(68, ng0);
47
+    t2 = (t0 + 3096);
48 48
     t3 = (t2 + 56U);
49 49
     t4 = *((char **)t3);
50 50
     t5 = (t4 + 56U);
51 51
     t6 = *((char **)t5);
52 52
     *((unsigned char *)t6) = (unsigned char)2;
53 53
     xsi_driver_first_trans_fast(t2);
54
-    xsi_set_current_line(74, ng0);
55
-    t2 = (t0 + 1648U);
54
+    xsi_set_current_line(69, ng0);
55
+    t2 = (t0 + 1488U);
56 56
     t3 = *((char **)t2);
57 57
     t7 = *((int64 *)t3);
58 58
     t8 = (t7 / 2);
59
-    t2 = (t0 + 2432);
59
+    t2 = (t0 + 2272);
60 60
     xsi_process_wait(t2, t8);
61 61
 
62 62
 LAB6:    *((char **)t1) = &&LAB7;
63 63
 
64 64
 LAB1:    return;
65
-LAB4:    xsi_set_current_line(75, ng0);
66
-    t2 = (t0 + 3256);
65
+LAB4:    xsi_set_current_line(70, ng0);
66
+    t2 = (t0 + 3096);
67 67
     t3 = (t2 + 56U);
68 68
     t4 = *((char **)t3);
69 69
     t5 = (t4 + 56U);
70 70
     t6 = *((char **)t5);
71 71
     *((unsigned char *)t6) = (unsigned char)3;
72 72
     xsi_driver_first_trans_fast(t2);
73
-    xsi_set_current_line(76, ng0);
74
-    t2 = (t0 + 1648U);
73
+    xsi_set_current_line(71, ng0);
74
+    t2 = (t0 + 1488U);
75 75
     t3 = *((char **)t2);
76 76
     t7 = *((int64 *)t3);
77 77
     t8 = (t7 / 2);
78
-    t2 = (t0 + 2432);
78
+    t2 = (t0 + 2272);
79 79
     xsi_process_wait(t2, t8);
80 80
 
81 81
 LAB10:    *((char **)t1) = &&LAB11;
@@ -93,7 +93,7 @@ LAB11:    goto LAB9;
93 93
 
94 94
 }
95 95
 
96
-static void work_a_4060154216_2372691052_p_1(char *t0)
96
+static void work_a_1229531095_2372691052_p_1(char *t0)
97 97
 {
98 98
     char *t1;
99 99
     char *t2;
@@ -103,30 +103,28 @@ static void work_a_4060154216_2372691052_p_1(char *t0)
103 103
     char *t6;
104 104
     char *t7;
105 105
     char *t8;
106
-    char *t9;
107
-    char *t10;
108 106
 
109
-LAB0:    t1 = (t0 + 2872U);
107
+LAB0:    t1 = (t0 + 2712U);
110 108
     t2 = *((char **)t1);
111 109
     if (t2 == 0)
112 110
         goto LAB2;
113 111
 
114 112
 LAB3:    goto *t2;
115 113
 
116
-LAB2:    xsi_set_current_line(84, ng0);
114
+LAB2:    xsi_set_current_line(79, ng0);
117 115
     t3 = (100 * 1000LL);
118
-    t2 = (t0 + 2680);
116
+    t2 = (t0 + 2520);
119 117
     xsi_process_wait(t2, t3);
120 118
 
121 119
 LAB6:    *((char **)t1) = &&LAB7;
122 120
 
123 121
 LAB1:    return;
124
-LAB4:    xsi_set_current_line(86, ng0);
125
-    t2 = (t0 + 1648U);
122
+LAB4:    xsi_set_current_line(81, ng0);
123
+    t2 = (t0 + 1488U);
126 124
     t4 = *((char **)t2);
127 125
     t3 = *((int64 *)t4);
128 126
     t5 = (t3 * 10);
129
-    t2 = (t0 + 2680);
127
+    t2 = (t0 + 2520);
130 128
     xsi_process_wait(t2, t5);
131 129
 
132 130
 LAB10:    *((char **)t1) = &&LAB11;
@@ -136,19 +134,15 @@ LAB5:    goto LAB4;
136 134
 
137 135
 LAB7:    goto LAB5;
138 136
 
139
-LAB8:    xsi_set_current_line(88, ng0);
140
-    t2 = (t0 + 5568);
141
-    t6 = (t0 + 3320);
137
+LAB8:    xsi_set_current_line(86, ng0);
138
+    t2 = (t0 + 3160);
139
+    t4 = (t2 + 56U);
140
+    t6 = *((char **)t4);
142 141
     t7 = (t6 + 56U);
143 142
     t8 = *((char **)t7);
144
-    t9 = (t8 + 56U);
145
-    t10 = *((char **)t9);
146
-    memcpy(t10, t2, 8U);
147
-    xsi_driver_first_trans_fast(t6);
148
-    xsi_set_current_line(89, ng0);
149
-    t3 = (100 * 1000LL);
150
-    t2 = (t0 + 2680);
151
-    xsi_process_wait(t2, t3);
143
+    *((unsigned char *)t8) = (unsigned char)3;
144
+    xsi_driver_first_trans_fast(t2);
145
+    xsi_set_current_line(90, ng0);
152 146
 
153 147
 LAB14:    *((char **)t1) = &&LAB15;
154 148
     goto LAB1;
@@ -157,36 +151,18 @@ LAB9:    goto LAB8;
157 151
 
158 152
 LAB11:    goto LAB9;
159 153
 
160
-LAB12:    xsi_set_current_line(91, ng0);
161
-    t2 = (t0 + 5576);
162
-    t6 = (t0 + 3320);
163
-    t7 = (t6 + 56U);
164
-    t8 = *((char **)t7);
165
-    t9 = (t8 + 56U);
166
-    t10 = *((char **)t9);
167
-    memcpy(t10, t2, 8U);
168
-    xsi_driver_first_trans_fast(t6);
169
-    xsi_set_current_line(94, ng0);
170
-
171
-LAB18:    *((char **)t1) = &&LAB19;
172
-    goto LAB1;
154
+LAB12:    goto LAB2;
173 155
 
174 156
 LAB13:    goto LAB12;
175 157
 
176 158
 LAB15:    goto LAB13;
177 159
 
178
-LAB16:    goto LAB2;
179
-
180
-LAB17:    goto LAB16;
181
-
182
-LAB19:    goto LAB17;
183
-
184 160
 }
185 161
 
186 162
 
187
-extern void work_a_4060154216_2372691052_init()
163
+extern void work_a_1229531095_2372691052_init()
188 164
 {
189
-	static char *pe[] = {(void *)work_a_4060154216_2372691052_p_0,(void *)work_a_4060154216_2372691052_p_1};
190
-	xsi_register_didat("work_a_4060154216_2372691052", "isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat");
165
+	static char *pe[] = {(void *)work_a_1229531095_2372691052_p_0,(void *)work_a_1229531095_2372691052_p_1};
166
+	xsi_register_didat("work_a_1229531095_2372691052", "isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat");
191 167
 	xsi_register_executes(pe);
192 168
 }

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat View File


BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.lin64.o View File


+ 181
- 0
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.c View File

@@ -0,0 +1,181 @@
1
+/**********************************************************************/
2
+/*   ____  ____                                                       */
3
+/*  /   /\/   /                                                       */
4
+/* /___/  \  /                                                        */
5
+/* \   \   \/                                                       */
6
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
+/*  /   /          All Right Reserved.                                 */
8
+/* /---/   /\                                                         */
9
+/* \   \  /  \                                                      */
10
+/*  \___\/\___\                                                    */
11
+/***********************************************************************/
12
+
13
+/* This file is designed for use with ISim build 0x8ddf5b5d */
14
+
15
+#define XSI_HIDE_SYMBOL_SPEC true
16
+#include "xsi.h"
17
+#include <memory.h>
18
+#ifdef __GNUC__
19
+#include <stdlib.h>
20
+#else
21
+#include <malloc.h>
22
+#define alloca _alloca
23
+#endif
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd";
25
+extern char *IEEE_P_2592010699;
26
+extern char *IEEE_P_1242562249;
27
+
28
+int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
29
+unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
30
+
31
+
32
+static void work_a_1466808984_3212880686_p_0(char *t0)
33
+{
34
+    char *t1;
35
+    char *t2;
36
+    char *t3;
37
+    unsigned char t4;
38
+    char *t5;
39
+    unsigned char t6;
40
+    char *t7;
41
+    int t8;
42
+    int t9;
43
+    unsigned int t10;
44
+    unsigned int t11;
45
+    unsigned int t12;
46
+    char *t13;
47
+    char *t14;
48
+    char *t15;
49
+    char *t16;
50
+    char *t17;
51
+    char *t18;
52
+    unsigned char t19;
53
+
54
+LAB0:    t1 = (t0 + 3144U);
55
+    t2 = *((char **)t1);
56
+    if (t2 == 0)
57
+        goto LAB2;
58
+
59
+LAB3:    goto *t2;
60
+
61
+LAB2:    xsi_set_current_line(42, ng0);
62
+
63
+LAB6:    t2 = (t0 + 3464);
64
+    *((int *)t2) = 1;
65
+    *((char **)t1) = &&LAB7;
66
+
67
+LAB1:    return;
68
+LAB4:    t5 = (t0 + 3464);
69
+    *((int *)t5) = 0;
70
+    xsi_set_current_line(43, ng0);
71
+    t2 = (t0 + 1352U);
72
+    t3 = *((char **)t2);
73
+    t4 = *((unsigned char *)t3);
74
+    t6 = (t4 == (unsigned char)3);
75
+    if (t6 != 0)
76
+        goto LAB8;
77
+
78
+LAB10:    xsi_set_current_line(46, ng0);
79
+    t2 = (t0 + 1192U);
80
+    t3 = *((char **)t2);
81
+    t2 = (t0 + 1032U);
82
+    t5 = *((char **)t2);
83
+    t2 = (t0 + 5968U);
84
+    t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t5, t2);
85
+    t9 = (t8 - 0);
86
+    t10 = (t9 * 1);
87
+    t11 = (8U * t10);
88
+    t12 = (0U + t11);
89
+    t7 = (t0 + 3608);
90
+    t13 = (t7 + 56U);
91
+    t14 = *((char **)t13);
92
+    t15 = (t14 + 56U);
93
+    t16 = *((char **)t15);
94
+    memcpy(t16, t3, 8U);
95
+    xsi_driver_first_trans_delta(t7, t12, 8U, 0LL);
96
+
97
+LAB9:    xsi_set_current_line(48, ng0);
98
+    t2 = (t0 + 1512U);
99
+    t3 = *((char **)t2);
100
+    t4 = *((unsigned char *)t3);
101
+    t6 = (t4 == (unsigned char)2);
102
+    if (t6 != 0)
103
+        goto LAB11;
104
+
105
+LAB13:
106
+LAB12:    goto LAB2;
107
+
108
+LAB5:    t3 = (t0 + 1632U);
109
+    t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
110
+    if (t4 == 1)
111
+        goto LAB4;
112
+    else
113
+        goto LAB6;
114
+
115
+LAB7:    goto LAB5;
116
+
117
+LAB8:    xsi_set_current_line(44, ng0);
118
+    t2 = (t0 + 1992U);
119
+    t5 = *((char **)t2);
120
+    t2 = (t0 + 1032U);
121
+    t7 = *((char **)t2);
122
+    t2 = (t0 + 5968U);
123
+    t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2);
124
+    t9 = (t8 - 0);
125
+    t10 = (t9 * 1);
126
+    xsi_vhdl_check_range_of_index(0, 255, 1, t8);
127
+    t11 = (8U * t10);
128
+    t12 = (0 + t11);
129
+    t13 = (t5 + t12);
130
+    t14 = (t0 + 3544);
131
+    t15 = (t14 + 56U);
132
+    t16 = *((char **)t15);
133
+    t17 = (t16 + 56U);
134
+    t18 = *((char **)t17);
135
+    memcpy(t18, t13, 8U);
136
+    xsi_driver_first_trans_fast_port(t14);
137
+    goto LAB9;
138
+
139
+LAB11:    xsi_set_current_line(49, ng0);
140
+    t2 = xsi_get_transient_memory(2048U);
141
+    memset(t2, 0, 2048U);
142
+    t5 = t2;
143
+    t7 = (t0 + 8123);
144
+    t19 = (8U != 0);
145
+    if (t19 == 1)
146
+        goto LAB14;
147
+
148
+LAB15:    t14 = (t0 + 3608);
149
+    t15 = (t14 + 56U);
150
+    t16 = *((char **)t15);
151
+    t17 = (t16 + 56U);
152
+    t18 = *((char **)t17);
153
+    memcpy(t18, t2, 2048U);
154
+    xsi_driver_first_trans_fast(t14);
155
+    xsi_set_current_line(50, ng0);
156
+    t2 = xsi_get_transient_memory(8U);
157
+    memset(t2, 0, 8U);
158
+    t3 = t2;
159
+    memset(t3, (unsigned char)2, 8U);
160
+    t5 = (t0 + 3544);
161
+    t7 = (t5 + 56U);
162
+    t13 = *((char **)t7);
163
+    t14 = (t13 + 56U);
164
+    t15 = *((char **)t14);
165
+    memcpy(t15, t2, 8U);
166
+    xsi_driver_first_trans_fast_port(t5);
167
+    goto LAB12;
168
+
169
+LAB14:    t10 = (2048U / 8U);
170
+    xsi_mem_set_data(t5, t7, 8U, t10);
171
+    goto LAB15;
172
+
173
+}
174
+
175
+
176
+extern void work_a_1466808984_3212880686_init()
177
+{
178
+	static char *pe[] = {(void *)work_a_1466808984_3212880686_p_0};
179
+	xsi_register_didat("work_a_1466808984_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat");
180
+	xsi_register_executes(pe);
181
+}

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat View File


BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.lin64.o View File


xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c → xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c View File

@@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0)
45 45
     char *t14;
46 46
     char *t15;
47 47
 
48
-LAB0:    xsi_set_current_line(39, ng0);
48
+LAB0:    xsi_set_current_line(45, ng0);
49 49
 
50 50
 LAB3:    t1 = (t0 + 1512U);
51 51
     t2 = *((char **)t1);
@@ -79,6 +79,6 @@ LAB4:    goto LAB2;
79 79
 extern void work_a_1802466774_3212880686_init()
80 80
 {
81 81
 	static char *pe[] = {(void *)work_a_1802466774_3212880686_p_0};
82
-	xsi_register_didat("work_a_1802466774_3212880686", "isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat");
82
+	xsi_register_didat("work_a_1802466774_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat");
83 83
 	xsi_register_executes(pe);
84 84
 }

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat → xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o → xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o View File


+ 116
- 0
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c View File

@@ -0,0 +1,116 @@
1
+/**********************************************************************/
2
+/*   ____  ____                                                       */
3
+/*  /   /\/   /                                                       */
4
+/* /___/  \  /                                                        */
5
+/* \   \   \/                                                       */
6
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
+/*  /   /          All Right Reserved.                                 */
8
+/* /---/   /\                                                         */
9
+/* \   \  /  \                                                      */
10
+/*  \___\/\___\                                                    */
11
+/***********************************************************************/
12
+
13
+/* This file is designed for use with ISim build 0x8ddf5b5d */
14
+
15
+#define XSI_HIDE_SYMBOL_SPEC true
16
+#include "xsi.h"
17
+#include <memory.h>
18
+#ifdef __GNUC__
19
+#include <stdlib.h>
20
+#else
21
+#include <malloc.h>
22
+#define alloca _alloca
23
+#endif
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd";
25
+extern char *IEEE_P_2592010699;
26
+
27
+unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
28
+
29
+
30
+static void work_a_3650175700_3212880686_p_0(char *t0)
31
+{
32
+    char *t1;
33
+    char *t2;
34
+    char *t3;
35
+    unsigned char t4;
36
+    char *t5;
37
+    char *t6;
38
+    char *t7;
39
+    char *t8;
40
+
41
+LAB0:    t1 = (t0 + 3464U);
42
+    t2 = *((char **)t1);
43
+    if (t2 == 0)
44
+        goto LAB2;
45
+
46
+LAB3:    goto *t2;
47
+
48
+LAB2:    xsi_set_current_line(49, ng0);
49
+
50
+LAB6:    t2 = (t0 + 3784);
51
+    *((int *)t2) = 1;
52
+    *((char **)t1) = &&LAB7;
53
+
54
+LAB1:    return;
55
+LAB4:    t5 = (t0 + 3784);
56
+    *((int *)t5) = 0;
57
+    xsi_set_current_line(50, ng0);
58
+    t2 = (t0 + 1032U);
59
+    t3 = *((char **)t2);
60
+    t2 = (t0 + 3864);
61
+    t5 = (t2 + 56U);
62
+    t6 = *((char **)t5);
63
+    t7 = (t6 + 56U);
64
+    t8 = *((char **)t7);
65
+    memcpy(t8, t3, 8U);
66
+    xsi_driver_first_trans_fast_port(t2);
67
+    xsi_set_current_line(51, ng0);
68
+    t2 = (t0 + 1192U);
69
+    t3 = *((char **)t2);
70
+    t2 = (t0 + 3928);
71
+    t5 = (t2 + 56U);
72
+    t6 = *((char **)t5);
73
+    t7 = (t6 + 56U);
74
+    t8 = *((char **)t7);
75
+    memcpy(t8, t3, 8U);
76
+    xsi_driver_first_trans_fast_port(t2);
77
+    xsi_set_current_line(52, ng0);
78
+    t2 = (t0 + 1352U);
79
+    t3 = *((char **)t2);
80
+    t2 = (t0 + 3992);
81
+    t5 = (t2 + 56U);
82
+    t6 = *((char **)t5);
83
+    t7 = (t6 + 56U);
84
+    t8 = *((char **)t7);
85
+    memcpy(t8, t3, 8U);
86
+    xsi_driver_first_trans_fast_port(t2);
87
+    xsi_set_current_line(53, ng0);
88
+    t2 = (t0 + 1512U);
89
+    t3 = *((char **)t2);
90
+    t2 = (t0 + 4056);
91
+    t5 = (t2 + 56U);
92
+    t6 = *((char **)t5);
93
+    t7 = (t6 + 56U);
94
+    t8 = *((char **)t7);
95
+    memcpy(t8, t3, 8U);
96
+    xsi_driver_first_trans_fast_port(t2);
97
+    goto LAB2;
98
+
99
+LAB5:    t3 = (t0 + 1632U);
100
+    t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
101
+    if (t4 == 1)
102
+        goto LAB4;
103
+    else
104
+        goto LAB6;
105
+
106
+LAB7:    goto LAB5;
107
+
108
+}
109
+
110
+
111
+extern void work_a_3650175700_3212880686_init()
112
+{
113
+	static char *pe[] = {(void *)work_a_3650175700_3212880686_p_0};
114
+	xsi_register_didat("work_a_3650175700_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat");
115
+	xsi_register_executes(pe);
116
+}

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat View File


BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.lin64.o View File


+ 343
- 0
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.c View File

@@ -0,0 +1,343 @@
1
+/**********************************************************************/
2
+/*   ____  ____                                                       */
3
+/*  /   /\/   /                                                       */
4
+/* /___/  \  /                                                        */
5
+/* \   \   \/                                                       */
6
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
+/*  /   /          All Right Reserved.                                 */
8
+/* /---/   /\                                                         */
9
+/* \   \  /  \                                                      */
10
+/*  \___\/\___\                                                    */
11
+/***********************************************************************/
12
+
13
+/* This file is designed for use with ISim build 0x8ddf5b5d */
14
+
15
+#define XSI_HIDE_SYMBOL_SPEC true
16
+#include "xsi.h"
17
+#include <memory.h>
18
+#ifdef __GNUC__
19
+#include <stdlib.h>
20
+#else
21
+#include <malloc.h>
22
+#define alloca _alloca
23
+#endif
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd";
25
+extern char *IEEE_P_2592010699;
26
+extern char *IEEE_P_1242562249;
27
+extern char *IEEE_P_3620187407;
28
+
29
+int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
30
+unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
31
+unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
32
+
33
+
34
+static void work_a_3998322972_3212880686_p_0(char *t0)
35
+{
36
+    char *t1;
37
+    char *t2;
38
+    char *t3;
39
+    unsigned char t4;
40
+    char *t5;
41
+    unsigned char t6;
42
+    char *t7;
43
+    int t8;
44
+    int t9;
45
+    unsigned int t10;
46
+    unsigned int t11;
47
+    unsigned int t12;
48
+    char *t13;
49
+    char *t14;
50
+    char *t15;
51
+    char *t16;
52
+    char *t17;
53
+    unsigned char t18;
54
+    char *t19;
55
+
56
+LAB0:    t1 = (t0 + 3624U);
57
+    t2 = *((char **)t1);
58
+    if (t2 == 0)
59
+        goto LAB2;
60
+
61
+LAB3:    goto *t2;
62
+
63
+LAB2:    xsi_set_current_line(47, ng0);
64
+
65
+LAB6:    t2 = (t0 + 4440);
66
+    *((int *)t2) = 1;
67
+    *((char **)t1) = &&LAB7;
68
+
69
+LAB1:    return;
70
+LAB4:    t5 = (t0 + 4440);
71
+    *((int *)t5) = 0;
72
+    xsi_set_current_line(48, ng0);
73
+    t2 = (t0 + 1512U);
74
+    t3 = *((char **)t2);
75
+    t4 = *((unsigned char *)t3);
76
+    t6 = (t4 == (unsigned char)3);
77
+    if (t6 != 0)
78
+        goto LAB8;
79
+
80
+LAB10:
81
+LAB9:    xsi_set_current_line(51, ng0);
82
+    t2 = (t0 + 1832U);
83
+    t3 = *((char **)t2);
84
+    t4 = *((unsigned char *)t3);
85
+    t6 = (t4 == (unsigned char)2);
86
+    if (t6 != 0)
87
+        goto LAB11;
88
+
89
+LAB13:
90
+LAB12:    goto LAB2;
91
+
92
+LAB5:    t3 = (t0 + 1952U);
93
+    t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
94
+    if (t4 == 1)
95
+        goto LAB4;
96
+    else
97
+        goto LAB6;
98
+
99
+LAB7:    goto LAB5;
100
+
101
+LAB8:    xsi_set_current_line(49, ng0);
102
+    t2 = (t0 + 1672U);
103
+    t5 = *((char **)t2);
104
+    t2 = (t0 + 1352U);
105
+    t7 = *((char **)t2);
106
+    t2 = (t0 + 7424U);
107
+    t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2);
108
+    t9 = (t8 - 0);
109
+    t10 = (t9 * 1);
110
+    t11 = (8U * t10);
111
+    t12 = (0U + t11);
112
+    t13 = (t0 + 4552);
113
+    t14 = (t13 + 56U);
114
+    t15 = *((char **)t14);
115
+    t16 = (t15 + 56U);
116
+    t17 = *((char **)t16);
117
+    memcpy(t17, t5, 8U);
118
+    xsi_driver_first_trans_delta(t13, t12, 8U, 0LL);
119
+    goto LAB9;
120
+
121
+LAB11:    xsi_set_current_line(52, ng0);
122
+    t2 = xsi_get_transient_memory(128U);
123
+    memset(t2, 0, 128U);
124
+    t5 = t2;
125
+    t7 = (t0 + 7679);
126
+    t18 = (8U != 0);
127
+    if (t18 == 1)
128
+        goto LAB14;
129
+
130
+LAB15:    t14 = (t0 + 4552);
131
+    t15 = (t14 + 56U);
132
+    t16 = *((char **)t15);
133
+    t17 = (t16 + 56U);
134
+    t19 = *((char **)t17);
135
+    memcpy(t19, t2, 128U);
136
+    xsi_driver_first_trans_fast(t14);
137
+    goto LAB12;
138
+
139
+LAB14:    t10 = (128U / 8U);
140
+    xsi_mem_set_data(t5, t7, 8U, t10);
141
+    goto LAB15;
142
+
143
+}
144
+
145
+static void work_a_3998322972_3212880686_p_1(char *t0)
146
+{
147
+    unsigned char t1;
148
+    char *t2;
149
+    char *t3;
150
+    unsigned char t4;
151
+    unsigned char t5;
152
+    char *t6;
153
+    char *t7;
154
+    char *t8;
155
+    unsigned char t9;
156
+    char *t10;
157
+    char *t11;
158
+    char *t12;
159
+    int t13;
160
+    int t14;
161
+    unsigned int t15;
162
+    unsigned int t16;
163
+    unsigned int t17;
164
+    char *t18;
165
+    char *t19;
166
+    char *t20;
167
+    char *t21;
168
+    char *t22;
169
+    char *t23;
170
+    char *t24;
171
+    char *t25;
172
+    char *t26;
173
+    char *t27;
174
+    char *t28;
175
+    char *t29;
176
+    char *t30;
177
+
178
+LAB0:    xsi_set_current_line(55, ng0);
179
+    t2 = (t0 + 1512U);
180
+    t3 = *((char **)t2);
181
+    t4 = *((unsigned char *)t3);
182
+    t5 = (t4 == (unsigned char)2);
183
+    if (t5 == 1)
184
+        goto LAB5;
185
+
186
+LAB6:    t2 = (t0 + 1032U);
187
+    t6 = *((char **)t2);
188
+    t2 = (t0 + 7392U);
189
+    t7 = (t0 + 1352U);
190
+    t8 = *((char **)t7);
191
+    t7 = (t0 + 7424U);
192
+    t9 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t6, t2, t8, t7);
193
+    t1 = t9;
194
+
195
+LAB7:    if (t1 != 0)
196
+        goto LAB3;
197
+
198
+LAB4:
199
+LAB8:    t24 = (t0 + 1672U);
200
+    t25 = *((char **)t24);
201
+    t24 = (t0 + 4616);
202
+    t26 = (t24 + 56U);
203
+    t27 = *((char **)t26);
204
+    t28 = (t27 + 56U);
205
+    t29 = *((char **)t28);
206
+    memcpy(t29, t25, 8U);
207
+    xsi_driver_first_trans_fast_port(t24);
208
+
209
+LAB2:    t30 = (t0 + 4456);
210
+    *((int *)t30) = 1;
211
+
212
+LAB1:    return;
213
+LAB3:    t10 = (t0 + 2472U);
214
+    t11 = *((char **)t10);
215
+    t10 = (t0 + 1032U);
216
+    t12 = *((char **)t10);
217
+    t10 = (t0 + 7392U);
218
+    t13 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t12, t10);
219
+    t14 = (t13 - 0);
220
+    t15 = (t14 * 1);
221
+    xsi_vhdl_check_range_of_index(0, 15, 1, t13);
222
+    t16 = (8U * t15);
223
+    t17 = (0 + t16);
224
+    t18 = (t11 + t17);
225
+    t19 = (t0 + 4616);
226
+    t20 = (t19 + 56U);
227
+    t21 = *((char **)t20);
228
+    t22 = (t21 + 56U);
229
+    t23 = *((char **)t22);
230
+    memcpy(t23, t18, 8U);
231
+    xsi_driver_first_trans_fast_port(t19);
232
+    goto LAB2;
233
+
234
+LAB5:    t1 = (unsigned char)1;
235
+    goto LAB7;
236
+
237
+LAB9:    goto LAB2;
238
+
239
+}
240
+
241
+static void work_a_3998322972_3212880686_p_2(char *t0)
242
+{
243
+    unsigned char t1;
244
+    char *t2;
245
+    char *t3;
246
+    unsigned char t4;
247
+    unsigned char t5;
248
+    char *t6;
249
+    char *t7;
250
+    char *t8;
251
+    unsigned char t9;
252
+    char *t10;
253
+    char *t11;
254
+    char *t12;
255
+    int t13;
256
+    int t14;
257
+    unsigned int t15;
258
+    unsigned int t16;
259
+    unsigned int t17;
260
+    char *t18;
261
+    char *t19;
262
+    char *t20;
263
+    char *t21;
264
+    char *t22;
265
+    char *t23;
266
+    char *t24;
267
+    char *t25;
268
+    char *t26;
269
+    char *t27;
270
+    char *t28;
271
+    char *t29;
272
+    char *t30;
273
+
274
+LAB0:    xsi_set_current_line(57, ng0);
275
+    t2 = (t0 + 1512U);
276
+    t3 = *((char **)t2);
277
+    t4 = *((unsigned char *)t3);
278
+    t5 = (t4 == (unsigned char)2);
279
+    if (t5 == 1)
280
+        goto LAB5;
281
+
282
+LAB6:    t2 = (t0 + 1192U);
283
+    t6 = *((char **)t2);
284
+    t2 = (t0 + 7408U);
285
+    t7 = (t0 + 1352U);
286
+    t8 = *((char **)t7);
287
+    t7 = (t0 + 7424U);
288
+    t9 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t6, t2, t8, t7);
289
+    t1 = t9;
290
+
291
+LAB7:    if (t1 != 0)
292
+        goto LAB3;
293
+
294
+LAB4:
295
+LAB8:    t24 = (t0 + 1672U);
296
+    t25 = *((char **)t24);
297
+    t24 = (t0 + 4680);
298
+    t26 = (t24 + 56U);
299
+    t27 = *((char **)t26);
300
+    t28 = (t27 + 56U);
301
+    t29 = *((char **)t28);
302
+    memcpy(t29, t25, 8U);
303
+    xsi_driver_first_trans_fast_port(t24);
304
+
305
+LAB2:    t30 = (t0 + 4472);
306
+    *((int *)t30) = 1;
307
+
308
+LAB1:    return;
309
+LAB3:    t10 = (t0 + 2472U);
310
+    t11 = *((char **)t10);
311
+    t10 = (t0 + 1192U);
312
+    t12 = *((char **)t10);
313
+    t10 = (t0 + 7408U);
314
+    t13 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t12, t10);
315
+    t14 = (t13 - 0);
316
+    t15 = (t14 * 1);
317
+    xsi_vhdl_check_range_of_index(0, 15, 1, t13);
318
+    t16 = (8U * t15);
319
+    t17 = (0 + t16);
320
+    t18 = (t11 + t17);
321
+    t19 = (t0 + 4680);
322
+    t20 = (t19 + 56U);
323
+    t21 = *((char **)t20);
324
+    t22 = (t21 + 56U);
325
+    t23 = *((char **)t22);
326
+    memcpy(t23, t18, 8U);
327
+    xsi_driver_first_trans_fast_port(t19);
328
+    goto LAB2;
329
+
330
+LAB5:    t1 = (unsigned char)1;
331
+    goto LAB7;
332
+
333
+LAB9:    goto LAB2;
334
+
335
+}
336
+
337
+
338
+extern void work_a_3998322972_3212880686_init()
339
+{
340
+	static char *pe[] = {(void *)work_a_3998322972_3212880686_p_0,(void *)work_a_3998322972_3212880686_p_1,(void *)work_a_3998322972_3212880686_p_2};
341
+	xsi_register_didat("work_a_3998322972_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat");
342
+	xsi_register_executes(pe);
343
+}

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat View File


BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.lin64.o View File


+ 1195
- 0
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c
File diff suppressed because it is too large