diff --git a/interpreter/interpreter b/interpreter/interpreter index 5585c34..daaf2bd 100755 Binary files a/interpreter/interpreter and b/interpreter/interpreter differ diff --git a/xilinx/ALU/ALU.gise b/xilinx/ALU/ALU.gise index 52da936..7a6fa15 100644 --- a/xilinx/ALU/ALU.gise +++ b/xilinx/ALU/ALU.gise @@ -34,6 +34,9 @@ + + + @@ -46,7 +49,7 @@ - + @@ -58,13 +61,14 @@ + - + - + @@ -72,7 +76,7 @@ - + @@ -84,20 +88,25 @@ + - - + + + + + + + + - - + + - - - - - + + + diff --git a/xilinx/ALU/ALU.xise b/xilinx/ALU/ALU.xise index be9b7ff..ecd5fc7 100644 --- a/xilinx/ALU/ALU.xise +++ b/xilinx/ALU/ALU.xise @@ -63,6 +63,12 @@ + + + + + + @@ -305,8 +311,8 @@ - - + + @@ -324,7 +330,7 @@ - + @@ -374,7 +380,7 @@ - + diff --git a/xilinx/ALU/bm_instr.vhd b/xilinx/ALU/bm_instr.vhd index 7b708d9..a51c05d 100644 --- a/xilinx/ALU/bm_instr.vhd +++ b/xilinx/ALU/bm_instr.vhd @@ -32,8 +32,14 @@ end bm_instr; architecture Behavioral of bm_instr is type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0); -signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000"); +-- instruction "00000110 00000001 00000110 00000000" +--test afc +--signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000"); +--test afc cop +signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000"); +--test add +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000"); begin OUT_data <= instr_memory(to_integer(unsigned(IN_addr))); diff --git a/xilinx/ALU/fuse.log b/xilinx/ALU/fuse.log index b922d6b..8225c6d 100644 --- a/xilinx/ALU/fuse.log +++ b/xilinx/ALU/fuse.log @@ -1,4 +1,4 @@ -Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_beh.prj work.processeur +Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test" ISim O.87xd (signature 0x8ddf5b5d) Number of CPUs detected in this system: 12 Turning on mult-threading, number of parallel sub-compilation jobs: 24 @@ -9,23 +9,27 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work -ERROR:HDLCompiler:32 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: is already declared in this region. -ERROR:HDLCompiler:32 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: is already declared in this region. -ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic is not declared in -ERROR:HDLCompiler:432 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal has no actual or default value. -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: is not declared. -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: is not declared. -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: is not declared. -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: is not declared. -ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic is not declared in -ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic is not declared in
-ERROR:HDLCompiler:432 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal has no actual or default value. -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: is not declared. -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: is not declared. -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: is not declared. -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: is not declared. -ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic is not declared in -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: is not declared. -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: is not declared. -ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: is not declared. -Sorry, too many errors.. +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd" into library work +Starting static elaboration +Completed static elaboration +Fuse Memory Usage: 98520 KB +Fuse CPU Usage: 760 ms +Compiling package standard +Compiling package std_logic_1164 +Compiling package std_logic_arith +Compiling package std_logic_unsigned +Compiling package numeric_std +Compiling architecture behavioral of entity bm_instr [bm_instr_default] +Compiling architecture behavioral of entity pipeline [pipeline_default] +Compiling architecture behavioral of entity br [br_default] +Compiling architecture behavioral of entity alu [alu_default] +Compiling architecture behavioral of entity bm_data [bm_data_default] +Compiling architecture behavioral of entity processeur [processeur_default] +Compiling architecture behavior of entity process_test +Time Resolution for simulation is 1ps. +Waiting for 1 sub-compilation(s) to finish... +Compiled 18 VHDL Units +Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe +Fuse Memory Usage: 1723208 KB +Fuse CPU Usage: 850 ms +GCC CPU Usage: 120 ms diff --git a/xilinx/ALU/fuse.xmsgs b/xilinx/ALU/fuse.xmsgs index 0a1af27..f84336a 100644 --- a/xilinx/ALU/fuse.xmsgs +++ b/xilinx/ALU/fuse.xmsgs @@ -5,62 +5,5 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: <rst> is already declared in this region. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: <clk> is already declared in this region. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic <ip> is not declared in <bm_instr> - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal <in_addr> has no actual or default value. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: <op_in> is not declared. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: <a_in> is not declared. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: <b_in> is not declared. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: <c_in> is not declared. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic <clk> is not declared in <pipeline> - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic <b_lidi_out> is not declared in <br> - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal <a_addr> has no actual or default value. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: <op_in> is not declared. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: <a_in> is not declared. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: <b_in> is not declared. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: <c_in> is not declared. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic <clk> is not declared in <pipeline> - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: <a> is not declared. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: <b> is not declared. - - -"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: <ctrl_alu> is not declared. - - diff --git a/xilinx/ALU/fuseRelaunch.cmd b/xilinx/ALU/fuseRelaunch.cmd index a5affee..b6f2149 100644 --- a/xilinx/ALU/fuseRelaunch.cmd +++ b/xilinx/ALU/fuseRelaunch.cmd @@ -1 +1 @@ --intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_beh.prj" "work.processeur" +-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test" diff --git a/xilinx/ALU/iseconfig/processeur.xreport b/xilinx/ALU/iseconfig/processeur.xreport new file mode 100644 index 0000000..a144ac5 --- /dev/null +++ b/xilinx/ALU/iseconfig/processeur.xreport @@ -0,0 +1,215 @@ + + +
+ 2021-05-10T10:47:06 + processeur + Unknown + /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport + /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU + 2021-05-10T09:34:56 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/ALU/isim.log b/xilinx/ALU/isim.log index e88ea9c..ac9885d 100644 --- a/xilinx/ALU/isim.log +++ b/xilinx/ALU/isim.log @@ -1,5 +1,5 @@ ISim log file -Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.wdb +Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb ISim O.87xd (signature 0x8ddf5b5d) WARNING: A WEBPACK license was found. WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. @@ -10,7 +10,13 @@ Time resolution is 1 ps # wave add / # run 1000 ns Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 ISim O.87xd (signature 0x8ddf5b5d) WARNING: A WEBPACK license was found. WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. @@ -18,5 +24,25 @@ WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for This is a Lite version of ISim. # run 1000 ns Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 # exit 0 diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg deleted file mode 100644 index 93d33cf..0000000 Binary files a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg and /dev/null differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe b/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe deleted file mode 100755 index 6ac1094..0000000 Binary files a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe and /dev/null differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log b/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log deleted file mode 100644 index c230b1f..0000000 --- a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log +++ /dev/null @@ -1,29 +0,0 @@ -Command line: - bm_instr_test_isim_beh.exe - -simmode gui - -simrunnum 0 - -socket 58939 - -Tue May 4 13:10:22 2021 - - - Elaboration Time: 0.01 sec - - Current Memory Usage: 187.593 Meg - - Total Signals : 7 - Total Nets : 8233 - Total Signal Drivers : 3 - Total Blocks : 6 - Total Primitive Blocks : 5 - Total Processes : 3 - Total Traceable Variables : 16 - Total Scalar Nets and Variables : 8735 -Total Line Count : 11 - - Total Simulation Time: 0.03 sec - - Current Memory Usage: 263.094 Meg - -Tue May 4 13:11:03 2021 - diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat b/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat deleted file mode 100644 index d184e14..0000000 Binary files a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat and /dev/null differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat b/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat deleted file mode 100644 index 983edd5..0000000 Binary files a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat and /dev/null differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o b/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o deleted file mode 100644 index ad0cc8f..0000000 Binary files a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o and /dev/null differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.lin64.o b/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.lin64.o deleted file mode 100644 index 4683e61..0000000 Binary files a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.lin64.o and /dev/null differ diff --git a/xilinx/ALU/isim/isim_usage_statistics.html b/xilinx/ALU/isim/isim_usage_statistics.html index 8ad21b6..8db4a1e 100644 --- a/xilinx/ALU/isim/isim_usage_statistics.html +++ b/xilinx/ALU/isim/isim_usage_statistics.html @@ -2,14 +2,14 @@ ISim Statistics Xilinx HDL Libraries Used=ieee -Fuse Resource Usage=840 ms, 1722812 KB +Fuse Resource Usage=850 ms, 1723208 KB -Total Signals=7 -Total Nets=8233 -Total Blocks=6 -Total Processes=3 +Total Signals=109 +Total Nets=10695 +Total Blocks=14 +Total Processes=31 Total Simulation Time=1 us -Simulation Resource Usage=0.03 sec, 262041 KB +Simulation Resource Usage=0.04 sec, 264146 KB Simulation Mode=gui Hardware CoSim=0 diff --git a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat index 4d5f6e0..286651d 100644 Binary files a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat and b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat differ diff --git a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat index bfeb462..b00d7b6 100644 Binary files a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat and b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat differ diff --git a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat index dcab07b..56ad3f8 100644 Binary files a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat and b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat differ diff --git a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat index ae12081..8385230 100644 Binary files a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat and b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg new file mode 100644 index 0000000..c4844f4 Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimcrash.log b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimcrash.log similarity index 100% rename from xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimcrash.log rename to xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimcrash.log diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log new file mode 100644 index 0000000..43b3bf6 --- /dev/null +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log @@ -0,0 +1,29 @@ +Command line: + process_test_isim_beh.exe + -simmode gui + -simrunnum 0 + -socket 43981 + +Mon May 10 12:31:07 2021 + + + Elaboration Time: 0.01 sec + + Current Memory Usage: 189.698 Meg + + Total Signals : 109 + Total Nets : 10695 + Total Signal Drivers : 44 + Total Blocks : 14 + Total Primitive Blocks : 12 + Total Processes : 31 + Total Traceable Variables : 16 + Total Scalar Nets and Variables : 11197 +Total Line Count : 66 + + Total Simulation Time: 0.04 sec + + Current Memory Usage: 265.2 Meg + +Mon May 10 12:32:41 2021 + diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat new file mode 100644 index 0000000..b6daf1e Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe new file mode 100755 index 0000000..b761c0b Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/tmp_save/_1 b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1 similarity index 62% rename from xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/tmp_save/_1 rename to xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1 index 7ea97a0..d89b164 100644 Binary files a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/tmp_save/_1 and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1 differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.c new file mode 100644 index 0000000..2ee9351 --- /dev/null +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.c @@ -0,0 +1,964 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd"; +extern char *IEEE_P_2592010699; +extern char *IEEE_P_3620187407; + +unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *); +char *ieee_p_3620187407_sub_1496620905533613331_3965413181(char *, char *, char *, char *, char *, char *); +char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *); +char *ieee_p_3620187407_sub_1496620905533721142_3965413181(char *, char *, char *, char *, char *, char *); + + +static void work_a_0832606739_3212880686_p_0(char *t0) +{ + char t5[16]; + char t7[16]; + char *t1; + char *t3; + char *t4; + char *t6; + char *t8; + char *t9; + int t10; + unsigned int t11; + unsigned char t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t17; + char *t18; + +LAB0: xsi_set_current_line(54, ng0); + +LAB3: t1 = (t0 + 11471); + t3 = (t0 + 1032U); + t4 = *((char **)t3); + t6 = ((IEEE_P_2592010699) + 4000); + t8 = (t7 + 0U); + t9 = (t8 + 0U); + *((int *)t9) = 0; + t9 = (t8 + 4U); + *((int *)t9) = 0; + t9 = (t8 + 8U); + *((int *)t9) = 1; + t10 = (0 - 0); + t11 = (t10 * 1); + t11 = (t11 + 1); + t9 = (t8 + 12U); + *((unsigned int *)t9) = t11; + t9 = (t0 + 11224U); + t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101); + t11 = (1U + 8U); + t12 = (9U != t11); + if (t12 == 1) + goto LAB5; + +LAB6: t13 = (t0 + 7304); + t14 = (t13 + 56U); + t15 = *((char **)t14); + t16 = (t15 + 56U); + t17 = *((char **)t16); + memcpy(t17, t3, 9U); + xsi_driver_first_trans_fast(t13); + +LAB2: t18 = (t0 + 7064); + *((int *)t18) = 1; + +LAB1: return; +LAB4: goto LAB2; + +LAB5: xsi_size_not_matching(9U, t11, 0); + goto LAB6; + +} + +static void work_a_0832606739_3212880686_p_1(char *t0) +{ + char t5[16]; + char t7[16]; + char *t1; + char *t3; + char *t4; + char *t6; + char *t8; + char *t9; + int t10; + unsigned int t11; + unsigned char t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t17; + char *t18; + +LAB0: xsi_set_current_line(55, ng0); + +LAB3: t1 = (t0 + 11472); + t3 = (t0 + 1192U); + t4 = *((char **)t3); + t6 = ((IEEE_P_2592010699) + 4000); + t8 = (t7 + 0U); + t9 = (t8 + 0U); + *((int *)t9) = 0; + t9 = (t8 + 4U); + *((int *)t9) = 0; + t9 = (t8 + 8U); + *((int *)t9) = 1; + t10 = (0 - 0); + t11 = (t10 * 1); + t11 = (t11 + 1); + t9 = (t8 + 12U); + *((unsigned int *)t9) = t11; + t9 = (t0 + 11240U); + t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101); + t11 = (1U + 8U); + t12 = (9U != t11); + if (t12 == 1) + goto LAB5; + +LAB6: t13 = (t0 + 7368); + t14 = (t13 + 56U); + t15 = *((char **)t14); + t16 = (t15 + 56U); + t17 = *((char **)t16); + memcpy(t17, t3, 9U); + xsi_driver_first_trans_fast(t13); + +LAB2: t18 = (t0 + 7080); + *((int *)t18) = 1; + +LAB1: return; +LAB4: goto LAB2; + +LAB5: xsi_size_not_matching(9U, t11, 0); + goto LAB6; + +} + +static void work_a_0832606739_3212880686_p_2(char *t0) +{ + char t1[16]; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + +LAB0: xsi_set_current_line(56, ng0); + +LAB3: t2 = (t0 + 2312U); + t3 = *((char **)t2); + t2 = (t0 + 11288U); + t4 = (t0 + 2472U); + t5 = *((char **)t4); + t4 = (t0 + 11304U); + t6 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4); + t7 = (t1 + 12U); + t8 = *((unsigned int *)t7); + t9 = (1U * t8); + t10 = (9U != t9); + if (t10 == 1) + goto LAB5; + +LAB6: t11 = (t0 + 7432); + t12 = (t11 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t6, 9U); + xsi_driver_first_trans_fast(t11); + +LAB2: t16 = (t0 + 7096); + *((int *)t16) = 1; + +LAB1: return; +LAB4: goto LAB2; + +LAB5: xsi_size_not_matching(9U, t9, 0); + goto LAB6; + +} + +static void work_a_0832606739_3212880686_p_3(char *t0) +{ + char t1[16]; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + +LAB0: xsi_set_current_line(57, ng0); + +LAB3: t2 = (t0 + 2312U); + t3 = *((char **)t2); + t2 = (t0 + 11288U); + t4 = (t0 + 2472U); + t5 = *((char **)t4); + t4 = (t0 + 11304U); + t6 = ieee_p_3620187407_sub_1496620905533721142_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4); + t7 = (t1 + 12U); + t8 = *((unsigned int *)t7); + t9 = (1U * t8); + t10 = (9U != t9); + if (t10 == 1) + goto LAB5; + +LAB6: t11 = (t0 + 7496); + t12 = (t11 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t6, 9U); + xsi_driver_first_trans_fast(t11); + +LAB2: t16 = (t0 + 7112); + *((int *)t16) = 1; + +LAB1: return; +LAB4: goto LAB2; + +LAB5: xsi_size_not_matching(9U, t9, 0); + goto LAB6; + +} + +static void work_a_0832606739_3212880686_p_4(char *t0) +{ + char t1[16]; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + +LAB0: xsi_set_current_line(58, ng0); + +LAB3: t2 = (t0 + 1032U); + t3 = *((char **)t2); + t2 = (t0 + 11224U); + t4 = (t0 + 1192U); + t5 = *((char **)t4); + t4 = (t0 + 11240U); + t6 = ieee_p_3620187407_sub_1496620905533613331_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4); + t7 = (t1 + 12U); + t8 = *((unsigned int *)t7); + t9 = (1U * t8); + t10 = (16U != t9); + if (t10 == 1) + goto LAB5; + +LAB6: t11 = (t0 + 7560); + t12 = (t11 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t6, 16U); + xsi_driver_first_trans_fast(t11); + +LAB2: t16 = (t0 + 7128); + *((int *)t16) = 1; + +LAB1: return; +LAB4: goto LAB2; + +LAB5: xsi_size_not_matching(16U, t9, 0); + goto LAB6; + +} + +static void work_a_0832606739_3212880686_p_5(char *t0) +{ + char t5[16]; + char t23[16]; + char t41[16]; + char *t1; + char *t2; + char *t3; + char *t6; + char *t7; + int t8; + unsigned int t9; + unsigned char t10; + char *t11; + unsigned int t12; + unsigned int t13; + char *t14; + char *t15; + char *t16; + char *t17; + char *t18; + char *t19; + char *t20; + char *t21; + char *t24; + char *t25; + int t26; + unsigned int t27; + unsigned char t28; + char *t29; + unsigned int t30; + unsigned int t31; + char *t32; + char *t33; + char *t34; + char *t35; + char *t36; + char *t37; + char *t38; + char *t39; + char *t42; + char *t43; + int t44; + unsigned int t45; + unsigned char t46; + char *t47; + unsigned int t48; + unsigned int t49; + char *t50; + char *t51; + char *t52; + char *t53; + char *t54; + char *t55; + char *t56; + char *t57; + char *t58; + char *t59; + char *t60; + char *t61; + char *t62; + +LAB0: xsi_set_current_line(60, ng0); + t1 = (t0 + 1352U); + t2 = *((char **)t1); + t1 = (t0 + 11256U); + t3 = (t0 + 11473); + t6 = (t5 + 0U); + t7 = (t6 + 0U); + *((int *)t7) = 0; + t7 = (t6 + 4U); + *((int *)t7) = 2; + t7 = (t6 + 8U); + *((int *)t7) = 1; + t8 = (2 - 0); + t9 = (t8 * 1); + t9 = (t9 + 1); + t7 = (t6 + 12U); + *((unsigned int *)t7) = t9; + t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); + if (t10 != 0) + goto LAB3; + +LAB4: t19 = (t0 + 1352U); + t20 = *((char **)t19); + t19 = (t0 + 11256U); + t21 = (t0 + 11476); + t24 = (t23 + 0U); + t25 = (t24 + 0U); + *((int *)t25) = 0; + t25 = (t24 + 4U); + *((int *)t25) = 2; + t25 = (t24 + 8U); + *((int *)t25) = 1; + t26 = (2 - 0); + t27 = (t26 * 1); + t27 = (t27 + 1); + t25 = (t24 + 12U); + *((unsigned int *)t25) = t27; + t28 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t20, t19, t21, t23); + if (t28 != 0) + goto LAB5; + +LAB6: t37 = (t0 + 1352U); + t38 = *((char **)t37); + t37 = (t0 + 11256U); + t39 = (t0 + 11479); + t42 = (t41 + 0U); + t43 = (t42 + 0U); + *((int *)t43) = 0; + t43 = (t42 + 4U); + *((int *)t43) = 2; + t43 = (t42 + 8U); + *((int *)t43) = 1; + t44 = (2 - 0); + t45 = (t44 * 1); + t45 = (t45 + 1); + t43 = (t42 + 12U); + *((unsigned int *)t43) = t45; + t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t38, t37, t39, t41); + if (t46 != 0) + goto LAB7; + +LAB8: +LAB9: t55 = xsi_get_transient_memory(8U); + memset(t55, 0, 8U); + t56 = t55; + memset(t56, (unsigned char)2, 8U); + t57 = (t0 + 7624); + t58 = (t57 + 56U); + t59 = *((char **)t58); + t60 = (t59 + 56U); + t61 = *((char **)t60); + memcpy(t61, t55, 8U); + xsi_driver_first_trans_fast(t57); + +LAB2: t62 = (t0 + 7144); + *((int *)t62) = 1; + +LAB1: return; +LAB3: t7 = (t0 + 2632U); + t11 = *((char **)t7); + t9 = (8 - 7); + t12 = (t9 * 1U); + t13 = (0 + t12); + t7 = (t11 + t13); + t14 = (t0 + 7624); + t15 = (t14 + 56U); + t16 = *((char **)t15); + t17 = (t16 + 56U); + t18 = *((char **)t17); + memcpy(t18, t7, 8U); + xsi_driver_first_trans_fast(t14); + goto LAB2; + +LAB5: t25 = (t0 + 2792U); + t29 = *((char **)t25); + t27 = (8 - 7); + t30 = (t27 * 1U); + t31 = (0 + t30); + t25 = (t29 + t31); + t32 = (t0 + 7624); + t33 = (t32 + 56U); + t34 = *((char **)t33); + t35 = (t34 + 56U); + t36 = *((char **)t35); + memcpy(t36, t25, 8U); + xsi_driver_first_trans_fast(t32); + goto LAB2; + +LAB7: t43 = (t0 + 2952U); + t47 = *((char **)t43); + t45 = (15 - 7); + t48 = (t45 * 1U); + t49 = (0 + t48); + t43 = (t47 + t49); + t50 = (t0 + 7624); + t51 = (t50 + 56U); + t52 = *((char **)t51); + t53 = (t52 + 56U); + t54 = *((char **)t53); + memcpy(t54, t43, 8U); + xsi_driver_first_trans_fast(t50); + goto LAB2; + +LAB10: goto LAB2; + +} + +static void work_a_0832606739_3212880686_p_6(char *t0) +{ + char t7[16]; + char t13[16]; + char t21[16]; + unsigned char t1; + char *t2; + char *t3; + unsigned int t4; + unsigned int t5; + unsigned int t6; + char *t8; + char *t9; + int t10; + unsigned int t11; + char *t14; + char *t15; + int t16; + unsigned char t17; + char *t18; + char *t19; + char *t22; + char *t23; + int t24; + unsigned char t25; + char *t26; + char *t27; + char *t28; + char *t29; + char *t30; + char *t31; + char *t32; + char *t33; + char *t34; + char *t35; + +LAB0: xsi_set_current_line(64, ng0); + t2 = (t0 + 2952U); + t3 = *((char **)t2); + t4 = (15 - 15); + t5 = (t4 * 1U); + t6 = (0 + t5); + t2 = (t3 + t6); + t8 = (t7 + 0U); + t9 = (t8 + 0U); + *((int *)t9) = 15; + t9 = (t8 + 4U); + *((int *)t9) = 8; + t9 = (t8 + 8U); + *((int *)t9) = -1; + t10 = (8 - 15); + t11 = (t10 * -1); + t11 = (t11 + 1); + t9 = (t8 + 12U); + *((unsigned int *)t9) = t11; + t9 = (t0 + 11482); + t14 = (t13 + 0U); + t15 = (t14 + 0U); + *((int *)t15) = 0; + t15 = (t14 + 4U); + *((int *)t15) = 7; + t15 = (t14 + 8U); + *((int *)t15) = 1; + t16 = (7 - 0); + t11 = (t16 * 1); + t11 = (t11 + 1); + t15 = (t14 + 12U); + *((unsigned int *)t15) = t11; + t17 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t2, t7, t9, t13); + if (t17 == 1) + goto LAB5; + +LAB6: t1 = (unsigned char)0; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB8: t30 = (t0 + 7688); + t31 = (t30 + 56U); + t32 = *((char **)t31); + t33 = (t32 + 56U); + t34 = *((char **)t33); + *((unsigned char *)t34) = (unsigned char)2; + xsi_driver_first_trans_fast_port(t30); + +LAB2: t35 = (t0 + 7160); + *((int *)t35) = 1; + +LAB1: return; +LAB3: t23 = (t0 + 7688); + t26 = (t23 + 56U); + t27 = *((char **)t26); + t28 = (t27 + 56U); + t29 = *((char **)t28); + *((unsigned char *)t29) = (unsigned char)3; + xsi_driver_first_trans_fast_port(t23); + goto LAB2; + +LAB5: t15 = (t0 + 1352U); + t18 = *((char **)t15); + t15 = (t0 + 11256U); + t19 = (t0 + 11490); + t22 = (t21 + 0U); + t23 = (t22 + 0U); + *((int *)t23) = 0; + t23 = (t22 + 4U); + *((int *)t23) = 2; + t23 = (t22 + 8U); + *((int *)t23) = 1; + t24 = (2 - 0); + t11 = (t24 * 1); + t11 = (t11 + 1); + t23 = (t22 + 12U); + *((unsigned int *)t23) = t11; + t25 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t18, t15, t19, t21); + t1 = t25; + goto LAB7; + +LAB9: goto LAB2; + +} + +static void work_a_0832606739_3212880686_p_7(char *t0) +{ + char t14[16]; + unsigned char t1; + char *t2; + char *t3; + int t4; + unsigned int t5; + unsigned int t6; + unsigned int t7; + unsigned char t8; + unsigned char t9; + char *t10; + char *t11; + char *t12; + char *t15; + char *t16; + int t17; + unsigned int t18; + unsigned char t19; + char *t20; + char *t21; + char *t22; + char *t23; + char *t24; + char *t25; + char *t26; + char *t27; + char *t28; + char *t29; + +LAB0: xsi_set_current_line(66, ng0); + t2 = (t0 + 2632U); + t3 = *((char **)t2); + t4 = (8 - 8); + t5 = (t4 * -1); + t6 = (1U * t5); + t7 = (0 + t6); + t2 = (t3 + t7); + t8 = *((unsigned char *)t2); + t9 = (t8 == (unsigned char)3); + if (t9 == 1) + goto LAB5; + +LAB6: t1 = (unsigned char)0; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB8: t24 = (t0 + 7752); + t25 = (t24 + 56U); + t26 = *((char **)t25); + t27 = (t26 + 56U); + t28 = *((char **)t27); + *((unsigned char *)t28) = (unsigned char)2; + xsi_driver_first_trans_fast_port(t24); + +LAB2: t29 = (t0 + 7176); + *((int *)t29) = 1; + +LAB1: return; +LAB3: t16 = (t0 + 7752); + t20 = (t16 + 56U); + t21 = *((char **)t20); + t22 = (t21 + 56U); + t23 = *((char **)t22); + *((unsigned char *)t23) = (unsigned char)3; + xsi_driver_first_trans_fast_port(t16); + goto LAB2; + +LAB5: t10 = (t0 + 1352U); + t11 = *((char **)t10); + t10 = (t0 + 11256U); + t12 = (t0 + 11493); + t15 = (t14 + 0U); + t16 = (t15 + 0U); + *((int *)t16) = 0; + t16 = (t15 + 4U); + *((int *)t16) = 2; + t16 = (t15 + 8U); + *((int *)t16) = 1; + t17 = (2 - 0); + t18 = (t17 * 1); + t18 = (t18 + 1); + t16 = (t15 + 12U); + *((unsigned int *)t16) = t18; + t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14); + t1 = t19; + goto LAB7; + +LAB9: goto LAB2; + +} + +static void work_a_0832606739_3212880686_p_8(char *t0) +{ + char t14[16]; + unsigned char t1; + char *t2; + char *t3; + int t4; + unsigned int t5; + unsigned int t6; + unsigned int t7; + unsigned char t8; + unsigned char t9; + char *t10; + char *t11; + char *t12; + char *t15; + char *t16; + int t17; + unsigned int t18; + unsigned char t19; + char *t20; + char *t21; + char *t22; + char *t23; + char *t24; + char *t25; + char *t26; + char *t27; + char *t28; + char *t29; + +LAB0: xsi_set_current_line(68, ng0); + t2 = (t0 + 2792U); + t3 = *((char **)t2); + t4 = (8 - 8); + t5 = (t4 * -1); + t6 = (1U * t5); + t7 = (0 + t6); + t2 = (t3 + t7); + t8 = *((unsigned char *)t2); + t9 = (t8 == (unsigned char)3); + if (t9 == 1) + goto LAB5; + +LAB6: t1 = (unsigned char)0; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB8: t24 = (t0 + 7816); + t25 = (t24 + 56U); + t26 = *((char **)t25); + t27 = (t26 + 56U); + t28 = *((char **)t27); + *((unsigned char *)t28) = (unsigned char)2; + xsi_driver_first_trans_fast_port(t24); + +LAB2: t29 = (t0 + 7192); + *((int *)t29) = 1; + +LAB1: return; +LAB3: t16 = (t0 + 7816); + t20 = (t16 + 56U); + t21 = *((char **)t20); + t22 = (t21 + 56U); + t23 = *((char **)t22); + *((unsigned char *)t23) = (unsigned char)3; + xsi_driver_first_trans_fast_port(t16); + goto LAB2; + +LAB5: t10 = (t0 + 1352U); + t11 = *((char **)t10); + t10 = (t0 + 11256U); + t12 = (t0 + 11496); + t15 = (t14 + 0U); + t16 = (t15 + 0U); + *((int *)t16) = 0; + t16 = (t15 + 4U); + *((int *)t16) = 2; + t16 = (t15 + 8U); + *((int *)t16) = 1; + t17 = (2 - 0); + t18 = (t17 * 1); + t18 = (t18 + 1); + t16 = (t15 + 12U); + *((unsigned int *)t16) = t18; + t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14); + t1 = t19; + goto LAB7; + +LAB9: goto LAB2; + +} + +static void work_a_0832606739_3212880686_p_9(char *t0) +{ + char t6[16]; + char t15[16]; + unsigned char t1; + char *t2; + char *t3; + char *t4; + char *t7; + char *t8; + int t9; + unsigned int t10; + unsigned char t11; + char *t12; + char *t13; + char *t16; + char *t17; + int t18; + unsigned char t19; + char *t20; + char *t21; + char *t22; + char *t23; + char *t24; + char *t25; + char *t26; + char *t27; + char *t28; + char *t29; + +LAB0: xsi_set_current_line(70, ng0); + t2 = (t0 + 3112U); + t3 = *((char **)t2); + t2 = (t0 + 11368U); + t4 = (t0 + 11499); + t7 = (t6 + 0U); + t8 = (t7 + 0U); + *((int *)t8) = 0; + t8 = (t7 + 4U); + *((int *)t8) = 7; + t8 = (t7 + 8U); + *((int *)t8) = 1; + t9 = (7 - 0); + t10 = (t9 * 1); + t10 = (t10 + 1); + t8 = (t7 + 12U); + *((unsigned int *)t8) = t10; + t11 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t3, t2, t4, t6); + if (t11 == 1) + goto LAB5; + +LAB6: t1 = (unsigned char)0; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB8: t24 = (t0 + 7880); + t25 = (t24 + 56U); + t26 = *((char **)t25); + t27 = (t26 + 56U); + t28 = *((char **)t27); + *((unsigned char *)t28) = (unsigned char)2; + xsi_driver_first_trans_fast_port(t24); + +LAB2: t29 = (t0 + 7208); + *((int *)t29) = 1; + +LAB1: return; +LAB3: t17 = (t0 + 7880); + t20 = (t17 + 56U); + t21 = *((char **)t20); + t22 = (t21 + 56U); + t23 = *((char **)t22); + *((unsigned char *)t23) = (unsigned char)3; + xsi_driver_first_trans_fast_port(t17); + goto LAB2; + +LAB5: t8 = (t0 + 1352U); + t12 = *((char **)t8); + t8 = (t0 + 11256U); + t13 = (t0 + 11507); + t16 = (t15 + 0U); + t17 = (t16 + 0U); + *((int *)t17) = 0; + t17 = (t16 + 4U); + *((int *)t17) = 2; + t17 = (t16 + 8U); + *((int *)t17) = 1; + t18 = (2 - 0); + t10 = (t18 * 1); + t10 = (t10 + 1); + t17 = (t16 + 12U); + *((unsigned int *)t17) = t10; + t19 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t12, t8, t13, t15); + t1 = t19; + goto LAB7; + +LAB9: goto LAB2; + +} + +static void work_a_0832606739_3212880686_p_10(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + +LAB0: xsi_set_current_line(72, ng0); + +LAB3: t1 = (t0 + 3112U); + t2 = *((char **)t1); + t1 = (t0 + 7944); + t3 = (t1 + 56U); + t4 = *((char **)t3); + t5 = (t4 + 56U); + t6 = *((char **)t5); + memcpy(t6, t2, 8U); + xsi_driver_first_trans_fast_port(t1); + +LAB2: t7 = (t0 + 7224); + *((int *)t7) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + + +extern void work_a_0832606739_3212880686_init() +{ + static char *pe[] = {(void *)work_a_0832606739_3212880686_p_0,(void *)work_a_0832606739_3212880686_p_1,(void *)work_a_0832606739_3212880686_p_2,(void *)work_a_0832606739_3212880686_p_3,(void *)work_a_0832606739_3212880686_p_4,(void *)work_a_0832606739_3212880686_p_5,(void *)work_a_0832606739_3212880686_p_6,(void *)work_a_0832606739_3212880686_p_7,(void *)work_a_0832606739_3212880686_p_8,(void *)work_a_0832606739_3212880686_p_9,(void *)work_a_0832606739_3212880686_p_10}; + xsi_register_didat("work_a_0832606739_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat"); + xsi_register_executes(pe); +} diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat new file mode 100644 index 0000000..9380503 Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.lin64.o new file mode 100644 index 0000000..5fb049e Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.lin64.o differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.c similarity index 62% rename from xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c rename to xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.c index e288f16..3d7b177 100644 --- a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.c @@ -21,11 +21,11 @@ #include #define alloca _alloca #endif -static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd"; +static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd"; -static void work_a_4060154216_2372691052_p_0(char *t0) +static void work_a_1229531095_2372691052_p_0(char *t0) { char *t1; char *t2; @@ -36,46 +36,46 @@ static void work_a_4060154216_2372691052_p_0(char *t0) int64 t7; int64 t8; -LAB0: t1 = (t0 + 2624U); +LAB0: t1 = (t0 + 2464U); t2 = *((char **)t1); if (t2 == 0) goto LAB2; LAB3: goto *t2; -LAB2: xsi_set_current_line(73, ng0); - t2 = (t0 + 3256); +LAB2: xsi_set_current_line(68, ng0); + t2 = (t0 + 3096); t3 = (t2 + 56U); t4 = *((char **)t3); t5 = (t4 + 56U); t6 = *((char **)t5); *((unsigned char *)t6) = (unsigned char)2; xsi_driver_first_trans_fast(t2); - xsi_set_current_line(74, ng0); - t2 = (t0 + 1648U); + xsi_set_current_line(69, ng0); + t2 = (t0 + 1488U); t3 = *((char **)t2); t7 = *((int64 *)t3); t8 = (t7 / 2); - t2 = (t0 + 2432); + t2 = (t0 + 2272); xsi_process_wait(t2, t8); LAB6: *((char **)t1) = &&LAB7; LAB1: return; -LAB4: xsi_set_current_line(75, ng0); - t2 = (t0 + 3256); +LAB4: xsi_set_current_line(70, ng0); + t2 = (t0 + 3096); t3 = (t2 + 56U); t4 = *((char **)t3); t5 = (t4 + 56U); t6 = *((char **)t5); *((unsigned char *)t6) = (unsigned char)3; xsi_driver_first_trans_fast(t2); - xsi_set_current_line(76, ng0); - t2 = (t0 + 1648U); + xsi_set_current_line(71, ng0); + t2 = (t0 + 1488U); t3 = *((char **)t2); t7 = *((int64 *)t3); t8 = (t7 / 2); - t2 = (t0 + 2432); + t2 = (t0 + 2272); xsi_process_wait(t2, t8); LAB10: *((char **)t1) = &&LAB11; @@ -93,7 +93,7 @@ LAB11: goto LAB9; } -static void work_a_4060154216_2372691052_p_1(char *t0) +static void work_a_1229531095_2372691052_p_1(char *t0) { char *t1; char *t2; @@ -103,30 +103,28 @@ static void work_a_4060154216_2372691052_p_1(char *t0) char *t6; char *t7; char *t8; - char *t9; - char *t10; -LAB0: t1 = (t0 + 2872U); +LAB0: t1 = (t0 + 2712U); t2 = *((char **)t1); if (t2 == 0) goto LAB2; LAB3: goto *t2; -LAB2: xsi_set_current_line(84, ng0); +LAB2: xsi_set_current_line(79, ng0); t3 = (100 * 1000LL); - t2 = (t0 + 2680); + t2 = (t0 + 2520); xsi_process_wait(t2, t3); LAB6: *((char **)t1) = &&LAB7; LAB1: return; -LAB4: xsi_set_current_line(86, ng0); - t2 = (t0 + 1648U); +LAB4: xsi_set_current_line(81, ng0); + t2 = (t0 + 1488U); t4 = *((char **)t2); t3 = *((int64 *)t4); t5 = (t3 * 10); - t2 = (t0 + 2680); + t2 = (t0 + 2520); xsi_process_wait(t2, t5); LAB10: *((char **)t1) = &&LAB11; @@ -136,19 +134,15 @@ LAB5: goto LAB4; LAB7: goto LAB5; -LAB8: xsi_set_current_line(88, ng0); - t2 = (t0 + 5568); - t6 = (t0 + 3320); +LAB8: xsi_set_current_line(86, ng0); + t2 = (t0 + 3160); + t4 = (t2 + 56U); + t6 = *((char **)t4); t7 = (t6 + 56U); t8 = *((char **)t7); - t9 = (t8 + 56U); - t10 = *((char **)t9); - memcpy(t10, t2, 8U); - xsi_driver_first_trans_fast(t6); - xsi_set_current_line(89, ng0); - t3 = (100 * 1000LL); - t2 = (t0 + 2680); - xsi_process_wait(t2, t3); + *((unsigned char *)t8) = (unsigned char)3; + xsi_driver_first_trans_fast(t2); + xsi_set_current_line(90, ng0); LAB14: *((char **)t1) = &&LAB15; goto LAB1; @@ -157,36 +151,18 @@ LAB9: goto LAB8; LAB11: goto LAB9; -LAB12: xsi_set_current_line(91, ng0); - t2 = (t0 + 5576); - t6 = (t0 + 3320); - t7 = (t6 + 56U); - t8 = *((char **)t7); - t9 = (t8 + 56U); - t10 = *((char **)t9); - memcpy(t10, t2, 8U); - xsi_driver_first_trans_fast(t6); - xsi_set_current_line(94, ng0); - -LAB18: *((char **)t1) = &&LAB19; - goto LAB1; +LAB12: goto LAB2; LAB13: goto LAB12; LAB15: goto LAB13; -LAB16: goto LAB2; - -LAB17: goto LAB16; - -LAB19: goto LAB17; - } -extern void work_a_4060154216_2372691052_init() +extern void work_a_1229531095_2372691052_init() { - static char *pe[] = {(void *)work_a_4060154216_2372691052_p_0,(void *)work_a_4060154216_2372691052_p_1}; - xsi_register_didat("work_a_4060154216_2372691052", "isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat"); + static char *pe[] = {(void *)work_a_1229531095_2372691052_p_0,(void *)work_a_1229531095_2372691052_p_1}; + xsi_register_didat("work_a_1229531095_2372691052", "isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat"); xsi_register_executes(pe); } diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat new file mode 100644 index 0000000..dab3502 Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.lin64.o new file mode 100644 index 0000000..7658f0b Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.lin64.o differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.c new file mode 100644 index 0000000..ea60d8c --- /dev/null +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.c @@ -0,0 +1,181 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd"; +extern char *IEEE_P_2592010699; +extern char *IEEE_P_1242562249; + +int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *); +unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int ); + + +static void work_a_1466808984_3212880686_p_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + unsigned char t4; + char *t5; + unsigned char t6; + char *t7; + int t8; + int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t17; + char *t18; + unsigned char t19; + +LAB0: t1 = (t0 + 3144U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(42, ng0); + +LAB6: t2 = (t0 + 3464); + *((int *)t2) = 1; + *((char **)t1) = &&LAB7; + +LAB1: return; +LAB4: t5 = (t0 + 3464); + *((int *)t5) = 0; + xsi_set_current_line(43, ng0); + t2 = (t0 + 1352U); + t3 = *((char **)t2); + t4 = *((unsigned char *)t3); + t6 = (t4 == (unsigned char)3); + if (t6 != 0) + goto LAB8; + +LAB10: xsi_set_current_line(46, ng0); + t2 = (t0 + 1192U); + t3 = *((char **)t2); + t2 = (t0 + 1032U); + t5 = *((char **)t2); + t2 = (t0 + 5968U); + t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t5, t2); + t9 = (t8 - 0); + t10 = (t9 * 1); + t11 = (8U * t10); + t12 = (0U + t11); + t7 = (t0 + 3608); + t13 = (t7 + 56U); + t14 = *((char **)t13); + t15 = (t14 + 56U); + t16 = *((char **)t15); + memcpy(t16, t3, 8U); + xsi_driver_first_trans_delta(t7, t12, 8U, 0LL); + +LAB9: xsi_set_current_line(48, ng0); + t2 = (t0 + 1512U); + t3 = *((char **)t2); + t4 = *((unsigned char *)t3); + t6 = (t4 == (unsigned char)2); + if (t6 != 0) + goto LAB11; + +LAB13: +LAB12: goto LAB2; + +LAB5: t3 = (t0 + 1632U); + t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U); + if (t4 == 1) + goto LAB4; + else + goto LAB6; + +LAB7: goto LAB5; + +LAB8: xsi_set_current_line(44, ng0); + t2 = (t0 + 1992U); + t5 = *((char **)t2); + t2 = (t0 + 1032U); + t7 = *((char **)t2); + t2 = (t0 + 5968U); + t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2); + t9 = (t8 - 0); + t10 = (t9 * 1); + xsi_vhdl_check_range_of_index(0, 255, 1, t8); + t11 = (8U * t10); + t12 = (0 + t11); + t13 = (t5 + t12); + t14 = (t0 + 3544); + t15 = (t14 + 56U); + t16 = *((char **)t15); + t17 = (t16 + 56U); + t18 = *((char **)t17); + memcpy(t18, t13, 8U); + xsi_driver_first_trans_fast_port(t14); + goto LAB9; + +LAB11: xsi_set_current_line(49, ng0); + t2 = xsi_get_transient_memory(2048U); + memset(t2, 0, 2048U); + t5 = t2; + t7 = (t0 + 8123); + t19 = (8U != 0); + if (t19 == 1) + goto LAB14; + +LAB15: t14 = (t0 + 3608); + t15 = (t14 + 56U); + t16 = *((char **)t15); + t17 = (t16 + 56U); + t18 = *((char **)t17); + memcpy(t18, t2, 2048U); + xsi_driver_first_trans_fast(t14); + xsi_set_current_line(50, ng0); + t2 = xsi_get_transient_memory(8U); + memset(t2, 0, 8U); + t3 = t2; + memset(t3, (unsigned char)2, 8U); + t5 = (t0 + 3544); + t7 = (t5 + 56U); + t13 = *((char **)t7); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t2, 8U); + xsi_driver_first_trans_fast_port(t5); + goto LAB12; + +LAB14: t10 = (2048U / 8U); + xsi_mem_set_data(t5, t7, 8U, t10); + goto LAB15; + +} + + +extern void work_a_1466808984_3212880686_init() +{ + static char *pe[] = {(void *)work_a_1466808984_3212880686_p_0}; + xsi_register_didat("work_a_1466808984_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat"); + xsi_register_executes(pe); +} diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat new file mode 100644 index 0000000..d0b248f Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.lin64.o new file mode 100644 index 0000000..b907dc0 Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.lin64.o differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c similarity index 93% rename from xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c rename to xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c index c6934a9..a5b42f6 100644 --- a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c @@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0) char *t14; char *t15; -LAB0: xsi_set_current_line(39, ng0); +LAB0: xsi_set_current_line(45, ng0); LAB3: t1 = (t0 + 1512U); t2 = *((char **)t1); @@ -79,6 +79,6 @@ LAB4: goto LAB2; extern void work_a_1802466774_3212880686_init() { static char *pe[] = {(void *)work_a_1802466774_3212880686_p_0}; - xsi_register_didat("work_a_1802466774_3212880686", "isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat"); + xsi_register_didat("work_a_1802466774_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat"); xsi_register_executes(pe); } diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat similarity index 83% rename from xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat rename to xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat index da7f22d..8b36ff9 100644 Binary files a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o similarity index 86% rename from xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o rename to xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o index 5d38769..921e541 100644 Binary files a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c new file mode 100644 index 0000000..4990355 --- /dev/null +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c @@ -0,0 +1,116 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd"; +extern char *IEEE_P_2592010699; + +unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int ); + + +static void work_a_3650175700_3212880686_p_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + unsigned char t4; + char *t5; + char *t6; + char *t7; + char *t8; + +LAB0: t1 = (t0 + 3464U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(49, ng0); + +LAB6: t2 = (t0 + 3784); + *((int *)t2) = 1; + *((char **)t1) = &&LAB7; + +LAB1: return; +LAB4: t5 = (t0 + 3784); + *((int *)t5) = 0; + xsi_set_current_line(50, ng0); + t2 = (t0 + 1032U); + t3 = *((char **)t2); + t2 = (t0 + 3864); + t5 = (t2 + 56U); + t6 = *((char **)t5); + t7 = (t6 + 56U); + t8 = *((char **)t7); + memcpy(t8, t3, 8U); + xsi_driver_first_trans_fast_port(t2); + xsi_set_current_line(51, ng0); + t2 = (t0 + 1192U); + t3 = *((char **)t2); + t2 = (t0 + 3928); + t5 = (t2 + 56U); + t6 = *((char **)t5); + t7 = (t6 + 56U); + t8 = *((char **)t7); + memcpy(t8, t3, 8U); + xsi_driver_first_trans_fast_port(t2); + xsi_set_current_line(52, ng0); + t2 = (t0 + 1352U); + t3 = *((char **)t2); + t2 = (t0 + 3992); + t5 = (t2 + 56U); + t6 = *((char **)t5); + t7 = (t6 + 56U); + t8 = *((char **)t7); + memcpy(t8, t3, 8U); + xsi_driver_first_trans_fast_port(t2); + xsi_set_current_line(53, ng0); + t2 = (t0 + 1512U); + t3 = *((char **)t2); + t2 = (t0 + 4056); + t5 = (t2 + 56U); + t6 = *((char **)t5); + t7 = (t6 + 56U); + t8 = *((char **)t7); + memcpy(t8, t3, 8U); + xsi_driver_first_trans_fast_port(t2); + goto LAB2; + +LAB5: t3 = (t0 + 1632U); + t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U); + if (t4 == 1) + goto LAB4; + else + goto LAB6; + +LAB7: goto LAB5; + +} + + +extern void work_a_3650175700_3212880686_init() +{ + static char *pe[] = {(void *)work_a_3650175700_3212880686_p_0}; + xsi_register_didat("work_a_3650175700_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat"); + xsi_register_executes(pe); +} diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat new file mode 100644 index 0000000..767be67 Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.lin64.o new file mode 100644 index 0000000..5d6c345 Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.lin64.o differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.c new file mode 100644 index 0000000..87f384a --- /dev/null +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.c @@ -0,0 +1,343 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd"; +extern char *IEEE_P_2592010699; +extern char *IEEE_P_1242562249; +extern char *IEEE_P_3620187407; + +int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *); +unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int ); +unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *); + + +static void work_a_3998322972_3212880686_p_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + unsigned char t4; + char *t5; + unsigned char t6; + char *t7; + int t8; + int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t17; + unsigned char t18; + char *t19; + +LAB0: t1 = (t0 + 3624U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(47, ng0); + +LAB6: t2 = (t0 + 4440); + *((int *)t2) = 1; + *((char **)t1) = &&LAB7; + +LAB1: return; +LAB4: t5 = (t0 + 4440); + *((int *)t5) = 0; + xsi_set_current_line(48, ng0); + t2 = (t0 + 1512U); + t3 = *((char **)t2); + t4 = *((unsigned char *)t3); + t6 = (t4 == (unsigned char)3); + if (t6 != 0) + goto LAB8; + +LAB10: +LAB9: xsi_set_current_line(51, ng0); + t2 = (t0 + 1832U); + t3 = *((char **)t2); + t4 = *((unsigned char *)t3); + t6 = (t4 == (unsigned char)2); + if (t6 != 0) + goto LAB11; + +LAB13: +LAB12: goto LAB2; + +LAB5: t3 = (t0 + 1952U); + t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U); + if (t4 == 1) + goto LAB4; + else + goto LAB6; + +LAB7: goto LAB5; + +LAB8: xsi_set_current_line(49, ng0); + t2 = (t0 + 1672U); + t5 = *((char **)t2); + t2 = (t0 + 1352U); + t7 = *((char **)t2); + t2 = (t0 + 7424U); + t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2); + t9 = (t8 - 0); + t10 = (t9 * 1); + t11 = (8U * t10); + t12 = (0U + t11); + t13 = (t0 + 4552); + t14 = (t13 + 56U); + t15 = *((char **)t14); + t16 = (t15 + 56U); + t17 = *((char **)t16); + memcpy(t17, t5, 8U); + xsi_driver_first_trans_delta(t13, t12, 8U, 0LL); + goto LAB9; + +LAB11: xsi_set_current_line(52, ng0); + t2 = xsi_get_transient_memory(128U); + memset(t2, 0, 128U); + t5 = t2; + t7 = (t0 + 7679); + t18 = (8U != 0); + if (t18 == 1) + goto LAB14; + +LAB15: t14 = (t0 + 4552); + t15 = (t14 + 56U); + t16 = *((char **)t15); + t17 = (t16 + 56U); + t19 = *((char **)t17); + memcpy(t19, t2, 128U); + xsi_driver_first_trans_fast(t14); + goto LAB12; + +LAB14: t10 = (128U / 8U); + xsi_mem_set_data(t5, t7, 8U, t10); + goto LAB15; + +} + +static void work_a_3998322972_3212880686_p_1(char *t0) +{ + unsigned char t1; + char *t2; + char *t3; + unsigned char t4; + unsigned char t5; + char *t6; + char *t7; + char *t8; + unsigned char t9; + char *t10; + char *t11; + char *t12; + int t13; + int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + char *t18; + char *t19; + char *t20; + char *t21; + char *t22; + char *t23; + char *t24; + char *t25; + char *t26; + char *t27; + char *t28; + char *t29; + char *t30; + +LAB0: xsi_set_current_line(55, ng0); + t2 = (t0 + 1512U); + t3 = *((char **)t2); + t4 = *((unsigned char *)t3); + t5 = (t4 == (unsigned char)2); + if (t5 == 1) + goto LAB5; + +LAB6: t2 = (t0 + 1032U); + t6 = *((char **)t2); + t2 = (t0 + 7392U); + t7 = (t0 + 1352U); + t8 = *((char **)t7); + t7 = (t0 + 7424U); + t9 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t6, t2, t8, t7); + t1 = t9; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB8: t24 = (t0 + 1672U); + t25 = *((char **)t24); + t24 = (t0 + 4616); + t26 = (t24 + 56U); + t27 = *((char **)t26); + t28 = (t27 + 56U); + t29 = *((char **)t28); + memcpy(t29, t25, 8U); + xsi_driver_first_trans_fast_port(t24); + +LAB2: t30 = (t0 + 4456); + *((int *)t30) = 1; + +LAB1: return; +LAB3: t10 = (t0 + 2472U); + t11 = *((char **)t10); + t10 = (t0 + 1032U); + t12 = *((char **)t10); + t10 = (t0 + 7392U); + t13 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t12, t10); + t14 = (t13 - 0); + t15 = (t14 * 1); + xsi_vhdl_check_range_of_index(0, 15, 1, t13); + t16 = (8U * t15); + t17 = (0 + t16); + t18 = (t11 + t17); + t19 = (t0 + 4616); + t20 = (t19 + 56U); + t21 = *((char **)t20); + t22 = (t21 + 56U); + t23 = *((char **)t22); + memcpy(t23, t18, 8U); + xsi_driver_first_trans_fast_port(t19); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB9: goto LAB2; + +} + +static void work_a_3998322972_3212880686_p_2(char *t0) +{ + unsigned char t1; + char *t2; + char *t3; + unsigned char t4; + unsigned char t5; + char *t6; + char *t7; + char *t8; + unsigned char t9; + char *t10; + char *t11; + char *t12; + int t13; + int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + char *t18; + char *t19; + char *t20; + char *t21; + char *t22; + char *t23; + char *t24; + char *t25; + char *t26; + char *t27; + char *t28; + char *t29; + char *t30; + +LAB0: xsi_set_current_line(57, ng0); + t2 = (t0 + 1512U); + t3 = *((char **)t2); + t4 = *((unsigned char *)t3); + t5 = (t4 == (unsigned char)2); + if (t5 == 1) + goto LAB5; + +LAB6: t2 = (t0 + 1192U); + t6 = *((char **)t2); + t2 = (t0 + 7408U); + t7 = (t0 + 1352U); + t8 = *((char **)t7); + t7 = (t0 + 7424U); + t9 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t6, t2, t8, t7); + t1 = t9; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB8: t24 = (t0 + 1672U); + t25 = *((char **)t24); + t24 = (t0 + 4680); + t26 = (t24 + 56U); + t27 = *((char **)t26); + t28 = (t27 + 56U); + t29 = *((char **)t28); + memcpy(t29, t25, 8U); + xsi_driver_first_trans_fast_port(t24); + +LAB2: t30 = (t0 + 4472); + *((int *)t30) = 1; + +LAB1: return; +LAB3: t10 = (t0 + 2472U); + t11 = *((char **)t10); + t10 = (t0 + 1192U); + t12 = *((char **)t10); + t10 = (t0 + 7408U); + t13 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t12, t10); + t14 = (t13 - 0); + t15 = (t14 * 1); + xsi_vhdl_check_range_of_index(0, 15, 1, t13); + t16 = (8U * t15); + t17 = (0 + t16); + t18 = (t11 + t17); + t19 = (t0 + 4680); + t20 = (t19 + 56U); + t21 = *((char **)t20); + t22 = (t21 + 56U); + t23 = *((char **)t22); + memcpy(t23, t18, 8U); + xsi_driver_first_trans_fast_port(t19); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB9: goto LAB2; + +} + + +extern void work_a_3998322972_3212880686_init() +{ + static char *pe[] = {(void *)work_a_3998322972_3212880686_p_0,(void *)work_a_3998322972_3212880686_p_1,(void *)work_a_3998322972_3212880686_p_2}; + xsi_register_didat("work_a_3998322972_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat"); + xsi_register_executes(pe); +} diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat new file mode 100644 index 0000000..01c7692 Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.lin64.o new file mode 100644 index 0000000..ee53acb Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.lin64.o differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c new file mode 100644 index 0000000..d7ee46a --- /dev/null +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c @@ -0,0 +1,1195 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd"; +extern char *IEEE_P_3620187407; +extern char *IEEE_P_2592010699; + +unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int ); +char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *); + + +static void work_a_4150868852_3212880686_p_0(char *t0) +{ + char t11[16]; + char t20[16]; + char t28[16]; + char t36[16]; + char t44[16]; + char t52[16]; + char t60[16]; + unsigned char t1; + unsigned char t2; + unsigned char t3; + unsigned char t4; + unsigned char t5; + unsigned char t6; + char *t7; + char *t8; + char *t9; + char *t12; + char *t13; + int t14; + unsigned int t15; + unsigned char t16; + char *t17; + char *t18; + char *t21; + char *t22; + int t23; + unsigned char t24; + char *t25; + char *t26; + char *t29; + char *t30; + int t31; + unsigned char t32; + char *t33; + char *t34; + char *t37; + char *t38; + int t39; + unsigned char t40; + char *t41; + char *t42; + char *t45; + char *t46; + int t47; + unsigned char t48; + char *t49; + char *t50; + char *t53; + char *t54; + int t55; + unsigned char t56; + char *t57; + char *t58; + char *t61; + char *t62; + int t63; + unsigned char t64; + char *t65; + char *t66; + char *t67; + char *t68; + char *t69; + char *t70; + char *t71; + char *t72; + char *t73; + char *t74; + +LAB0: xsi_set_current_line(166, ng0); + t7 = (t0 + 4872U); + t8 = *((char **)t7); + t7 = (t0 + 17848U); + t9 = (t0 + 18267); + t12 = (t11 + 0U); + t13 = (t12 + 0U); + *((int *)t13) = 0; + t13 = (t12 + 4U); + *((int *)t13) = 7; + t13 = (t12 + 8U); + *((int *)t13) = 1; + t14 = (7 - 0); + t15 = (t14 * 1); + t15 = (t15 + 1); + t13 = (t12 + 12U); + *((unsigned int *)t13) = t15; + t16 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t8, t7, t9, t11); + if (t16 == 1) + goto LAB20; + +LAB21: t13 = (t0 + 4872U); + t17 = *((char **)t13); + t13 = (t0 + 17848U); + t18 = (t0 + 18275); + t21 = (t20 + 0U); + t22 = (t21 + 0U); + *((int *)t22) = 0; + t22 = (t21 + 4U); + *((int *)t22) = 7; + t22 = (t21 + 8U); + *((int *)t22) = 1; + t23 = (7 - 0); + t15 = (t23 * 1); + t15 = (t15 + 1); + t22 = (t21 + 12U); + *((unsigned int *)t22) = t15; + t24 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t17, t13, t18, t20); + t6 = t24; + +LAB22: if (t6 == 1) + goto LAB17; + +LAB18: t22 = (t0 + 4872U); + t25 = *((char **)t22); + t22 = (t0 + 17848U); + t26 = (t0 + 18283); + t29 = (t28 + 0U); + t30 = (t29 + 0U); + *((int *)t30) = 0; + t30 = (t29 + 4U); + *((int *)t30) = 7; + t30 = (t29 + 8U); + *((int *)t30) = 1; + t31 = (7 - 0); + t15 = (t31 * 1); + t15 = (t15 + 1); + t30 = (t29 + 12U); + *((unsigned int *)t30) = t15; + t32 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t25, t22, t26, t28); + t5 = t32; + +LAB19: if (t5 == 1) + goto LAB14; + +LAB15: t30 = (t0 + 4872U); + t33 = *((char **)t30); + t30 = (t0 + 17848U); + t34 = (t0 + 18291); + t37 = (t36 + 0U); + t38 = (t37 + 0U); + *((int *)t38) = 0; + t38 = (t37 + 4U); + *((int *)t38) = 7; + t38 = (t37 + 8U); + *((int *)t38) = 1; + t39 = (7 - 0); + t15 = (t39 * 1); + t15 = (t15 + 1); + t38 = (t37 + 12U); + *((unsigned int *)t38) = t15; + t40 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t33, t30, t34, t36); + t4 = t40; + +LAB16: if (t4 == 1) + goto LAB11; + +LAB12: t38 = (t0 + 4872U); + t41 = *((char **)t38); + t38 = (t0 + 17848U); + t42 = (t0 + 18299); + t45 = (t44 + 0U); + t46 = (t45 + 0U); + *((int *)t46) = 0; + t46 = (t45 + 4U); + *((int *)t46) = 7; + t46 = (t45 + 8U); + *((int *)t46) = 1; + t47 = (7 - 0); + t15 = (t47 * 1); + t15 = (t15 + 1); + t46 = (t45 + 12U); + *((unsigned int *)t46) = t15; + t48 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t41, t38, t42, t44); + t3 = t48; + +LAB13: if (t3 == 1) + goto LAB8; + +LAB9: t46 = (t0 + 4872U); + t49 = *((char **)t46); + t46 = (t0 + 17848U); + t50 = (t0 + 18307); + t53 = (t52 + 0U); + t54 = (t53 + 0U); + *((int *)t54) = 0; + t54 = (t53 + 4U); + *((int *)t54) = 7; + t54 = (t53 + 8U); + *((int *)t54) = 1; + t55 = (7 - 0); + t15 = (t55 * 1); + t15 = (t15 + 1); + t54 = (t53 + 12U); + *((unsigned int *)t54) = t15; + t56 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t49, t46, t50, t52); + t2 = t56; + +LAB10: if (t2 == 1) + goto LAB5; + +LAB6: t54 = (t0 + 4872U); + t57 = *((char **)t54); + t54 = (t0 + 17848U); + t58 = (t0 + 18315); + t61 = (t60 + 0U); + t62 = (t61 + 0U); + *((int *)t62) = 0; + t62 = (t61 + 4U); + *((int *)t62) = 7; + t62 = (t61 + 8U); + *((int *)t62) = 1; + t63 = (7 - 0); + t15 = (t63 * 1); + t15 = (t15 + 1); + t62 = (t61 + 12U); + *((unsigned int *)t62) = t15; + t64 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t57, t54, t58, t60); + t1 = t64; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB23: t69 = (t0 + 10296); + t70 = (t69 + 56U); + t71 = *((char **)t70); + t72 = (t71 + 56U); + t73 = *((char **)t72); + *((unsigned char *)t73) = (unsigned char)2; + xsi_driver_first_trans_fast(t69); + +LAB2: t74 = (t0 + 10088); + *((int *)t74) = 1; + +LAB1: return; +LAB3: t62 = (t0 + 10296); + t65 = (t62 + 56U); + t66 = *((char **)t65); + t67 = (t66 + 56U); + t68 = *((char **)t67); + *((unsigned char *)t68) = (unsigned char)3; + xsi_driver_first_trans_fast(t62); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB8: t2 = (unsigned char)1; + goto LAB10; + +LAB11: t3 = (unsigned char)1; + goto LAB13; + +LAB14: t4 = (unsigned char)1; + goto LAB16; + +LAB17: t5 = (unsigned char)1; + goto LAB19; + +LAB20: t6 = (unsigned char)1; + goto LAB22; + +LAB24: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_1(char *t0) +{ + char t9[16]; + char t18[16]; + char t26[16]; + char t34[16]; + char t42[16]; + unsigned char t1; + unsigned char t2; + unsigned char t3; + unsigned char t4; + char *t5; + char *t6; + char *t7; + char *t10; + char *t11; + int t12; + unsigned int t13; + unsigned char t14; + char *t15; + char *t16; + char *t19; + char *t20; + int t21; + unsigned char t22; + char *t23; + char *t24; + char *t27; + char *t28; + int t29; + unsigned char t30; + char *t31; + char *t32; + char *t35; + char *t36; + int t37; + unsigned char t38; + char *t39; + char *t40; + char *t43; + char *t44; + int t45; + unsigned char t46; + char *t47; + char *t48; + char *t49; + char *t50; + char *t51; + char *t52; + char *t53; + char *t54; + char *t55; + char *t56; + char *t57; + char *t58; + +LAB0: xsi_set_current_line(181, ng0); + t5 = (t0 + 2152U); + t6 = *((char **)t5); + t5 = (t0 + 17640U); + t7 = (t0 + 18323); + t10 = (t9 + 0U); + t11 = (t10 + 0U); + *((int *)t11) = 0; + t11 = (t10 + 4U); + *((int *)t11) = 7; + t11 = (t10 + 8U); + *((int *)t11) = 1; + t12 = (7 - 0); + t13 = (t12 * 1); + t13 = (t13 + 1); + t11 = (t10 + 12U); + *((unsigned int *)t11) = t13; + t14 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t6, t5, t7, t9); + if (t14 == 1) + goto LAB14; + +LAB15: t11 = (t0 + 2152U); + t15 = *((char **)t11); + t11 = (t0 + 17640U); + t16 = (t0 + 18331); + t19 = (t18 + 0U); + t20 = (t19 + 0U); + *((int *)t20) = 0; + t20 = (t19 + 4U); + *((int *)t20) = 7; + t20 = (t19 + 8U); + *((int *)t20) = 1; + t21 = (7 - 0); + t13 = (t21 * 1); + t13 = (t13 + 1); + t20 = (t19 + 12U); + *((unsigned int *)t20) = t13; + t22 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t15, t11, t16, t18); + t4 = t22; + +LAB16: if (t4 == 1) + goto LAB11; + +LAB12: t20 = (t0 + 2152U); + t23 = *((char **)t20); + t20 = (t0 + 17640U); + t24 = (t0 + 18339); + t27 = (t26 + 0U); + t28 = (t27 + 0U); + *((int *)t28) = 0; + t28 = (t27 + 4U); + *((int *)t28) = 7; + t28 = (t27 + 8U); + *((int *)t28) = 1; + t29 = (7 - 0); + t13 = (t29 * 1); + t13 = (t13 + 1); + t28 = (t27 + 12U); + *((unsigned int *)t28) = t13; + t30 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t23, t20, t24, t26); + t3 = t30; + +LAB13: if (t3 == 1) + goto LAB8; + +LAB9: t28 = (t0 + 2152U); + t31 = *((char **)t28); + t28 = (t0 + 17640U); + t32 = (t0 + 18347); + t35 = (t34 + 0U); + t36 = (t35 + 0U); + *((int *)t36) = 0; + t36 = (t35 + 4U); + *((int *)t36) = 7; + t36 = (t35 + 8U); + *((int *)t36) = 1; + t37 = (7 - 0); + t13 = (t37 * 1); + t13 = (t13 + 1); + t36 = (t35 + 12U); + *((unsigned int *)t36) = t13; + t38 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t31, t28, t32, t34); + t2 = t38; + +LAB10: if (t2 == 1) + goto LAB5; + +LAB6: t36 = (t0 + 2152U); + t39 = *((char **)t36); + t36 = (t0 + 17640U); + t40 = (t0 + 18355); + t43 = (t42 + 0U); + t44 = (t43 + 0U); + *((int *)t44) = 0; + t44 = (t43 + 4U); + *((int *)t44) = 7; + t44 = (t43 + 8U); + *((int *)t44) = 1; + t45 = (7 - 0); + t13 = (t45 * 1); + t13 = (t13 + 1); + t44 = (t43 + 12U); + *((unsigned int *)t44) = t13; + t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t39, t36, t40, t42); + t1 = t46; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB17: t52 = (t0 + 2472U); + t53 = *((char **)t52); + t52 = (t0 + 10360); + t54 = (t52 + 56U); + t55 = *((char **)t54); + t56 = (t55 + 56U); + t57 = *((char **)t56); + memcpy(t57, t53, 8U); + xsi_driver_first_trans_fast(t52); + +LAB2: t58 = (t0 + 10104); + *((int *)t58) = 1; + +LAB1: return; +LAB3: t44 = (t0 + 1512U); + t47 = *((char **)t44); + t44 = (t0 + 10360); + t48 = (t44 + 56U); + t49 = *((char **)t48); + t50 = (t49 + 56U); + t51 = *((char **)t50); + memcpy(t51, t47, 8U); + xsi_driver_first_trans_fast(t44); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB8: t2 = (unsigned char)1; + goto LAB10; + +LAB11: t3 = (unsigned char)1; + goto LAB13; + +LAB14: t4 = (unsigned char)1; + goto LAB16; + +LAB18: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_2(char *t0) +{ + char t5[16]; + char t21[16]; + char t36[16]; + char *t1; + char *t2; + char *t3; + char *t6; + char *t7; + int t8; + unsigned int t9; + unsigned char t10; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t17; + char *t18; + char *t19; + char *t22; + char *t23; + int t24; + unsigned char t25; + char *t27; + char *t28; + char *t29; + char *t30; + char *t31; + char *t32; + char *t33; + char *t34; + char *t37; + char *t38; + int t39; + unsigned char t40; + char *t42; + char *t43; + char *t44; + char *t45; + char *t46; + char *t47; + char *t49; + char *t50; + char *t51; + char *t52; + char *t53; + char *t54; + +LAB0: xsi_set_current_line(197, ng0); + t1 = (t0 + 2792U); + t2 = *((char **)t1); + t1 = (t0 + 17704U); + t3 = (t0 + 18363); + t6 = (t5 + 0U); + t7 = (t6 + 0U); + *((int *)t7) = 0; + t7 = (t6 + 4U); + *((int *)t7) = 7; + t7 = (t6 + 8U); + *((int *)t7) = 1; + t8 = (7 - 0); + t9 = (t8 * 1); + t9 = (t9 + 1); + t7 = (t6 + 12U); + *((unsigned int *)t7) = t9; + t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); + if (t10 != 0) + goto LAB3; + +LAB4: t17 = (t0 + 2792U); + t18 = *((char **)t17); + t17 = (t0 + 17704U); + t19 = (t0 + 18374); + t22 = (t21 + 0U); + t23 = (t22 + 0U); + *((int *)t23) = 0; + t23 = (t22 + 4U); + *((int *)t23) = 7; + t23 = (t22 + 8U); + *((int *)t23) = 1; + t24 = (7 - 0); + t9 = (t24 * 1); + t9 = (t9 + 1); + t23 = (t22 + 12U); + *((unsigned int *)t23) = t9; + t25 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t18, t17, t19, t21); + if (t25 != 0) + goto LAB5; + +LAB6: t32 = (t0 + 2792U); + t33 = *((char **)t32); + t32 = (t0 + 17704U); + t34 = (t0 + 18385); + t37 = (t36 + 0U); + t38 = (t37 + 0U); + *((int *)t38) = 0; + t38 = (t37 + 4U); + *((int *)t38) = 7; + t38 = (t37 + 8U); + *((int *)t38) = 1; + t39 = (7 - 0); + t9 = (t39 * 1); + t9 = (t9 + 1); + t38 = (t37 + 12U); + *((unsigned int *)t38) = t9; + t40 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t33, t32, t34, t36); + if (t40 != 0) + goto LAB7; + +LAB8: +LAB9: t47 = (t0 + 18396); + t49 = (t0 + 10424); + t50 = (t49 + 56U); + t51 = *((char **)t50); + t52 = (t51 + 56U); + t53 = *((char **)t52); + memcpy(t53, t47, 3U); + xsi_driver_first_trans_fast(t49); + +LAB2: t54 = (t0 + 10120); + *((int *)t54) = 1; + +LAB1: return; +LAB3: t7 = (t0 + 18371); + t12 = (t0 + 10424); + t13 = (t12 + 56U); + t14 = *((char **)t13); + t15 = (t14 + 56U); + t16 = *((char **)t15); + memcpy(t16, t7, 3U); + xsi_driver_first_trans_fast(t12); + goto LAB2; + +LAB5: t23 = (t0 + 18382); + t27 = (t0 + 10424); + t28 = (t27 + 56U); + t29 = *((char **)t28); + t30 = (t29 + 56U); + t31 = *((char **)t30); + memcpy(t31, t23, 3U); + xsi_driver_first_trans_fast(t27); + goto LAB2; + +LAB7: t38 = (t0 + 18393); + t42 = (t0 + 10424); + t43 = (t42 + 56U); + t44 = *((char **)t43); + t45 = (t44 + 56U); + t46 = *((char **)t45); + memcpy(t46, t38, 3U); + xsi_driver_first_trans_fast(t42); + goto LAB2; + +LAB10: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_3(char *t0) +{ + char t7[16]; + char t16[16]; + char t24[16]; + unsigned char t1; + unsigned char t2; + char *t3; + char *t4; + char *t5; + char *t8; + char *t9; + int t10; + unsigned int t11; + unsigned char t12; + char *t13; + char *t14; + char *t17; + char *t18; + int t19; + unsigned char t20; + char *t21; + char *t22; + char *t25; + char *t26; + int t27; + unsigned char t28; + char *t29; + char *t30; + char *t31; + char *t32; + char *t33; + char *t34; + char *t35; + char *t36; + char *t37; + char *t38; + char *t39; + char *t40; + +LAB0: xsi_set_current_line(214, ng0); + t3 = (t0 + 2792U); + t4 = *((char **)t3); + t3 = (t0 + 17704U); + t5 = (t0 + 18399); + t8 = (t7 + 0U); + t9 = (t8 + 0U); + *((int *)t9) = 0; + t9 = (t8 + 4U); + *((int *)t9) = 7; + t9 = (t8 + 8U); + *((int *)t9) = 1; + t10 = (7 - 0); + t11 = (t10 * 1); + t11 = (t11 + 1); + t9 = (t8 + 12U); + *((unsigned int *)t9) = t11; + t12 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t4, t3, t5, t7); + if (t12 == 1) + goto LAB8; + +LAB9: t9 = (t0 + 2792U); + t13 = *((char **)t9); + t9 = (t0 + 17704U); + t14 = (t0 + 18407); + t17 = (t16 + 0U); + t18 = (t17 + 0U); + *((int *)t18) = 0; + t18 = (t17 + 4U); + *((int *)t18) = 7; + t18 = (t17 + 8U); + *((int *)t18) = 1; + t19 = (7 - 0); + t11 = (t19 * 1); + t11 = (t11 + 1); + t18 = (t17 + 12U); + *((unsigned int *)t18) = t11; + t20 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t13, t9, t14, t16); + t2 = t20; + +LAB10: if (t2 == 1) + goto LAB5; + +LAB6: t18 = (t0 + 2792U); + t21 = *((char **)t18); + t18 = (t0 + 17704U); + t22 = (t0 + 18415); + t25 = (t24 + 0U); + t26 = (t25 + 0U); + *((int *)t26) = 0; + t26 = (t25 + 4U); + *((int *)t26) = 7; + t26 = (t25 + 8U); + *((int *)t26) = 1; + t27 = (7 - 0); + t11 = (t27 * 1); + t11 = (t11 + 1); + t26 = (t25 + 12U); + *((unsigned int *)t26) = t11; + t28 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t21, t18, t22, t24); + t1 = t28; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB11: t34 = (t0 + 3112U); + t35 = *((char **)t34); + t34 = (t0 + 10488); + t36 = (t34 + 56U); + t37 = *((char **)t36); + t38 = (t37 + 56U); + t39 = *((char **)t38); + memcpy(t39, t35, 8U); + xsi_driver_first_trans_fast(t34); + +LAB2: t40 = (t0 + 10136); + *((int *)t40) = 1; + +LAB1: return; +LAB3: t26 = (t0 + 6152U); + t29 = *((char **)t26); + t26 = (t0 + 10488); + t30 = (t26 + 56U); + t31 = *((char **)t30); + t32 = (t31 + 56U); + t33 = *((char **)t32); + memcpy(t33, t29, 8U); + xsi_driver_first_trans_fast(t26); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB8: t2 = (unsigned char)1; + goto LAB10; + +LAB12: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_4(char *t0) +{ + char t5[16]; + char *t1; + char *t2; + char *t3; + char *t6; + char *t7; + int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t17; + char *t18; + char *t19; + char *t20; + +LAB0: xsi_set_current_line(231, ng0); + t1 = (t0 + 4392U); + t2 = *((char **)t1); + t1 = (t0 + 17800U); + t3 = (t0 + 18423); + t6 = (t5 + 0U); + t7 = (t6 + 0U); + *((int *)t7) = 0; + t7 = (t6 + 4U); + *((int *)t7) = 7; + t7 = (t6 + 8U); + *((int *)t7) = 1; + t8 = (7 - 0); + t9 = (t8 * 1); + t9 = (t9 + 1); + t7 = (t6 + 12U); + *((unsigned int *)t7) = t9; + t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); + if (t10 != 0) + goto LAB3; + +LAB4: +LAB5: t15 = (t0 + 10552); + t16 = (t15 + 56U); + t17 = *((char **)t16); + t18 = (t17 + 56U); + t19 = *((char **)t18); + *((unsigned char *)t19) = (unsigned char)3; + xsi_driver_first_trans_fast(t15); + +LAB2: t20 = (t0 + 10152); + *((int *)t20) = 1; + +LAB1: return; +LAB3: t7 = (t0 + 10552); + t11 = (t7 + 56U); + t12 = *((char **)t11); + t13 = (t12 + 56U); + t14 = *((char **)t13); + *((unsigned char *)t14) = (unsigned char)2; + xsi_driver_first_trans_fast(t7); + goto LAB2; + +LAB6: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_5(char *t0) +{ + char t5[16]; + char *t1; + char *t2; + char *t3; + char *t6; + char *t7; + int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t17; + char *t18; + char *t19; + char *t20; + char *t21; + char *t22; + +LAB0: xsi_set_current_line(233, ng0); + t1 = (t0 + 4392U); + t2 = *((char **)t1); + t1 = (t0 + 17800U); + t3 = (t0 + 18431); + t6 = (t5 + 0U); + t7 = (t6 + 0U); + *((int *)t7) = 0; + t7 = (t6 + 4U); + *((int *)t7) = 7; + t7 = (t6 + 8U); + *((int *)t7) = 1; + t8 = (7 - 0); + t9 = (t8 * 1); + t9 = (t9 + 1); + t7 = (t6 + 12U); + *((unsigned int *)t7) = t9; + t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); + if (t10 != 0) + goto LAB3; + +LAB4: +LAB5: t16 = (t0 + 4072U); + t17 = *((char **)t16); + t16 = (t0 + 10616); + t18 = (t16 + 56U); + t19 = *((char **)t18); + t20 = (t19 + 56U); + t21 = *((char **)t20); + memcpy(t21, t17, 8U); + xsi_driver_first_trans_fast(t16); + +LAB2: t22 = (t0 + 10168); + *((int *)t22) = 1; + +LAB1: return; +LAB3: t7 = (t0 + 4232U); + t11 = *((char **)t7); + t7 = (t0 + 10616); + t12 = (t7 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t11, 8U); + xsi_driver_first_trans_fast(t7); + goto LAB2; + +LAB6: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_6(char *t0) +{ + char t5[16]; + char *t1; + char *t2; + char *t3; + char *t6; + char *t7; + int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + +LAB0: xsi_set_current_line(235, ng0); + t1 = (t0 + 4392U); + t2 = *((char **)t1); + t1 = (t0 + 17800U); + t3 = (t0 + 18439); + t6 = (t5 + 0U); + t7 = (t6 + 0U); + *((int *)t7) = 0; + t7 = (t6 + 4U); + *((int *)t7) = 7; + t7 = (t6 + 8U); + *((int *)t7) = 1; + t8 = (7 - 0); + t9 = (t8 * 1); + t9 = (t9 + 1); + t7 = (t6 + 12U); + *((unsigned int *)t7) = t9; + t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); + if (t10 != 0) + goto LAB3; + +LAB4: +LAB2: t16 = (t0 + 10184); + *((int *)t16) = 1; + +LAB1: return; +LAB3: t7 = (t0 + 4232U); + t11 = *((char **)t7); + t7 = (t0 + 10680); + t12 = (t7 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t11, 8U); + xsi_driver_first_trans_fast(t7); + goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_7(char *t0) +{ + char t5[16]; + char *t1; + char *t2; + char *t3; + char *t6; + char *t7; + int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t17; + char *t18; + char *t19; + char *t20; + char *t21; + char *t22; + +LAB0: xsi_set_current_line(236, ng0); + t1 = (t0 + 4392U); + t2 = *((char **)t1); + t1 = (t0 + 17800U); + t3 = (t0 + 18447); + t6 = (t5 + 0U); + t7 = (t6 + 0U); + *((int *)t7) = 0; + t7 = (t6 + 4U); + *((int *)t7) = 7; + t7 = (t6 + 8U); + *((int *)t7) = 1; + t8 = (7 - 0); + t9 = (t8 * 1); + t9 = (t9 + 1); + t7 = (t6 + 12U); + *((unsigned int *)t7) = t9; + t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); + if (t10 != 0) + goto LAB3; + +LAB4: +LAB5: t16 = (t0 + 4232U); + t17 = *((char **)t16); + t16 = (t0 + 10744); + t18 = (t16 + 56U); + t19 = *((char **)t18); + t20 = (t19 + 56U); + t21 = *((char **)t20); + memcpy(t21, t17, 8U); + xsi_driver_first_trans_fast(t16); + +LAB2: t22 = (t0 + 10200); + *((int *)t22) = 1; + +LAB1: return; +LAB3: t7 = (t0 + 5672U); + t11 = *((char **)t7); + t7 = (t0 + 10744); + t12 = (t7 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t11, 8U); + xsi_driver_first_trans_fast(t7); + goto LAB2; + +LAB6: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_8(char *t0) +{ + char t12[16]; + char t13[16]; + char *t1; + char *t2; + char *t3; + unsigned char t4; + char *t5; + unsigned char t6; + char *t7; + char *t8; + char *t9; + char *t10; + char *t11; + int t14; + unsigned int t15; + unsigned int t16; + char *t17; + char *t18; + char *t19; + char *t20; + +LAB0: t1 = (t0 + 9768U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(262, ng0); + +LAB6: t2 = (t0 + 10216); + *((int *)t2) = 1; + *((char **)t1) = &&LAB7; + +LAB1: return; +LAB4: t5 = (t0 + 10216); + *((int *)t5) = 0; + xsi_set_current_line(263, ng0); + t2 = (t0 + 1192U); + t3 = *((char **)t2); + t4 = *((unsigned char *)t3); + t6 = (t4 == (unsigned char)2); + if (t6 != 0) + goto LAB8; + +LAB10: xsi_set_current_line(266, ng0); + t2 = (t0 + 1352U); + t3 = *((char **)t2); + t2 = (t0 + 17560U); + t5 = (t0 + 18463); + t8 = (t13 + 0U); + t9 = (t8 + 0U); + *((int *)t9) = 0; + t9 = (t8 + 4U); + *((int *)t9) = 7; + t9 = (t8 + 8U); + *((int *)t9) = 1; + t14 = (7 - 0); + t15 = (t14 * 1); + t15 = (t15 + 1); + t9 = (t8 + 12U); + *((unsigned int *)t9) = t15; + t9 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t12, t3, t2, t5, t13); + t10 = (t12 + 12U); + t15 = *((unsigned int *)t10); + t16 = (1U * t15); + t4 = (8U != t16); + if (t4 == 1) + goto LAB11; + +LAB12: t11 = (t0 + 10808); + t17 = (t11 + 56U); + t18 = *((char **)t17); + t19 = (t18 + 56U); + t20 = *((char **)t19); + memcpy(t20, t9, 8U); + xsi_driver_first_trans_fast(t11); + +LAB9: goto LAB2; + +LAB5: t3 = (t0 + 992U); + t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U); + if (t4 == 1) + goto LAB4; + else + goto LAB6; + +LAB7: goto LAB5; + +LAB8: xsi_set_current_line(264, ng0); + t2 = (t0 + 18455); + t7 = (t0 + 10808); + t8 = (t7 + 56U); + t9 = *((char **)t8); + t10 = (t9 + 56U); + t11 = *((char **)t10); + memcpy(t11, t2, 8U); + xsi_driver_first_trans_fast(t7); + goto LAB9; + +LAB11: xsi_size_not_matching(8U, t16, 0); + goto LAB12; + +} + + +extern void work_a_4150868852_3212880686_init() +{ + static char *pe[] = {(void *)work_a_4150868852_3212880686_p_0,(void *)work_a_4150868852_3212880686_p_1,(void *)work_a_4150868852_3212880686_p_2,(void *)work_a_4150868852_3212880686_p_3,(void *)work_a_4150868852_3212880686_p_4,(void *)work_a_4150868852_3212880686_p_5,(void *)work_a_4150868852_3212880686_p_6,(void *)work_a_4150868852_3212880686_p_7,(void *)work_a_4150868852_3212880686_p_8}; + xsi_register_didat("work_a_4150868852_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat"); + xsi_register_executes(pe); +} diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat new file mode 100644 index 0000000..e84fb20 Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o new file mode 100644 index 0000000..ef6a22d Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o differ diff --git a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/process_test_isim_beh.exe_main.c similarity index 84% rename from xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.c rename to xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/process_test_isim_beh.exe_main.c index 3bd117f..b2cbaad 100644 --- a/xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.c +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/process_test_isim_beh.exe_main.c @@ -32,10 +32,15 @@ int main(int argc, char **argv) ieee_p_3620187407_init(); ieee_p_1242562249_init(); work_a_1802466774_3212880686_init(); - work_a_4060154216_2372691052_init(); + work_a_3650175700_3212880686_init(); + work_a_3998322972_3212880686_init(); + work_a_0832606739_3212880686_init(); + work_a_1466808984_3212880686_init(); + work_a_4150868852_3212880686_init(); + work_a_1229531095_2372691052_init(); - xsi_register_tops("work_a_4060154216_2372691052"); + xsi_register_tops("work_a_1229531095_2372691052"); IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699"); xsi_register_ieee_std_logic_1164(IEEE_P_2592010699); diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/process_test_isim_beh.exe_main.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/process_test_isim_beh.exe_main.lin64.o new file mode 100644 index 0000000..0a163fb Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/process_test_isim_beh.exe_main.lin64.o differ diff --git a/xilinx/ALU/isim/work/alu.vdb b/xilinx/ALU/isim/work/alu.vdb new file mode 100644 index 0000000..3d69e0f Binary files /dev/null and b/xilinx/ALU/isim/work/alu.vdb differ diff --git a/xilinx/ALU/isim/work/bm_data.vdb b/xilinx/ALU/isim/work/bm_data.vdb new file mode 100644 index 0000000..c50550a Binary files /dev/null and b/xilinx/ALU/isim/work/bm_data.vdb differ diff --git a/xilinx/ALU/isim/work/bm_instr.vdb b/xilinx/ALU/isim/work/bm_instr.vdb new file mode 100644 index 0000000..a590406 Binary files /dev/null and b/xilinx/ALU/isim/work/bm_instr.vdb differ diff --git a/xilinx/ALU/isim/work/br.vdb b/xilinx/ALU/isim/work/br.vdb new file mode 100644 index 0000000..cb363ad Binary files /dev/null and b/xilinx/ALU/isim/work/br.vdb differ diff --git a/xilinx/ALU/isim/work/pipeline.vdb b/xilinx/ALU/isim/work/pipeline.vdb new file mode 100644 index 0000000..14165e2 Binary files /dev/null and b/xilinx/ALU/isim/work/pipeline.vdb differ diff --git a/xilinx/ALU/isim/work/process_test.vdb b/xilinx/ALU/isim/work/process_test.vdb new file mode 100644 index 0000000..7e7008d Binary files /dev/null and b/xilinx/ALU/isim/work/process_test.vdb differ diff --git a/xilinx/ALU/isim/work/processeur.vdb b/xilinx/ALU/isim/work/processeur.vdb new file mode 100644 index 0000000..37a8687 Binary files /dev/null and b/xilinx/ALU/isim/work/processeur.vdb differ diff --git a/xilinx/ALU/process_test.vhd b/xilinx/ALU/process_test.vhd new file mode 100644 index 0000000..81f6de9 --- /dev/null +++ b/xilinx/ALU/process_test.vhd @@ -0,0 +1,93 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:37:50 05/10/2021 +-- Design Name: +-- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd +-- Project Name: ALU +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: processeur +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY process_test IS +END process_test; + +ARCHITECTURE behavior OF process_test IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT processeur + PORT( + CLK : IN std_logic; + RST : IN std_logic + ); + END COMPONENT; + + + --Inputs + signal CLK : std_logic := '0'; + signal RST : std_logic := '0'; + + -- Clock period definitions + constant CLK_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: processeur PORT MAP ( + CLK => CLK, + RST => RST + ); + + -- Clock process definitions + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + wait for 100 ns; + + wait for CLK_period*10; + + -- insert stimulus here + + -- AFC test + RST<='1'; + + + + wait; + end process; + +END; diff --git a/xilinx/ALU/process_test_beh.prj b/xilinx/ALU/process_test_beh.prj new file mode 100644 index 0000000..9a6873c --- /dev/null +++ b/xilinx/ALU/process_test_beh.prj @@ -0,0 +1,7 @@ +vhdl work "pipeline.vhd" +vhdl work "br.vhd" +vhdl work "bm_instr.vhd" +vhdl work "bm.vhd" +vhdl work "alu.vhd" +vhdl work "processeur.vhd" +vhdl work "process_test.vhd" diff --git a/xilinx/ALU/process_test_isim_beh.exe b/xilinx/ALU/process_test_isim_beh.exe new file mode 100755 index 0000000..beb9ccd Binary files /dev/null and b/xilinx/ALU/process_test_isim_beh.exe differ diff --git a/xilinx/ALU/process_test_isim_beh.wdb b/xilinx/ALU/process_test_isim_beh.wdb new file mode 100644 index 0000000..6c339fb Binary files /dev/null and b/xilinx/ALU/process_test_isim_beh.wdb differ diff --git a/xilinx/ALU/processeur.vhd b/xilinx/ALU/processeur.vhd index 3434470..04b95cd 100644 --- a/xilinx/ALU/processeur.vhd +++ b/xilinx/ALU/processeur.vhd @@ -19,6 +19,9 @@ ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values @@ -38,7 +41,7 @@ architecture Behavioral of processeur is COMPONENT bm_instr PORT( IN_addr : IN std_logic_vector(7 downto 0); - OUT_data : OUT std_logic_vector(7 downto 0); + OUT_data : OUT std_logic_vector(31 downto 0); CLK : IN std_logic ); END COMPONENT; @@ -48,6 +51,7 @@ architecture Behavioral of processeur is A_IN : in STD_LOGIC_VECTOR (7 downto 0); B_IN : in STD_LOGIC_VECTOR (7 downto 0); C_IN : in STD_LOGIC_VECTOR (7 downto 0); + CLK : IN std_logic; OP_OUT : out STD_LOGIC_VECTOR (7 downto 0); A_OUT : out STD_LOGIC_VECTOR (7 downto 0); B_OUT : out STD_LOGIC_VECTOR (7 downto 0); @@ -92,13 +96,7 @@ architecture Behavioral of processeur is OUT_data : OUT std_logic_vector(7 downto 0) ); END COMPONENT; - - signal RST : std_logic := '0'; - signal CLK : std_logic := '0'; - - -- Clock period definitions - constant CLK_period : time := 10 ns; --Inputs signal IP : std_logic_vector(7 downto 0) := (others => '0'); signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0'); @@ -107,7 +105,7 @@ architecture Behavioral of processeur is signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); --Outputs - signal OUT_data : std_logic_vector(7 downto 0); + signal OUT_data : std_logic_vector(31 downto 0); signal OP_LIDI_OUT : std_logic_vector(7 downto 0); signal A_LIDI_OUT : std_logic_vector(7 downto 0); @@ -139,53 +137,56 @@ architecture Behavioral of processeur is signal addr_dm_MUX : std_logic_vector(7 downto 0); signal in_dm_MUX : std_logic_vector(7 downto 0); signal out_dm_MUX : std_logic_vector(7 downto 0); + signal B_EXMem_IN : std_logic_vector(7 downto 0); signal W_br_LC : std_logic; + signal S_IN_MUX : std_logic_vector(7 downto 0); + signal B_MemRE_IN : std_logic_vector(7 downto 0); begin -- Instantiate adresse des instructions addr_instructions: bm_instr PORT MAP ( - IP => IN_addr, + IN_addr => IP, OUT_data => OUT_data, CLK => CLK ); -- Instantiate pipeline LI_LD LI_LD : pipeline PORT MAP ( - OP_IN <= OUT_data(31 downto 24), - A_IN <= OUT_data(23 downto 16), - B_IN <= OUT_data(15 downto 8), - C_IN <= OUT_data(7 downto 0), + OP_IN => OUT_data(31 downto 24), + A_IN => OUT_data(23 downto 16), + B_IN => OUT_data(15 downto 8), + C_IN => OUT_data(7 downto 0), CLK => CLK, A_OUT => A_LIDI_OUT, B_OUT => B_LIDI_OUT, C_OUT => C_LIDI_OUT, OP_OUT => OP_LIDI_OUT ); - W_br_LC <= '1' when OP_MemRE_OUT = x"07" else + W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else '0'; -- Instanciate banc de registre banc_registres : br PORT MAP ( - B_LIDI_OUT => A_addr, - C_LIDI_OUT => B_addr, - A_MemRE_OUT => W_addr, - W_br_LC => W, --ATTENTION LC - B_MemRE_OUT => Data, + A_addr => B_LIDI_OUT(3 downto 0), + B_addr => C_LIDI_OUT(3 downto 0), + W_addr => A_MemRE_OUT(3 downto 0), + W => W_br_LC, --ATTENTION LC + Data => B_MemRE_OUT, RST => RST, CLK => CLK, QA => QA_IN_MUX, QB => C_DIEX_IN ); - B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" else B_LIDI_OUT ; + B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ; -- Instantiate pipeline DI_EX DI_EX : pipeline PORT MAP ( - OP_IN <= OP_LIDI_OUT, - A_IN <= A_LIDI_OUT, - B_IN <= B_DIEX_IN, - C_IN <= C_DIEX_IN, + OP_IN => OP_LIDI_OUT, + A_IN => A_LIDI_OUT, + B_IN => B_DIEX_IN, + C_IN => C_DIEX_IN, CLK => CLK, A_OUT => A_DIEX_OUT, B_OUT => B_DIEX_OUT, @@ -200,9 +201,9 @@ begin -- Instantiate alu UAL : alu PORT MAP ( - A <= B_DIEX_OUT, - B <= C_DIEX_OUT, - Ctrl_Alu <= Ctr_AlU_LC, + A => B_DIEX_OUT, + B => C_DIEX_OUT, + Ctrl_Alu =>Ctr_AlU_LC, N => N_ALU_OUT, O => O_ALU_OUT, Z => Z_ALU_OUT, @@ -216,10 +217,10 @@ begin -- Instantiate pipeline EX_Mem EX_Mem : pipeline PORT MAP ( - OP_IN <= OP_DIEX_OUT, - A_IN <= A_DIEX_OUT, - B_IN <= B_EXMem_IN, - C_IN <= x"00", + OP_IN => OP_DIEX_OUT, + A_IN => A_DIEX_OUT, + B_IN => B_EXMem_IN, + C_IN => x"00", CLK => CLK, A_OUT => A_EXMem_OUT, B_OUT => B_EXMem_OUT, @@ -236,9 +237,9 @@ begin B_EXMem_OUT; -- Instantiate banc de donnĂ©es data_memory: bm_data PORT MAP ( - addr_dm_MUX => IN_addr, - B_MemRE_IN => IN_data, - RW_LC => RW, + IN_addr => addr_dm_MUX, + IN_data => B_MemRE_IN, + RW => RW_LC, RST => RST, CLK => CLK, OUT_data => out_dm_MUX @@ -246,29 +247,25 @@ begin -- Instantiate pipeline Mem_RE Mem_RE : pipeline PORT MAP ( - OP_IN <= OP_EXMem_OUT, - A_IN <= A_EXMem_OUT, - B_IN <= OUT_data(15 downto 8), - C_IN <= x"00", + OP_IN => OP_EXMem_OUT, + A_IN => A_EXMem_OUT, + B_IN => B_EXMem_OUT, + C_IN => x"00", CLK => CLK, A_OUT => A_MemRE_OUT, B_OUT => B_MemRE_OUT, C_OUT => open, OP_OUT => OP_MemRE_OUT ); - - - -- Clock process definitions - CLK_process :process - begin - CLK <= '0'; - wait for CLK_period/2; - CLK <= '1'; - wait for CLK_period/2; - end process; - - - IP <= IP + "00000001"; + process + begin + wait until rising_edge(CLK); + if rst = '0' then + IP <= x"00"; + else + IP <= IP + "00000001"; + end if; + end process; end Behavioral; diff --git a/xilinx/ALU/processeur_summary.html b/xilinx/ALU/processeur_summary.html index 1cbf791..23acf3d 100644 --- a/xilinx/ALU/processeur_summary.html +++ b/xilinx/ALU/processeur_summary.html @@ -2,7 +2,7 @@ - + @@ -72,9 +72,9 @@  
alu Project Status
processeur Project Status
Project File: ALU.xise
- +
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datemar. mai 4 13:11:04 2021
ISIM Simulator LogOut of Datelun. mai 10 10:45:43 2021
-
Date Generated: 05/04/2021 - 15:22:09
+
Date Generated: 05/10/2021 - 10:47:06
\ No newline at end of file diff --git a/xilinx/ALU/tests/test_afc.wcfg b/xilinx/ALU/tests/test_afc.wcfg new file mode 100644 index 0000000..42c8451 --- /dev/null +++ b/xilinx/ALU/tests/test_afc.wcfg @@ -0,0 +1,149 @@ + + + + + + + + + + + + + + + + + + clk + clk + + + rst + rst + + + clk_period + clk_period + + + in_addr[7:0] + in_addr[7:0] + + + out_data[31:0] + out_data[31:0] + + + op_in[7:0] + op_in[7:0] + + + a_in[7:0] + a_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + op_in[7:0] + op_in[7:0] + + + a_in[7:0] + a_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + a_in[7:0] + a_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + op_in[7:0] + op_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + op_in[7:0] + op_in[7:0] + + + a_in[7:0] + a_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + w_addr[3:0] + w_addr[3:0] + + + w + w + + + data[7:0] + data[7:0] + + + registres[0:15] + registres[0:15] + + diff --git a/xilinx/ALU/tests/test_alu.wcfg b/xilinx/ALU/tests/test_alu.wcfg new file mode 100644 index 0000000..4a0a0b6 --- /dev/null +++ b/xilinx/ALU/tests/test_alu.wcfg @@ -0,0 +1,209 @@ + + + + + + + + + + + + + + + + + + clk + clk + + + rst + rst + + + clk_period + clk_period + + + in_addr[7:0] + in_addr[7:0] + + + out_data[31:0] + out_data[31:0] + + + op_in[7:0] + op_in[7:0] + + + a_in[7:0] + a_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + c_in[7:0] + c_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + c_out[7:0] + c_out[7:0] + + + op_in[7:0] + op_in[7:0] + + + a_in[7:0] + a_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + c_in[7:0] + c_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + c_out[7:0] + c_out[7:0] + + + a[7:0] + a[7:0] + + + b[7:0] + b[7:0] + + + ctrl_alu[2:0] + ctrl_alu[2:0] + + + s[7:0] + s[7:0] + + + op_in[7:0] + op_in[7:0] + + + a_in[7:0] + a_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + c_in[7:0] + c_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + c_out[7:0] + c_out[7:0] + + + op_in[7:0] + op_in[7:0] + + + a_in[7:0] + a_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + c_in[7:0] + c_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + c_out[7:0] + c_out[7:0] + + + a_addr[3:0] + a_addr[3:0] + + + b_addr[3:0] + b_addr[3:0] + + + w + w + + + qa[7:0] + qa[7:0] + + + w_addr[3:0] + w_addr[3:0] + + + data[7:0] + data[7:0] + + + registres[0:15] + registres[0:15] + + diff --git a/xilinx/ALU/tests/test_cop.wcfg b/xilinx/ALU/tests/test_cop.wcfg new file mode 100644 index 0000000..59ea4cd --- /dev/null +++ b/xilinx/ALU/tests/test_cop.wcfg @@ -0,0 +1,165 @@ + + + + + + + + + + + + + + + + + + clk + clk + + + rst + rst + + + clk_period + clk_period + + + in_addr[7:0] + in_addr[7:0] + + + out_data[31:0] + out_data[31:0] + + + a_in[7:0] + a_in[7:0] + + + op_in[7:0] + op_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + op_in[7:0] + op_in[7:0] + + + a_in[7:0] + a_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + op_in[7:0] + op_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + a_in[7:0] + a_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + op_in[7:0] + op_in[7:0] + + + a_in[7:0] + a_in[7:0] + + + b_in[7:0] + b_in[7:0] + + + op_out[7:0] + op_out[7:0] + + + a_out[7:0] + a_out[7:0] + + + b_out[7:0] + b_out[7:0] + + + a_addr[3:0] + a_addr[3:0] + + + w_addr[3:0] + w_addr[3:0] + + + b_addr[3:0] + b_addr[3:0] + + + w + w + + + data[7:0] + data[7:0] + + + qa[7:0] + qa[7:0] + + + registres[0:15] + registres[0:15] + + + qb[7:0] + qb[7:0] + +