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processeur.vhd 7.8KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 12:52:06 05/04/2021
  6. -- Design Name:
  7. -- Module Name: processeur - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  23. use IEEE.NUMERIC_STD.ALL;
  24. -- Uncomment the following library declaration if using
  25. -- arithmetic functions with Signed or Unsigned values
  26. --use IEEE.NUMERIC_STD.ALL;
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31. entity processeur is
  32. Port ( CLK: in STD_LOGIC ;
  33. RST : in STD_LOGIC);
  34. end processeur;
  35. architecture Behavioral of processeur is
  36. COMPONENT bm_instr
  37. PORT(
  38. IN_addr : IN std_logic_vector(7 downto 0);
  39. OUT_data : OUT std_logic_vector(31 downto 0);
  40. CLK : IN std_logic
  41. );
  42. END COMPONENT;
  43. COMPONENT pipeline
  44. PORT( OP_IN : in STD_LOGIC_VECTOR (7 downto 0);
  45. A_IN : in STD_LOGIC_VECTOR (7 downto 0);
  46. B_IN : in STD_LOGIC_VECTOR (7 downto 0);
  47. C_IN : in STD_LOGIC_VECTOR (7 downto 0);
  48. CLK : IN std_logic;
  49. OP_OUT : out STD_LOGIC_VECTOR (7 downto 0);
  50. A_OUT : out STD_LOGIC_VECTOR (7 downto 0);
  51. B_OUT : out STD_LOGIC_VECTOR (7 downto 0);
  52. C_OUT : out STD_LOGIC_VECTOR (7 downto 0)
  53. );
  54. END COMPONENT;
  55. COMPONENT br
  56. PORT(
  57. A_addr : IN std_logic_vector(3 downto 0);
  58. B_addr : IN std_logic_vector(3 downto 0);
  59. W_addr : IN std_logic_vector(3 downto 0);
  60. W : IN std_logic;
  61. Data : IN std_logic_vector(7 downto 0);
  62. RST : IN std_logic;
  63. CLK : IN std_logic;
  64. QA : OUT std_logic_vector(7 downto 0);
  65. QB : OUT std_logic_vector(7 downto 0)
  66. );
  67. END COMPONENT;
  68. COMPONENT alu
  69. PORT(
  70. A : IN std_logic_vector(7 downto 0);
  71. B : IN std_logic_vector(7 downto 0);
  72. Ctrl_Alu : IN std_logic_vector(2 downto 0);
  73. N : OUT std_logic;
  74. O : OUT std_logic;
  75. Z : OUT std_logic;
  76. C : OUT std_logic;
  77. S : OUT std_logic_vector(7 downto 0)
  78. );
  79. END COMPONENT;
  80. COMPONENT bm_data
  81. PORT(
  82. IN_addr : IN std_logic_vector(7 downto 0);
  83. IN_data : IN std_logic_vector(7 downto 0);
  84. RW : IN std_logic;
  85. RST : IN std_logic;
  86. CLK : IN std_logic;
  87. OUT_data : OUT std_logic_vector(7 downto 0)
  88. );
  89. END COMPONENT;
  90. --Inputs
  91. signal IP : std_logic_vector(7 downto 0) := (others => '0');
  92. signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0');
  93. signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
  94. signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
  95. --Outputs
  96. signal OUT_data : std_logic_vector(31 downto 0);
  97. signal OP_LIDI_OUT : std_logic_vector(7 downto 0);
  98. signal A_LIDI_OUT : std_logic_vector(7 downto 0);
  99. signal B_LIDI_OUT : std_logic_vector(7 downto 0);
  100. signal C_LIDI_OUT : std_logic_vector(7 downto 0);
  101. signal OP_DIEX_OUT : std_logic_vector(7 downto 0);
  102. signal A_DIEX_OUT : std_logic_vector(7 downto 0);
  103. signal B_DIEX_OUT : std_logic_vector(7 downto 0);
  104. signal C_DIEX_OUT : std_logic_vector(7 downto 0);
  105. signal O_ALU_OUT : std_logic;
  106. signal N_ALU_OUT : std_logic;
  107. signal Z_ALU_OUT : std_logic;
  108. signal C_ALU_OUT : std_logic;
  109. signal A_EXMem_OUT : std_logic_vector(7 downto 0);
  110. signal B_EXMem_OUT : std_logic_vector(7 downto 0);
  111. signal OP_EXMem_OUT : std_logic_vector(7 downto 0);
  112. signal A_MemRE_OUT : std_logic_vector(7 downto 0);
  113. signal B_MemRE_OUT : std_logic_vector(7 downto 0);
  114. signal OP_MemRE_OUT : std_logic_vector(7 downto 0);
  115. --AUX
  116. signal Ctr_ALU_LC : std_logic_vector(2 downto 0);
  117. signal RW_LC : std_logic;
  118. signal addr_dm_MUX : std_logic_vector(7 downto 0);
  119. signal in_dm_MUX : std_logic_vector(7 downto 0);
  120. signal out_dm_MUX : std_logic_vector(7 downto 0);
  121. signal B_EXMem_IN : std_logic_vector(7 downto 0);
  122. signal W_br_LC : std_logic;
  123. signal S_IN_MUX : std_logic_vector(7 downto 0);
  124. signal B_MemRE_IN : std_logic_vector(7 downto 0);
  125. begin
  126. -- Instantiate adresse des instructions
  127. addr_instructions: bm_instr PORT MAP (
  128. IN_addr => IP,
  129. OUT_data => OUT_data,
  130. CLK => CLK
  131. );
  132. -- Instantiate pipeline LI_LD
  133. LI_LD : pipeline PORT MAP (
  134. OP_IN => OUT_data(31 downto 24),
  135. A_IN => OUT_data(23 downto 16),
  136. B_IN => OUT_data(15 downto 8),
  137. C_IN => OUT_data(7 downto 0),
  138. CLK => CLK,
  139. A_OUT => A_LIDI_OUT,
  140. B_OUT => B_LIDI_OUT,
  141. C_OUT => C_LIDI_OUT,
  142. OP_OUT => OP_LIDI_OUT
  143. );
  144. W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else
  145. '0';
  146. -- Instanciate banc de registre
  147. banc_registres : br PORT MAP (
  148. A_addr => B_LIDI_OUT(3 downto 0),
  149. B_addr => C_LIDI_OUT(3 downto 0),
  150. W_addr => A_MemRE_OUT(3 downto 0),
  151. W => W_br_LC, --ATTENTION LC
  152. Data => B_MemRE_OUT,
  153. RST => RST,
  154. CLK => CLK,
  155. QA => QA_IN_MUX,
  156. QB => C_DIEX_IN
  157. );
  158. B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" or OP_LIDI_OUT = x"08" else B_LIDI_OUT ;
  159. -- Instantiate pipeline DI_EX
  160. DI_EX : pipeline PORT MAP (
  161. OP_IN => OP_LIDI_OUT,
  162. A_IN => A_LIDI_OUT,
  163. B_IN => B_DIEX_IN,
  164. C_IN => C_DIEX_IN,
  165. CLK => CLK,
  166. A_OUT => A_DIEX_OUT,
  167. B_OUT => B_DIEX_OUT,
  168. C_OUT => C_DIEX_OUT,
  169. OP_OUT => OP_DIEX_OUT
  170. );
  171. Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else
  172. "010" when OP_DIEX_OUT = x"03" else
  173. "011" when OP_DIEX_OUT = x"02" else
  174. "000";
  175. -- Instantiate alu
  176. UAL : alu PORT MAP (
  177. A => B_DIEX_OUT,
  178. B => C_DIEX_OUT,
  179. Ctrl_Alu =>Ctr_AlU_LC,
  180. N => N_ALU_OUT,
  181. O => O_ALU_OUT,
  182. Z => Z_ALU_OUT,
  183. C => C_ALU_OUT,
  184. S => S_IN_MUX
  185. );
  186. B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else
  187. B_DIEX_OUT ;
  188. -- Instantiate pipeline EX_Mem
  189. EX_Mem : pipeline PORT MAP (
  190. OP_IN => OP_DIEX_OUT,
  191. A_IN => A_DIEX_OUT,
  192. B_IN => B_EXMem_IN,
  193. C_IN => x"00",
  194. CLK => CLK,
  195. A_OUT => A_EXMem_OUT,
  196. B_OUT => B_EXMem_OUT,
  197. C_OUT => open,
  198. OP_OUT => OP_EXMem_OUT
  199. );
  200. RW_LC <= '0' when OP_EXMem_OUT = x"08" else
  201. '1';
  202. addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
  203. A_EXMem_OUT;
  204. in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08";
  205. B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" or OP_EXMem_OUT = x"07" else
  206. B_EXMem_OUT;
  207. -- Instantiate banc de données
  208. data_memory: bm_data PORT MAP (
  209. IN_addr => addr_dm_MUX,
  210. IN_data => in_dm_MUX,
  211. RW => RW_LC,
  212. RST => RST,
  213. CLK => CLK,
  214. OUT_data => out_dm_MUX
  215. );
  216. -- Instantiate pipeline Mem_RE
  217. Mem_RE : pipeline PORT MAP (
  218. OP_IN => OP_EXMem_OUT,
  219. A_IN => A_EXMem_OUT,
  220. B_IN => B_MemRE_IN,
  221. C_IN => x"00",
  222. CLK => CLK,
  223. A_OUT => A_MemRE_OUT,
  224. B_OUT => B_MemRE_OUT,
  225. C_OUT => open,
  226. OP_OUT => OP_MemRE_OUT
  227. );
  228. process
  229. begin
  230. wait until rising_edge(CLK);
  231. if rst = '0' then
  232. IP <= x"00";
  233. else
  234. IP <= IP + "00000001";
  235. end if;
  236. end process;
  237. end Behavioral;