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Tests processeur OK

Foussats Morgane 3 years ago
parent
c06ce09028
commit
9b69ceadef
41 changed files with 801 additions and 278 deletions
Split View Show Diff Stats
  1. 23
    4
      xilinx/ALU/ALU.gise
  2. 3
    3
      xilinx/ALU/ALU.xise
  3. 1
    1
      xilinx/ALU/_xmsgs/pn_parser.xmsgs
  4. 13
    1
      xilinx/ALU/bm_instr.vhd
  5. 6
    6
      xilinx/ALU/fuse.log
  6. 14
    13
      xilinx/ALU/iseconfig/ALU.projectmgr
  7. 2
    2
      xilinx/ALU/iseconfig/processeur.xreport
  8. 126
    1
      xilinx/ALU/isim.log
  9. 1
    12
      xilinx/ALU/isim/isim_usage_statistics.html
  10. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat
  11. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat
  12. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat
  13. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat
  14. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
  15. 3
    22
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log
  16. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat
  17. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe
  18. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1
  19. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat
  20. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat
  21. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat
  22. 1
    1
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c
  23. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat
  24. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o
  25. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat
  26. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat
  27. 272
    206
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c
  28. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat
  29. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o
  30. BIN
      xilinx/ALU/isim/work/alu.vdb
  31. BIN
      xilinx/ALU/isim/work/bm_data.vdb
  32. BIN
      xilinx/ALU/isim/work/bm_instr.vdb
  33. BIN
      xilinx/ALU/isim/work/br.vdb
  34. BIN
      xilinx/ALU/isim/work/pipeline.vdb
  35. BIN
      xilinx/ALU/isim/work/process_test.vdb
  36. BIN
      xilinx/ALU/isim/work/processeur.vdb
  37. BIN
      xilinx/ALU/process_test_isim_beh.wdb
  38. 4
    4
      xilinx/ALU/processeur.vhd
  39. 2
    2
      xilinx/ALU/processeur_summary.html
  40. 165
    0
      xilinx/ALU/tests/test_load.wcfg
  41. 165
    0
      xilinx/ALU/tests/test_store.wcfg

+ 23
- 4
xilinx/ALU/ALU.gise View File 

@@ -49,9 +49,13 @@
49 49 
       <status xil_pn:value="SuccessfullyRun"/>
50 50 
       <status xil_pn:value="ReadyToRun"/>
51 51 
     </transform>
52 
-    <transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620641821">
52 
+    <transform xil_pn:end_ts="1620740667" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620740667">
53 53 
       <status xil_pn:value="SuccessfullyRun"/>
54 54 
       <status xil_pn:value="ReadyToRun"/>
55 
+      <status xil_pn:value="OutOfDateForInputs"/>
56 
+      <status xil_pn:value="OutOfDateForOutputs"/>
57 
+      <status xil_pn:value="InputChanged"/>
58 
+      <status xil_pn:value="OutputChanged"/>
55 59 
       <outfile xil_pn:name="alu.vhd"/>
56 60 
       <outfile xil_pn:name="alu_test.vhd"/>
57 61 
       <outfile xil_pn:name="bm.vhd"/>

@@ -76,9 +80,14 @@
76 80 
       <status xil_pn:value="SuccessfullyRun"/>
77 81 
       <status xil_pn:value="ReadyToRun"/>
78 82 
     </transform>
79 
-    <transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620641821">
83 
+    <transform xil_pn:end_ts="1620740667" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620740667">
80 84 
       <status xil_pn:value="SuccessfullyRun"/>
81 85 
       <status xil_pn:value="ReadyToRun"/>
86 
+      <status xil_pn:value="OutOfDateForInputs"/>
87 
+      <status xil_pn:value="OutOfDateForPredecessor"/>
88 
+      <status xil_pn:value="OutOfDateForOutputs"/>
89 
+      <status xil_pn:value="InputChanged"/>
90 
+      <status xil_pn:value="OutputChanged"/>
82 91 
       <outfile xil_pn:name="alu.vhd"/>
83 92 
       <outfile xil_pn:name="alu_test.vhd"/>
84 93 
       <outfile xil_pn:name="bm.vhd"/>

@@ -91,9 +100,15 @@
91 100 
       <outfile xil_pn:name="process_test.vhd"/>
92 101 
       <outfile xil_pn:name="processeur.vhd"/>
93 102 
     </transform>
94 
-    <transform xil_pn:end_ts="1620641822" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1620641821">
103 
+    <transform xil_pn:end_ts="1620740670" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1620740667">
95 104 
       <status xil_pn:value="SuccessfullyRun"/>
96 105 
       <status xil_pn:value="ReadyToRun"/>
106 
+      <status xil_pn:value="OutOfDateForInputs"/>
107 
+      <status xil_pn:value="OutOfDateForProperties"/>
108 
+      <status xil_pn:value="OutOfDateForPredecessor"/>
109 
+      <status xil_pn:value="OutOfDateForOutputs"/>
110 
+      <status xil_pn:value="InputChanged"/>
111 
+      <status xil_pn:value="OutputChanged"/>
97 112 
       <outfile xil_pn:name="fuse.log"/>
98 113 
       <outfile xil_pn:name="isim"/>
99 114 
       <outfile xil_pn:name="isim.log"/>

@@ -101,9 +116,13 @@
101 116 
       <outfile xil_pn:name="process_test_isim_beh.exe"/>
102 117 
       <outfile xil_pn:name="xilinxsim.ini"/>
103 118 
     </transform>
104 
-    <transform xil_pn:end_ts="1620641823" xil_pn:in_ck="482655878171119177" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1620641822">
119 
+    <transform xil_pn:end_ts="1620740670" xil_pn:in_ck="482655878171119177" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1620740670">
105 120 
       <status xil_pn:value="SuccessfullyRun"/>
106 121 
       <status xil_pn:value="ReadyToRun"/>
122 
+      <status xil_pn:value="OutOfDateForProperties"/>
123 
+      <status xil_pn:value="OutOfDateForPredecessor"/>
124 
+      <status xil_pn:value="OutOfDateForOutputs"/>
125 
+      <status xil_pn:value="OutputChanged"/>
107 126 
       <outfile xil_pn:name="isim.cmd"/>
108 127 
       <outfile xil_pn:name="isim.log"/>
109 128 
       <outfile xil_pn:name="process_test_isim_beh.wdb"/>

+ 3
- 3
xilinx/ALU/ALU.xise View File 

@@ -311,8 +311,8 @@
311 311 
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
312 312 
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
313 313 
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
314 
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/process_test" xil_pn:valueState="non-default"/>
315 
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.process_test" xil_pn:valueState="non-default"/>
314 
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/process_test/uut/data_memory" xil_pn:valueState="non-default"/>
315 
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.bm_data" xil_pn:valueState="non-default"/>
316 316 
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
317 317 
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
318 318 
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
 
@@ -330,7 +330,7 @@
330 330 
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
331 331 
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
332 332 
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
333 
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.process_test" xil_pn:valueState="default"/>
333 
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.bm_data" xil_pn:valueState="default"/>
334 334 
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
335 335 
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
336 336 
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>

+ 1
- 1
xilinx/ALU/_xmsgs/pn_parser.xmsgs View File 

@@ -8,7 +8,7 @@
8 8 
 <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
9 9
10 10 
 <messages>
11 
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd&quot; into library work</arg>
11 
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd&quot; into library work</arg>
12 12 
 </msg>
13 13
14 14 
 </messages>

+ 13
- 1
xilinx/ALU/bm_instr.vhd View File 

@@ -37,9 +37,21 @@ type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
37 37 
 --signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
38 38
39 39 
 --test afc cop
40 
-signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
40 
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
41 41 
 --test add
42 42 
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
43 
+--test sub
44 
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000011000000110000000100000010", others =>"00000000000000000000000000000000");
45 
+--test mul
46 
+signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000010000000110000000100000010", others =>"00000000000000000000000000000000");
47 
+
48 
+--test store
49 
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
50 
+
51 
+--test load
52 
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", 15 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000");
53 
+
54 
+
43 55 
 begin
44 56
45 57 
 		OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));

+ 6
- 6
xilinx/ALU/fuse.log View File 

@@ -1,7 +1,7 @@
1 1 
 Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test"
2 2 
 ISim O.87xd (signature 0x8ddf5b5d)
3 
-Number of CPUs detected in this system: 12
4 
-Turning on mult-threading, number of parallel sub-compilation jobs: 24
3 
+Number of CPUs detected in this system: 8
4 
+Turning on mult-threading, number of parallel sub-compilation jobs: 16
5 5 
 Determining compilation order of HDL files
6 6 
 Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work
7 7 
 Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work
 
@@ -13,7 +13,7 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU
13 13 
 Starting static elaboration
14 14 
 Completed static elaboration
15 15 
 Fuse Memory Usage: 98520 KB
16 
-Fuse CPU Usage: 760 ms
16 
+Fuse CPU Usage: 880 ms
17 17 
 Compiling package standard
18 18 
 Compiling package std_logic_1164
19 19 
 Compiling package std_logic_arith
 
@@ -30,6 +30,6 @@ Time Resolution for simulation is 1ps.
30 30 
 Waiting for 1 sub-compilation(s) to finish...
31 31 
 Compiled 18 VHDL Units
32 32 
 Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe
33 
-Fuse Memory Usage: 1723208 KB
34 
-Fuse CPU Usage: 850 ms
35 
-GCC CPU Usage: 120 ms
33 
+Fuse Memory Usage: 1198916 KB
34 
+Fuse CPU Usage: 1010 ms
35 
+GCC CPU Usage: 140 ms

+ 14
- 13
xilinx/ALU/iseconfig/ALU.projectmgr View File 

@@ -9,13 +9,13 @@
9 9 
          <ClosedNodesVersion>2</ClosedNodesVersion>
10 10 
       </ClosedNodes>
11 11 
       <SelectedItems>
12 
-         <SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
12 
+         <SelectedItem>addr_instructions - bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</SelectedItem>
13 13 
       </SelectedItems>
14 14 
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
15 15 
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
16 
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
16 
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001c5000000020000000000000000000000000200000064ffffffff000000810000000300000002000001c50000000100000003000000000000000100000003</ViewHeaderState>
17 17 
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
18 
-      <CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
18 
+      <CurrentItem>addr_instructions - bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</CurrentItem>
19 19 
    </ItemView>
20 20 
    <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
21 21 
       <ClosedNodes>
 
@@ -23,13 +23,13 @@
23 23 
          <ClosedNode>Design Utilities</ClosedNode>
24 24 
       </ClosedNodes>
25 25 
       <SelectedItems>
26 
-         <SelectedItem></SelectedItem>
26 
+         <SelectedItem/>
27 27 
       </SelectedItems>
28 28 
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
29 29 
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
30 30 
       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
31 31 
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
32 
-      <CurrentItem></CurrentItem>
32 
+      <CurrentItem/>
33 33 
    </ItemView>
34 34 
    <ItemView guiview="File" >
35 35 
       <ClosedNodes>
 
@@ -50,7 +50,7 @@
50 50 
       <SelectedItems/>
51 51 
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
52 52 
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
53 
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000148000000010001000100000000000000000000000064ffffffff000000810000000000000001000001480000000100000000</ViewHeaderState>
53 
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000132000000010001000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000</ViewHeaderState>
54 54 
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
55 55 
       <CurrentItem>work</CurrentItem>
56 56 
    </ItemView>
 
@@ -79,41 +79,42 @@
79 79 
          <ClosedNode>/bm_data_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_data_test.vhd</ClosedNode>
80 80 
          <ClosedNode>/bm_instr_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_instr_test.vhd</ClosedNode>
81 81 
          <ClosedNode>/br_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|br_test.vhd</ClosedNode>
82 
+         <ClosedNode>/processeur - Behavioral |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|processeur.vhd</ClosedNode>
82 83 
       </ClosedNodes>
83 84 
       <SelectedItems>
84 
-         <SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
85 
+         <SelectedItem>data_memory - bm_data - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd)</SelectedItem>
85 86 
       </SelectedItems>
86 87 
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
87 88 
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
88 
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
89 
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001d9000000020000000000000000000000000200000064ffffffff000000810000000300000002000001d90000000100000003000000000000000100000003</ViewHeaderState>
89 90 
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
90 
-      <CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
91 
+      <CurrentItem>data_memory - bm_data - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd)</CurrentItem>
91 92 
    </ItemView>
92 93 
    <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
93 94 
       <ClosedNodes>
94 95 
          <ClosedNodesVersion>1</ClosedNodesVersion>
95 96 
       </ClosedNodes>
96 97 
       <SelectedItems>
97 
-         <SelectedItem></SelectedItem>
98 
+         <SelectedItem/>
98 99 
       </SelectedItems>
99 100 
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
100 101 
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
101 102 
       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
102 103 
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
103 
-      <CurrentItem></CurrentItem>
104 
+      <CurrentItem/>
104 105 
    </ItemView>
105 106 
    <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
106 107 
       <ClosedNodes>
107 108 
          <ClosedNodesVersion>1</ClosedNodesVersion>
108 109 
       </ClosedNodes>
109 110 
       <SelectedItems>
110 
-         <SelectedItem>Simulate Behavioral Model</SelectedItem>
111 
+         <SelectedItem></SelectedItem>
111 112 
       </SelectedItems>
112 113 
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
113 114 
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
114 115 
       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
115 116 
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
116 
-      <CurrentItem>Simulate Behavioral Model</CurrentItem>
117 
+      <CurrentItem></CurrentItem>
117 118 
    </ItemView>
118 119 
    <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
119 120 
       <ClosedNodes>

+ 2
- 2
xilinx/ALU/iseconfig/processeur.xreport View File 

@@ -1,11 +1,11 @@
1 1 
 <?xml version='1.0' encoding='UTF-8'?>
2 2 
 <report-views version="2.0" >
3 3 
  <header>
4 
-  <DateModified>2021-05-10T10:47:06</DateModified>
4 
+  <DateModified>2021-05-11T15:38:05</DateModified>
5 5 
   <ModuleName>processeur</ModuleName>
6 6 
   <SummaryTimeStamp>Unknown</SummaryTimeStamp>
7 7 
   <SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath>
8 
-  <ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU</ImplementationReportsDirectory>
8 
+  <ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/</ImplementationReportsDirectory>
9 9 
   <DateInitialized>2021-05-10T09:34:56</DateInitialized>
10 10 
   <EnableMessageFiltering>false</EnableMessageFiltering>
11 11 
  </header>

+ 126
- 1
xilinx/ALU/isim.log View File 

@@ -45,4 +45,129 @@ at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_IN
45 45 
 at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
46 46 
 at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
47 47 
 at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
48 
-# exit 0
48 
+ISim O.87xd (signature 0x8ddf5b5d)
49 
+WARNING: A WEBPACK license was found.
50 
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
51 
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
52 
+This is a Lite version of ISim.
53 
+# run 1000 ns
54 
+Simulator is doing circuit initialization process.
55 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
56 
+Finished circuit initialization process.
57 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
58 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
59 
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
60 
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
61 
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
62 
+ISim O.87xd (signature 0x8ddf5b5d)
63 
+WARNING: A WEBPACK license was found.
64 
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
65 
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
66 
+This is a Lite version of ISim.
67 
+# run 1000 ns
68 
+Simulator is doing circuit initialization process.
69 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
70 
+Finished circuit initialization process.
71 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
72 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
73 
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
74 
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
75 
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
76 
+ISim O.87xd (signature 0x8ddf5b5d)
77 
+WARNING: A WEBPACK license was found.
78 
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
79 
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
80 
+This is a Lite version of ISim.
81 
+# run 1000 ns
82 
+Simulator is doing circuit initialization process.
83 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
84 
+Finished circuit initialization process.
85 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
86 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
87 
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
88 
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
89 
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
90 
+ISim O.87xd (signature 0x8ddf5b5d)
91 
+WARNING: A WEBPACK license was found.
92 
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
93 
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
94 
+This is a Lite version of ISim.
95 
+# run 1000 ns
96 
+Simulator is doing circuit initialization process.
97 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
98 
+Finished circuit initialization process.
99 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
100 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
101 
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
102 
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
103 
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
104 
+ISim O.87xd (signature 0x8ddf5b5d)
105 
+WARNING: A WEBPACK license was found.
106 
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
107 
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
108 
+This is a Lite version of ISim.
109 
+# run 1000 ns
110 
+Simulator is doing circuit initialization process.
111 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
112 
+Finished circuit initialization process.
113 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
114 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
115 
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
116 
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
117 
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
118 
+ISim O.87xd (signature 0x8ddf5b5d)
119 
+WARNING: A WEBPACK license was found.
120 
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
121 
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
122 
+This is a Lite version of ISim.
123 
+# run 1000 ns
124 
+Simulator is doing circuit initialization process.
125 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
126 
+Finished circuit initialization process.
127 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
128 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
129 
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
130 
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
131 
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
132 
+ISim O.87xd (signature 0x8ddf5b5d)
133 
+WARNING: A WEBPACK license was found.
134 
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
135 
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
136 
+This is a Lite version of ISim.
137 
+# run 1000 ns
138 
+Simulator is doing circuit initialization process.
139 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
140 
+Finished circuit initialization process.
141 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
142 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
143 
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
144 
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
145 
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
146 
+ISim O.87xd (signature 0x8ddf5b5d)
147 
+WARNING: A WEBPACK license was found.
148 
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
149 
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
150 
+This is a Lite version of ISim.
151 
+# run 1000 ns
152 
+Simulator is doing circuit initialization process.
153 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
154 
+Finished circuit initialization process.
155 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
156 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
157 
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
158 
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
159 
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
160 
+ISim O.87xd (signature 0x8ddf5b5d)
161 
+WARNING: A WEBPACK license was found.
162 
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
163 
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
164 
+This is a Lite version of ISim.
165 
+# run 1000 ns
166 
+Simulator is doing circuit initialization process.
167 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
168 
+Finished circuit initialization process.
169 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
170 
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
171 
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
172 
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
173 
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

+ 1
- 12
xilinx/ALU/isim/isim_usage_statistics.html View File 

@@ -2,15 +2,4 @@
2 2 
 <xtag-section name="ISimStatistics">
3 3 
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
4 4 
 <TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
5 
-<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>850 ms, 1723208 KB</xtag-isim-property-value></TD></TR>
6 
-
7 
-<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>109</xtag-isim-property-value></TD></TR>
8 
-<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10695</xtag-isim-property-value></TD></TR>
9 
-<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>14</xtag-isim-property-value></TD></TR>
10 
-<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>31</xtag-isim-property-value></TD></TR>
11 
-<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
12 
-<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.04 sec, 264146 KB</xtag-isim-property-value></TD></TR>
13 
-<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
14 
-<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
15 
-</xtag-section>
16 
-</TABLE>
5 
+<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1010 ms, 1198916 KB</xtag-isim-property-value></TD></TR>

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xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat View File


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+ 3
- 22
xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log View File 

@@ -2,28 +2,9 @@ Command line:
2 2 
    process_test_isim_beh.exe
3 3 
      -simmode  gui
4 4 
      -simrunnum  0
5 
-     -socket  43981
5 
+     -socket  54129
6 6
7 
-Mon May 10 12:31:07 2021
7 
+Tue May 11 16:30:48 2021
8 8
9 9
10 
- Elaboration Time: 0.01 sec
11 
-
12 
- Current Memory Usage: 189.698 Meg
13 
-
14 
- Total Signals          : 109
15 
- Total Nets             : 10695
16 
- Total Signal Drivers   : 44
17 
- Total Blocks           : 14
18 
- Total Primitive Blocks : 12
19 
- Total Processes        : 31
20 
- Total Traceable Variables  : 16
21 
- Total Scalar Nets and Variables : 11197
22 
-Total Line Count : 66
23 
-
24 
- Total Simulation Time: 0.04 sec
25 
-
26 
- Current Memory Usage: 265.2 Meg
27 
-
28 
-Mon May 10 12:32:41 2021
29 
-
10 
+ Elaboration Time: 0.02 sec

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat View File


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xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe View File


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xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1 View File


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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat View File


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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat View File


+ 1
- 1
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c View File 

@@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0)
45 45 
     char *t14;
46 46 
     char *t15;
47 47
48 
-LAB0:    xsi_set_current_line(45, ng0);
48 
+LAB0:    xsi_set_current_line(57, ng0);
49 49
50 50 
 LAB3:    t1 = (t0 + 1512U);
51 51 
     t2 = *((char **)t1);

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat View File


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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o View File


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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat View File


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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat View File


+ 272
- 206
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c View File 

@@ -298,193 +298,223 @@ LAB24:    goto LAB2;
298 298
299 299 
 static void work_a_4150868852_3212880686_p_1(char *t0)
300 300 
 {
301 
-    char t9[16];
302 
-    char t18[16];
303 
-    char t26[16];
304 
-    char t34[16];
305 
-    char t42[16];
301 
+    char t10[16];
302 
+    char t19[16];
303 
+    char t27[16];
304 
+    char t35[16];
305 
+    char t43[16];
306 
+    char t51[16];
306 307 
     unsigned char t1;
307 308 
     unsigned char t2;
308 309 
     unsigned char t3;
309 310 
     unsigned char t4;
310 
-    char *t5;
311 
+    unsigned char t5;
311 312 
     char *t6;
312 313 
     char *t7;
313 
-    char *t10;
314 
+    char *t8;
314 315 
     char *t11;
315 
-    int t12;
316 
-    unsigned int t13;
317 
-    unsigned char t14;
318 
-    char *t15;
316 
+    char *t12;
317 
+    int t13;
318 
+    unsigned int t14;
319 
+    unsigned char t15;
319 320 
     char *t16;
320 
-    char *t19;
321 
+    char *t17;
321 322 
     char *t20;
322 
-    int t21;
323 
-    unsigned char t22;
324 
-    char *t23;
323 
+    char *t21;
324 
+    int t22;
325 
+    unsigned char t23;
325 326 
     char *t24;
326 
-    char *t27;
327 
+    char *t25;
327 328 
     char *t28;
328 
-    int t29;
329 
-    unsigned char t30;
330 
-    char *t31;
329 
+    char *t29;
330 
+    int t30;
331 
+    unsigned char t31;
331 332 
     char *t32;
332 
-    char *t35;
333 
+    char *t33;
333 334 
     char *t36;
334 
-    int t37;
335 
-    unsigned char t38;
336 
-    char *t39;
335 
+    char *t37;
336 
+    int t38;
337 
+    unsigned char t39;
337 338 
     char *t40;
338 
-    char *t43;
339 
+    char *t41;
339 340 
     char *t44;
340 
-    int t45;
341 
-    unsigned char t46;
342 
-    char *t47;
341 
+    char *t45;
342 
+    int t46;
343 
+    unsigned char t47;
343 344 
     char *t48;
344 345 
     char *t49;
345 
-    char *t50;
346 
-    char *t51;
347 346 
     char *t52;
348 347 
     char *t53;
349 
-    char *t54;
350 
-    char *t55;
348 
+    int t54;
349 
+    unsigned char t55;
351 350 
     char *t56;
352 351 
     char *t57;
353 352 
     char *t58;
353 
+    char *t59;
354 
+    char *t60;
355 
+    char *t61;
356 
+    char *t62;
357 
+    char *t63;
358 
+    char *t64;
359 
+    char *t65;
360 
+    char *t66;
361 
+    char *t67;
354 362
355 363 
 LAB0:    xsi_set_current_line(181, ng0);
356 
-    t5 = (t0 + 2152U);
357 
-    t6 = *((char **)t5);
358 
-    t5 = (t0 + 17640U);
359 
-    t7 = (t0 + 18323);
360 
-    t10 = (t9 + 0U);
364 
+    t6 = (t0 + 2152U);
365 
+    t7 = *((char **)t6);
366 
+    t6 = (t0 + 17640U);
367 
+    t8 = (t0 + 18323);
361 368 
     t11 = (t10 + 0U);
362 
-    *((int *)t11) = 0;
363 
-    t11 = (t10 + 4U);
364 
-    *((int *)t11) = 7;
365 
-    t11 = (t10 + 8U);
366 
-    *((int *)t11) = 1;
367 
-    t12 = (7 - 0);
368 
-    t13 = (t12 * 1);
369 
-    t13 = (t13 + 1);
370 
-    t11 = (t10 + 12U);
371 
-    *((unsigned int *)t11) = t13;
372 
-    t14 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t6, t5, t7, t9);
373 
-    if (t14 == 1)
374 
-        goto LAB14;
369 
+    t12 = (t11 + 0U);
370 
+    *((int *)t12) = 0;
371 
+    t12 = (t11 + 4U);
372 
+    *((int *)t12) = 7;
373 
+    t12 = (t11 + 8U);
374 
+    *((int *)t12) = 1;
375 
+    t13 = (7 - 0);
376 
+    t14 = (t13 * 1);
377 
+    t14 = (t14 + 1);
378 
+    t12 = (t11 + 12U);
379 
+    *((unsigned int *)t12) = t14;
380 
+    t15 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t7, t6, t8, t10);
381 
+    if (t15 == 1)
382 
+        goto LAB17;
375 383
376 
-LAB15:    t11 = (t0 + 2152U);
377 
-    t15 = *((char **)t11);
378 
-    t11 = (t0 + 17640U);
379 
-    t16 = (t0 + 18331);
380 
-    t19 = (t18 + 0U);
384 
+LAB18:    t12 = (t0 + 2152U);
385 
+    t16 = *((char **)t12);
386 
+    t12 = (t0 + 17640U);
387 
+    t17 = (t0 + 18331);
381 388 
     t20 = (t19 + 0U);
382 
-    *((int *)t20) = 0;
383 
-    t20 = (t19 + 4U);
384 
-    *((int *)t20) = 7;
385 
-    t20 = (t19 + 8U);
386 
-    *((int *)t20) = 1;
387 
-    t21 = (7 - 0);
388 
-    t13 = (t21 * 1);
389 
-    t13 = (t13 + 1);
390 
-    t20 = (t19 + 12U);
391 
-    *((unsigned int *)t20) = t13;
392 
-    t22 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t15, t11, t16, t18);
393 
-    t4 = t22;
389 
+    t21 = (t20 + 0U);
390 
+    *((int *)t21) = 0;
391 
+    t21 = (t20 + 4U);
392 
+    *((int *)t21) = 7;
393 
+    t21 = (t20 + 8U);
394 
+    *((int *)t21) = 1;
395 
+    t22 = (7 - 0);
396 
+    t14 = (t22 * 1);
397 
+    t14 = (t14 + 1);
398 
+    t21 = (t20 + 12U);
399 
+    *((unsigned int *)t21) = t14;
400 
+    t23 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t16, t12, t17, t19);
401 
+    t5 = t23;
402 
+
403 
+LAB19:    if (t5 == 1)
404 
+        goto LAB14;
405 
+
406 
+LAB15:    t21 = (t0 + 2152U);
407 
+    t24 = *((char **)t21);
408 
+    t21 = (t0 + 17640U);
409 
+    t25 = (t0 + 18339);
410 
+    t28 = (t27 + 0U);
411 
+    t29 = (t28 + 0U);
412 
+    *((int *)t29) = 0;
413 
+    t29 = (t28 + 4U);
414 
+    *((int *)t29) = 7;
415 
+    t29 = (t28 + 8U);
416 
+    *((int *)t29) = 1;
417 
+    t30 = (7 - 0);
418 
+    t14 = (t30 * 1);
419 
+    t14 = (t14 + 1);
420 
+    t29 = (t28 + 12U);
421 
+    *((unsigned int *)t29) = t14;
422 
+    t31 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t24, t21, t25, t27);
423 
+    t4 = t31;
394 424
395 425 
 LAB16:    if (t4 == 1)
396 426 
         goto LAB11;
397 427
398 
-LAB12:    t20 = (t0 + 2152U);
399 
-    t23 = *((char **)t20);
400 
-    t20 = (t0 + 17640U);
401 
-    t24 = (t0 + 18339);
402 
-    t27 = (t26 + 0U);
403 
-    t28 = (t27 + 0U);
404 
-    *((int *)t28) = 0;
405 
-    t28 = (t27 + 4U);
406 
-    *((int *)t28) = 7;
407 
-    t28 = (t27 + 8U);
408 
-    *((int *)t28) = 1;
409 
-    t29 = (7 - 0);
410 
-    t13 = (t29 * 1);
411 
-    t13 = (t13 + 1);
412 
-    t28 = (t27 + 12U);
413 
-    *((unsigned int *)t28) = t13;
414 
-    t30 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t23, t20, t24, t26);
415 
-    t3 = t30;
428 
+LAB12:    t29 = (t0 + 2152U);
429 
+    t32 = *((char **)t29);
430 
+    t29 = (t0 + 17640U);
431 
+    t33 = (t0 + 18347);
432 
+    t36 = (t35 + 0U);
433 
+    t37 = (t36 + 0U);
434 
+    *((int *)t37) = 0;
435 
+    t37 = (t36 + 4U);
436 
+    *((int *)t37) = 7;
437 
+    t37 = (t36 + 8U);
438 
+    *((int *)t37) = 1;
439 
+    t38 = (7 - 0);
440 
+    t14 = (t38 * 1);
441 
+    t14 = (t14 + 1);
442 
+    t37 = (t36 + 12U);
443 
+    *((unsigned int *)t37) = t14;
444 
+    t39 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t32, t29, t33, t35);
445 
+    t3 = t39;
416 446
417 447 
 LAB13:    if (t3 == 1)
418 448 
         goto LAB8;
419 449
420 
-LAB9:    t28 = (t0 + 2152U);
421 
-    t31 = *((char **)t28);
422 
-    t28 = (t0 + 17640U);
423 
-    t32 = (t0 + 18347);
424 
-    t35 = (t34 + 0U);
425 
-    t36 = (t35 + 0U);
426 
-    *((int *)t36) = 0;
427 
-    t36 = (t35 + 4U);
428 
-    *((int *)t36) = 7;
429 
-    t36 = (t35 + 8U);
430 
-    *((int *)t36) = 1;
431 
-    t37 = (7 - 0);
432 
-    t13 = (t37 * 1);
433 
-    t13 = (t13 + 1);
434 
-    t36 = (t35 + 12U);
435 
-    *((unsigned int *)t36) = t13;
436 
-    t38 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t31, t28, t32, t34);
437 
-    t2 = t38;
450 
+LAB9:    t37 = (t0 + 2152U);
451 
+    t40 = *((char **)t37);
452 
+    t37 = (t0 + 17640U);
453 
+    t41 = (t0 + 18355);
454 
+    t44 = (t43 + 0U);
455 
+    t45 = (t44 + 0U);
456 
+    *((int *)t45) = 0;
457 
+    t45 = (t44 + 4U);
458 
+    *((int *)t45) = 7;
459 
+    t45 = (t44 + 8U);
460 
+    *((int *)t45) = 1;
461 
+    t46 = (7 - 0);
462 
+    t14 = (t46 * 1);
463 
+    t14 = (t14 + 1);
464 
+    t45 = (t44 + 12U);
465 
+    *((unsigned int *)t45) = t14;
466 
+    t47 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t40, t37, t41, t43);
467 
+    t2 = t47;
438 468
439 469 
 LAB10:    if (t2 == 1)
440 470 
         goto LAB5;
441 471
442 
-LAB6:    t36 = (t0 + 2152U);
443 
-    t39 = *((char **)t36);
444 
-    t36 = (t0 + 17640U);
445 
-    t40 = (t0 + 18355);
446 
-    t43 = (t42 + 0U);
447 
-    t44 = (t43 + 0U);
448 
-    *((int *)t44) = 0;
449 
-    t44 = (t43 + 4U);
450 
-    *((int *)t44) = 7;
451 
-    t44 = (t43 + 8U);
452 
-    *((int *)t44) = 1;
453 
-    t45 = (7 - 0);
454 
-    t13 = (t45 * 1);
455 
-    t13 = (t13 + 1);
456 
-    t44 = (t43 + 12U);
457 
-    *((unsigned int *)t44) = t13;
458 
-    t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t39, t36, t40, t42);
459 
-    t1 = t46;
472 
+LAB6:    t45 = (t0 + 2152U);
473 
+    t48 = *((char **)t45);
474 
+    t45 = (t0 + 17640U);
475 
+    t49 = (t0 + 18363);
476 
+    t52 = (t51 + 0U);
477 
+    t53 = (t52 + 0U);
478 
+    *((int *)t53) = 0;
479 
+    t53 = (t52 + 4U);
480 
+    *((int *)t53) = 7;
481 
+    t53 = (t52 + 8U);
482 
+    *((int *)t53) = 1;
483 
+    t54 = (7 - 0);
484 
+    t14 = (t54 * 1);
485 
+    t14 = (t14 + 1);
486 
+    t53 = (t52 + 12U);
487 
+    *((unsigned int *)t53) = t14;
488 
+    t55 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t48, t45, t49, t51);
489 
+    t1 = t55;
460 490
461 491 
 LAB7:    if (t1 != 0)
462 492 
         goto LAB3;
463 493
464 494 
 LAB4:
465 
-LAB17:    t52 = (t0 + 2472U);
466 
-    t53 = *((char **)t52);
467 
-    t52 = (t0 + 10360);
468 
-    t54 = (t52 + 56U);
469 
-    t55 = *((char **)t54);
470 
-    t56 = (t55 + 56U);
471 
-    t57 = *((char **)t56);
472 
-    memcpy(t57, t53, 8U);
473 
-    xsi_driver_first_trans_fast(t52);
495 
+LAB20:    t61 = (t0 + 2472U);
496 
+    t62 = *((char **)t61);
497 
+    t61 = (t0 + 10360);
498 
+    t63 = (t61 + 56U);
499 
+    t64 = *((char **)t63);
500 
+    t65 = (t64 + 56U);
501 
+    t66 = *((char **)t65);
502 
+    memcpy(t66, t62, 8U);
503 
+    xsi_driver_first_trans_fast(t61);
474 504
475 
-LAB2:    t58 = (t0 + 10104);
476 
-    *((int *)t58) = 1;
505 
+LAB2:    t67 = (t0 + 10104);
506 
+    *((int *)t67) = 1;
477 507
478 508 
 LAB1:    return;
479 
-LAB3:    t44 = (t0 + 1512U);
480 
-    t47 = *((char **)t44);
481 
-    t44 = (t0 + 10360);
482 
-    t48 = (t44 + 56U);
483 
-    t49 = *((char **)t48);
484 
-    t50 = (t49 + 56U);
485 
-    t51 = *((char **)t50);
486 
-    memcpy(t51, t47, 8U);
487 
-    xsi_driver_first_trans_fast(t44);
509 
+LAB3:    t53 = (t0 + 1512U);
510 
+    t56 = *((char **)t53);
511 
+    t53 = (t0 + 10360);
512 
+    t57 = (t53 + 56U);
513 
+    t58 = *((char **)t57);
514 
+    t59 = (t58 + 56U);
515 
+    t60 = *((char **)t59);
516 
+    memcpy(t60, t56, 8U);
517 
+    xsi_driver_first_trans_fast(t53);
488 518 
     goto LAB2;
489 519
490 520 
 LAB5:    t1 = (unsigned char)1;
 
@@ -499,7 +529,10 @@ LAB11:    t3 = (unsigned char)1;
499 529 
 LAB14:    t4 = (unsigned char)1;
500 530 
     goto LAB16;
501 531
502 
-LAB18:    goto LAB2;
532 
+LAB17:    t5 = (unsigned char)1;
533 
+    goto LAB19;
534 
+
535 
+LAB21:    goto LAB2;
503 536
504 537 
 }
505 538 
 
@@ -557,7 +590,7 @@ LAB0:    xsi_set_current_line(197, ng0);
557 590 
     t1 = (t0 + 2792U);
558 591 
     t2 = *((char **)t1);
559 592 
     t1 = (t0 + 17704U);
560 
-    t3 = (t0 + 18363);
593 
+    t3 = (t0 + 18371);
561 594 
     t6 = (t5 + 0U);
562 595 
     t7 = (t6 + 0U);
563 596 
     *((int *)t7) = 0;
 
@@ -577,7 +610,7 @@ LAB0:    xsi_set_current_line(197, ng0);
577 610 
 LAB4:    t17 = (t0 + 2792U);
578 611 
     t18 = *((char **)t17);
579 612 
     t17 = (t0 + 17704U);
580 
-    t19 = (t0 + 18374);
613 
+    t19 = (t0 + 18382);
581 614 
     t22 = (t21 + 0U);
582 615 
     t23 = (t22 + 0U);
583 616 
     *((int *)t23) = 0;
 
@@ -597,7 +630,7 @@ LAB4:    t17 = (t0 + 2792U);
597 630 
 LAB6:    t32 = (t0 + 2792U);
598 631 
     t33 = *((char **)t32);
599 632 
     t32 = (t0 + 17704U);
600 
-    t34 = (t0 + 18385);
633 
+    t34 = (t0 + 18393);
601 634 
     t37 = (t36 + 0U);
602 635 
     t38 = (t37 + 0U);
603 636 
     *((int *)t38) = 0;
 
@@ -615,7 +648,7 @@ LAB6:    t32 = (t0 + 2792U);
615 648 
         goto LAB7;
616 649
617 650 
 LAB8:
618 
-LAB9:    t47 = (t0 + 18396);
651 
+LAB9:    t47 = (t0 + 18404);
619 652 
     t49 = (t0 + 10424);
620 653 
     t50 = (t49 + 56U);
621 654 
     t51 = *((char **)t50);
 
@@ -628,7 +661,7 @@ LAB2:    t54 = (t0 + 10120);
628 661 
     *((int *)t54) = 1;
629 662
630 663 
 LAB1:    return;
631 
-LAB3:    t7 = (t0 + 18371);
664 
+LAB3:    t7 = (t0 + 18379);
632 665 
     t12 = (t0 + 10424);
633 666 
     t13 = (t12 + 56U);
634 667 
     t14 = *((char **)t13);
 
@@ -638,7 +671,7 @@ LAB3:    t7 = (t0 + 18371);
638 671 
     xsi_driver_first_trans_fast(t12);
639 672 
     goto LAB2;
640 673
641 
-LAB5:    t23 = (t0 + 18382);
674 
+LAB5:    t23 = (t0 + 18390);
642 675 
     t27 = (t0 + 10424);
643 676 
     t28 = (t27 + 56U);
644 677 
     t29 = *((char **)t28);
 
@@ -648,7 +681,7 @@ LAB5:    t23 = (t0 + 18382);
648 681 
     xsi_driver_first_trans_fast(t27);
649 682 
     goto LAB2;
650 683
651 
-LAB7:    t38 = (t0 + 18393);
684 
+LAB7:    t38 = (t0 + 18401);
652 685 
     t42 = (t0 + 10424);
653 686 
     t43 = (t42 + 56U);
654 687 
     t44 = *((char **)t43);
 
@@ -706,7 +739,7 @@ LAB0:    xsi_set_current_line(214, ng0);
706 739 
     t3 = (t0 + 2792U);
707 740 
     t4 = *((char **)t3);
708 741 
     t3 = (t0 + 17704U);
709 
-    t5 = (t0 + 18399);
742 
+    t5 = (t0 + 18407);
710 743 
     t8 = (t7 + 0U);
711 744 
     t9 = (t8 + 0U);
712 745 
     *((int *)t9) = 0;
 
@@ -726,7 +759,7 @@ LAB0:    xsi_set_current_line(214, ng0);
726 759 
 LAB9:    t9 = (t0 + 2792U);
727 760 
     t13 = *((char **)t9);
728 761 
     t9 = (t0 + 17704U);
729 
-    t14 = (t0 + 18407);
762 
+    t14 = (t0 + 18415);
730 763 
     t17 = (t16 + 0U);
731 764 
     t18 = (t17 + 0U);
732 765 
     *((int *)t18) = 0;
 
@@ -748,7 +781,7 @@ LAB10:    if (t2 == 1)
748 781 
 LAB6:    t18 = (t0 + 2792U);
749 782 
     t21 = *((char **)t18);
750 783 
     t18 = (t0 + 17704U);
751 
-    t22 = (t0 + 18415);
784 
+    t22 = (t0 + 18423);
752 785 
     t25 = (t24 + 0U);
753 786 
     t26 = (t25 + 0U);
754 787 
     *((int *)t26) = 0;
 
@@ -829,7 +862,7 @@ LAB0:    xsi_set_current_line(231, ng0);
829 862 
     t1 = (t0 + 4392U);
830 863 
     t2 = *((char **)t1);
831 864 
     t1 = (t0 + 17800U);
832 
-    t3 = (t0 + 18423);
865 
+    t3 = (t0 + 18431);
833 866 
     t6 = (t5 + 0U);
834 867 
     t7 = (t6 + 0U);
835 868 
     *((int *)t7) = 0;
 
@@ -900,7 +933,7 @@ LAB0:    xsi_set_current_line(233, ng0);
900 933 
     t1 = (t0 + 4392U);
901 934 
     t2 = *((char **)t1);
902 935 
     t1 = (t0 + 17800U);
903 
-    t3 = (t0 + 18431);
936 
+    t3 = (t0 + 18439);
904 937 
     t6 = (t5 + 0U);
905 938 
     t7 = (t6 + 0U);
906 939 
     *((int *)t7) = 0;
 
@@ -969,7 +1002,7 @@ LAB0:    xsi_set_current_line(235, ng0);
969 1002 
     t1 = (t0 + 4392U);
970 1003 
     t2 = *((char **)t1);
971 1004 
     t1 = (t0 + 17800U);
972 
-    t3 = (t0 + 18439);
1005 
+    t3 = (t0 + 18447);
973 1006 
     t6 = (t5 + 0U);
974 1007 
     t7 = (t6 + 0U);
975 1008 
     *((int *)t7) = 0;
 
@@ -1006,76 +1039,109 @@ LAB3:    t7 = (t0 + 4232U);
1006 1039
1007 1040 
 static void work_a_4150868852_3212880686_p_7(char *t0)
1008 1041 
 {
1009 
-    char t5[16];
1010 
-    char *t1;
1042 
+    char t6[16];
1043 
+    char t15[16];
1044 
+    unsigned char t1;
1011 1045 
     char *t2;
1012 1046 
     char *t3;
1013 
-    char *t6;
1047 
+    char *t4;
1014 1048 
     char *t7;
1015 
-    int t8;
1016 
-    unsigned int t9;
1017 
-    unsigned char t10;
1018 
-    char *t11;
1049 
+    char *t8;
1050 
+    int t9;
1051 
+    unsigned int t10;
1052 
+    unsigned char t11;
1019 1053 
     char *t12;
1020 1054 
     char *t13;
1021 
-    char *t14;
1022 
-    char *t15;
1023 1055 
     char *t16;
1024 1056 
     char *t17;
1025 
-    char *t18;
1026 
-    char *t19;
1057 
+    int t18;
1058 
+    unsigned char t19;
1027 1059 
     char *t20;
1028 1060 
     char *t21;
1029 1061 
     char *t22;
1062 
+    char *t23;
1063 
+    char *t24;
1064 
+    char *t25;
1065 
+    char *t26;
1066 
+    char *t27;
1067 
+    char *t28;
1068 
+    char *t29;
1069 
+    char *t30;
1070 
+    char *t31;
1030 1071
1031 1072 
 LAB0:    xsi_set_current_line(236, ng0);
1032 
-    t1 = (t0 + 4392U);
1033 
-    t2 = *((char **)t1);
1034 
-    t1 = (t0 + 17800U);
1035 
-    t3 = (t0 + 18447);
1036 
-    t6 = (t5 + 0U);
1073 
+    t2 = (t0 + 4392U);
1074 
+    t3 = *((char **)t2);
1075 
+    t2 = (t0 + 17800U);
1076 
+    t4 = (t0 + 18455);
1037 1077 
     t7 = (t6 + 0U);
1038 
-    *((int *)t7) = 0;
1039 
-    t7 = (t6 + 4U);
1040 
-    *((int *)t7) = 7;
1041 
-    t7 = (t6 + 8U);
1042 
-    *((int *)t7) = 1;
1043 
-    t8 = (7 - 0);
1044 
-    t9 = (t8 * 1);
1045 
-    t9 = (t9 + 1);
1046 
-    t7 = (t6 + 12U);
1047 
-    *((unsigned int *)t7) = t9;
1048 
-    t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
1049 
-    if (t10 != 0)
1078 
+    t8 = (t7 + 0U);
1079 
+    *((int *)t8) = 0;
1080 
+    t8 = (t7 + 4U);
1081 
+    *((int *)t8) = 7;
1082 
+    t8 = (t7 + 8U);
1083 
+    *((int *)t8) = 1;
1084 
+    t9 = (7 - 0);
1085 
+    t10 = (t9 * 1);
1086 
+    t10 = (t10 + 1);
1087 
+    t8 = (t7 + 12U);
1088 
+    *((unsigned int *)t8) = t10;
1089 
+    t11 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t3, t2, t4, t6);
1090 
+    if (t11 == 1)
1091 
+        goto LAB5;
1092 
+
1093 
+LAB6:    t8 = (t0 + 4392U);
1094 
+    t12 = *((char **)t8);
1095 
+    t8 = (t0 + 17800U);
1096 
+    t13 = (t0 + 18463);
1097 
+    t16 = (t15 + 0U);
1098 
+    t17 = (t16 + 0U);
1099 
+    *((int *)t17) = 0;
1100 
+    t17 = (t16 + 4U);
1101 
+    *((int *)t17) = 7;
1102 
+    t17 = (t16 + 8U);
1103 
+    *((int *)t17) = 1;
1104 
+    t18 = (7 - 0);
1105 
+    t10 = (t18 * 1);
1106 
+    t10 = (t10 + 1);
1107 
+    t17 = (t16 + 12U);
1108 
+    *((unsigned int *)t17) = t10;
1109 
+    t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t12, t8, t13, t15);
1110 
+    t1 = t19;
1111 
+
1112 
+LAB7:    if (t1 != 0)
1050 1113 
         goto LAB3;
1051 1114
1052 1115 
 LAB4:
1053 
-LAB5:    t16 = (t0 + 4232U);
1054 
-    t17 = *((char **)t16);
1055 
-    t16 = (t0 + 10744);
1056 
-    t18 = (t16 + 56U);
1057 
-    t19 = *((char **)t18);
1058 
-    t20 = (t19 + 56U);
1059 
-    t21 = *((char **)t20);
1060 
-    memcpy(t21, t17, 8U);
1061 
-    xsi_driver_first_trans_fast(t16);
1062 
-
1063 
-LAB2:    t22 = (t0 + 10200);
1064 
-    *((int *)t22) = 1;
1116 
+LAB8:    t25 = (t0 + 4232U);
1117 
+    t26 = *((char **)t25);
1118 
+    t25 = (t0 + 10744);
1119 
+    t27 = (t25 + 56U);
1120 
+    t28 = *((char **)t27);
1121 
+    t29 = (t28 + 56U);
1122 
+    t30 = *((char **)t29);
1123 
+    memcpy(t30, t26, 8U);
1124 
+    xsi_driver_first_trans_fast(t25);
1125 
+
1126 
+LAB2:    t31 = (t0 + 10200);
1127 
+    *((int *)t31) = 1;
1065 1128
1066 1129 
 LAB1:    return;
1067 
-LAB3:    t7 = (t0 + 5672U);
1068 
-    t11 = *((char **)t7);
1069 
-    t7 = (t0 + 10744);
1070 
-    t12 = (t7 + 56U);
1071 
-    t13 = *((char **)t12);
1072 
-    t14 = (t13 + 56U);
1073 
-    t15 = *((char **)t14);
1074 
-    memcpy(t15, t11, 8U);
1075 
-    xsi_driver_first_trans_fast(t7);
1130 
+LAB3:    t17 = (t0 + 5672U);
1131 
+    t20 = *((char **)t17);
1132 
+    t17 = (t0 + 10744);
1133 
+    t21 = (t17 + 56U);
1134 
+    t22 = *((char **)t21);
1135 
+    t23 = (t22 + 56U);
1136 
+    t24 = *((char **)t23);
1137 
+    memcpy(t24, t20, 8U);
1138 
+    xsi_driver_first_trans_fast(t17);
1076 1139 
     goto LAB2;
1077 1140
1078 
-LAB6:    goto LAB2;
1141 
+LAB5:    t1 = (unsigned char)1;
1142 
+    goto LAB7;
1143 
+
1144 
+LAB9:    goto LAB2;
1079 1145
1080 1146 
 }
1081 1147 
 
@@ -1130,7 +1196,7 @@ LAB10:    xsi_set_current_line(266, ng0);
1130 1196 
     t2 = (t0 + 1352U);
1131 1197 
     t3 = *((char **)t2);
1132 1198 
     t2 = (t0 + 17560U);
1133 
-    t5 = (t0 + 18463);
1199 
+    t5 = (t0 + 18479);
1134 1200 
     t8 = (t13 + 0U);
1135 1201 
     t9 = (t8 + 0U);
1136 1202 
     *((int *)t9) = 0;
 
@@ -1171,7 +1237,7 @@ LAB5:    t3 = (t0 + 992U);
1171 1237 
 LAB7:    goto LAB5;
1172 1238
1173 1239 
 LAB8:    xsi_set_current_line(264, ng0);
1174 
-    t2 = (t0 + 18455);
1240 
+    t2 = (t0 + 18471);
1175 1241 
     t7 = (t0 + 10808);
1176 1242 
     t8 = (t7 + 56U);
1177 1243 
     t9 = *((char **)t8);

BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat View File


BIN
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o View File


BIN
xilinx/ALU/isim/work/alu.vdb View File


BIN
xilinx/ALU/isim/work/bm_data.vdb View File


BIN
xilinx/ALU/isim/work/bm_instr.vdb View File


BIN
xilinx/ALU/isim/work/br.vdb View File


BIN
xilinx/ALU/isim/work/pipeline.vdb View File


BIN
xilinx/ALU/isim/work/process_test.vdb View File


BIN
xilinx/ALU/isim/work/processeur.vdb View File


BIN
xilinx/ALU/process_test_isim_beh.wdb View File


+ 4
- 4
xilinx/ALU/processeur.vhd View File 

@@ -178,7 +178,7 @@ begin
178 178 
           QB => C_DIEX_IN
179 179 
         );
180 180
181 
-	B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ;
181 
+	B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" or OP_LIDI_OUT = x"08" else B_LIDI_OUT ;
182 182
183 183
184 184 
 	-- Instantiate pipeline DI_EX
 
@@ -233,12 +233,12 @@ begin
233 233 
 	addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
234 234 
 						A_EXMem_OUT;
235 235 
 	in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08";
236 
-	B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" else
236 
+	B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" or OP_EXMem_OUT = x"07" else
237 237 
 						B_EXMem_OUT;
238 238 
 	-- Instantiate banc de données
239 239 
    data_memory: bm_data PORT MAP (
240 240 
           IN_addr => addr_dm_MUX,
241 
-          IN_data => B_MemRE_IN,
241 
+          IN_data => in_dm_MUX,
242 242 
           RW => RW_LC,
243 243 
           RST => RST,
244 244 
           CLK => CLK,
 
@@ -249,7 +249,7 @@ begin
249 249 
 	Mem_RE : pipeline PORT MAP (
250 250 
 			OP_IN => OP_EXMem_OUT,
251 251 
            A_IN => A_EXMem_OUT,
252 
-           B_IN => B_EXMem_OUT,
252 
+           B_IN => B_MemRE_IN,
253 253 
            C_IN => x"00",
254 254 
 			  CLK => CLK,
255 255 
 			  A_OUT => A_MemRE_OUT,

+ 2
- 2
xilinx/ALU/processeur_summary.html View File 

@@ -72,9 +72,9 @@
72 72 
 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
73 73 
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
74 74 
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
75 
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lun. mai 10 10:45:43 2021</TD></TR>
75 
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>lun. mai 10 12:32:42 2021</TD></TR>
76 76 
 </TABLE>
77 77
78 78
79 
-<br><center><b>Date Generated:</b> 05/10/2021 - 10:47:06</center>
79 
+<br><center><b>Date Generated:</b> 05/11/2021 - 15:38:05</center>
80 80 
 </BODY></HTML>

+ 165
- 0
xilinx/ALU/tests/test_load.wcfg View File 

@@ -0,0 +1,165 @@
1 
+<?xml version="1.0" encoding="UTF-8"?>
2 
+<wave_config>
3 
+   <wave_state>
4 
+   </wave_state>
5 
+   <db_ref_list>
6 
+      <db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
7 
+         <top_modules>
8 
+            <top_module name="numeric_std" />
9 
+            <top_module name="process_test" />
10 
+            <top_module name="std_logic_1164" />
11 
+            <top_module name="std_logic_arith" />
12 
+            <top_module name="std_logic_unsigned" />
13 
+         </top_modules>
14 
+      </db_ref>
15 
+   </db_ref_list>
16 
+   <WVObjectSize size="37" />
17 
+   <wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
18 
+      <obj_property name="ElementShortName">clk</obj_property>
19 
+      <obj_property name="ObjectShortName">clk</obj_property>
20 
+   </wvobject>
21 
+   <wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
22 
+      <obj_property name="ElementShortName">rst</obj_property>
23 
+      <obj_property name="ObjectShortName">rst</obj_property>
24 
+   </wvobject>
25 
+   <wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
26 
+      <obj_property name="ElementShortName">clk_period</obj_property>
27 
+      <obj_property name="ObjectShortName">clk_period</obj_property>
28 
+   </wvobject>
29 
+   <wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
30 
+      <obj_property name="ElementShortName">out_data[31:0]</obj_property>
31 
+      <obj_property name="ObjectShortName">out_data[31:0]</obj_property>
32 
+   </wvobject>
33 
+   <wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
34 
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
35 
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
36 
+   </wvobject>
37 
+   <wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
38 
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
39 
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
40 
+   </wvobject>
41 
+   <wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
42 
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
43 
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
44 
+   </wvobject>
45 
+   <wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
46 
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
47 
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
48 
+   </wvobject>
49 
+   <wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
50 
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
51 
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
52 
+   </wvobject>
53 
+   <wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
54 
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
55 
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
56 
+   </wvobject>
57 
+   <wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
58 
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
59 
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
60 
+   </wvobject>
61 
+   <wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
62 
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
63 
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
64 
+   </wvobject>
65 
+   <wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
66 
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
67 
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
68 
+   </wvobject>
69 
+   <wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
70 
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
71 
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
72 
+   </wvobject>
73 
+   <wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
74 
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
75 
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
76 
+   </wvobject>
77 
+   <wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
78 
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
79 
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
80 
+   </wvobject>
81 
+   <wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
82 
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
83 
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
84 
+   </wvobject>
85 
+   <wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
86 
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
87 
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
88 
+   </wvobject>
89 
+   <wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
90 
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
91 
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
92 
+   </wvobject>
93 
+   <wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
94 
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
95 
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
96 
+   </wvobject>
97 
+   <wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
98 
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
99 
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
100 
+   </wvobject>
101 
+   <wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
102 
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
103 
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
104 
+   </wvobject>
105 
+   <wvobject fp_name="/process_test/uut/data_memory/in_addr" type="array" db_ref_id="1">
106 
+      <obj_property name="ElementShortName">in_addr[7:0]</obj_property>
107 
+      <obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
108 
+   </wvobject>
109 
+   <wvobject fp_name="/process_test/uut/data_memory/in_data" type="array" db_ref_id="1">
110 
+      <obj_property name="ElementShortName">in_data[7:0]</obj_property>
111 
+      <obj_property name="ObjectShortName">in_data[7:0]</obj_property>
112 
+   </wvobject>
113 
+   <wvobject fp_name="/process_test/uut/data_memory/rw" type="logic" db_ref_id="1">
114 
+      <obj_property name="ElementShortName">rw</obj_property>
115 
+      <obj_property name="ObjectShortName">rw</obj_property>
116 
+   </wvobject>
117 
+   <wvobject fp_name="/process_test/uut/data_memory/out_data" type="array" db_ref_id="1">
118 
+      <obj_property name="ElementShortName">out_data[7:0]</obj_property>
119 
+      <obj_property name="ObjectShortName">out_data[7:0]</obj_property>
120 
+   </wvobject>
121 
+   <wvobject fp_name="/process_test/uut/data_memory/data_memory" type="array" db_ref_id="1">
122 
+      <obj_property name="ElementShortName">data_memory[0:255]</obj_property>
123 
+      <obj_property name="ObjectShortName">data_memory[0:255]</obj_property>
124 
+   </wvobject>
125 
+   <wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
126 
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
127 
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
128 
+   </wvobject>
129 
+   <wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
130 
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
131 
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
132 
+   </wvobject>
133 
+   <wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
134 
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
135 
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
136 
+   </wvobject>
137 
+   <wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
138 
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
139 
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
140 
+   </wvobject>
141 
+   <wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
142 
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
143 
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
144 
+   </wvobject>
145 
+   <wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
146 
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
147 
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
148 
+   </wvobject>
149 
+   <wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
150 
+      <obj_property name="ElementShortName">registres[0:15]</obj_property>
151 
+      <obj_property name="ObjectShortName">registres[0:15]</obj_property>
152 
+   </wvobject>
153 
+   <wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
154 
+      <obj_property name="ElementShortName">w_addr[3:0]</obj_property>
155 
+      <obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
156 
+   </wvobject>
157 
+   <wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
158 
+      <obj_property name="ElementShortName">w</obj_property>
159 
+      <obj_property name="ObjectShortName">w</obj_property>
160 
+   </wvobject>
161 
+   <wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
162 
+      <obj_property name="ElementShortName">data[7:0]</obj_property>
163 
+      <obj_property name="ObjectShortName">data[7:0]</obj_property>
164 
+   </wvobject>
165 
+</wave_config>

+ 165
- 0
xilinx/ALU/tests/test_store.wcfg View File 

@@ -0,0 +1,165 @@
1 
+<?xml version="1.0" encoding="UTF-8"?>
2 
+<wave_config>
3 
+   <wave_state>
4 
+   </wave_state>
5 
+   <db_ref_list>
6 
+      <db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
7 
+         <top_modules>
8 
+            <top_module name="numeric_std" />
9 
+            <top_module name="process_test" />
10 
+            <top_module name="std_logic_1164" />
11 
+            <top_module name="std_logic_arith" />
12 
+            <top_module name="std_logic_unsigned" />
13 
+         </top_modules>
14 
+      </db_ref>
15 
+   </db_ref_list>
16 
+   <WVObjectSize size="37" />
17 
+   <wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
18 
+      <obj_property name="ElementShortName">clk</obj_property>
19 
+      <obj_property name="ObjectShortName">clk</obj_property>
20 
+   </wvobject>
21 
+   <wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
22 
+      <obj_property name="ElementShortName">rst</obj_property>
23 
+      <obj_property name="ObjectShortName">rst</obj_property>
24 
+   </wvobject>
25 
+   <wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
26 
+      <obj_property name="ElementShortName">clk_period</obj_property>
27 
+      <obj_property name="ObjectShortName">clk_period</obj_property>
28 
+   </wvobject>
29 
+   <wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
30 
+      <obj_property name="ElementShortName">out_data[31:0]</obj_property>
31 
+      <obj_property name="ObjectShortName">out_data[31:0]</obj_property>
32 
+   </wvobject>
33 
+   <wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
34 
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
35 
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
36 
+   </wvobject>
37 
+   <wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
38 
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
39 
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
40 
+   </wvobject>
41 
+   <wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
42 
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
43 
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
44 
+   </wvobject>
45 
+   <wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
46 
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
47 
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
48 
+   </wvobject>
49 
+   <wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
50 
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
51 
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
52 
+   </wvobject>
53 
+   <wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
54 
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
55 
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
56 
+   </wvobject>
57 
+   <wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
58 
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
59 
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
60 
+   </wvobject>
61 
+   <wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
62 
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
63 
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
64 
+   </wvobject>
65 
+   <wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
66 
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
67 
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
68 
+   </wvobject>
69 
+   <wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
70 
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
71 
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
72 
+   </wvobject>
73 
+   <wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
74 
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
75 
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
76 
+   </wvobject>
77 
+   <wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
78 
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
79 
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
80 
+   </wvobject>
81 
+   <wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
82 
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
83 
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
84 
+   </wvobject>
85 
+   <wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
86 
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
87 
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
88 
+   </wvobject>
89 
+   <wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
90 
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
91 
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
92 
+   </wvobject>
93 
+   <wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
94 
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
95 
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
96 
+   </wvobject>
97 
+   <wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
98 
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
99 
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
100 
+   </wvobject>
101 
+   <wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
102 
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
103 
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
104 
+   </wvobject>
105 
+   <wvobject fp_name="/process_test/uut/data_memory/in_addr" type="array" db_ref_id="1">
106 
+      <obj_property name="ElementShortName">in_addr[7:0]</obj_property>
107 
+      <obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
108 
+   </wvobject>
109 
+   <wvobject fp_name="/process_test/uut/data_memory/in_data" type="array" db_ref_id="1">
110 
+      <obj_property name="ElementShortName">in_data[7:0]</obj_property>
111 
+      <obj_property name="ObjectShortName">in_data[7:0]</obj_property>
112 
+   </wvobject>
113 
+   <wvobject fp_name="/process_test/uut/data_memory/rw" type="logic" db_ref_id="1">
114 
+      <obj_property name="ElementShortName">rw</obj_property>
115 
+      <obj_property name="ObjectShortName">rw</obj_property>
116 
+   </wvobject>
117 
+   <wvobject fp_name="/process_test/uut/data_memory/out_data" type="array" db_ref_id="1">
118 
+      <obj_property name="ElementShortName">out_data[7:0]</obj_property>
119 
+      <obj_property name="ObjectShortName">out_data[7:0]</obj_property>
120 
+   </wvobject>
121 
+   <wvobject fp_name="/process_test/uut/data_memory/data_memory" type="array" db_ref_id="1">
122 
+      <obj_property name="ElementShortName">data_memory[0:255]</obj_property>
123 
+      <obj_property name="ObjectShortName">data_memory[0:255]</obj_property>
124 
+   </wvobject>
125 
+   <wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
126 
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
127 
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
128 
+   </wvobject>
129 
+   <wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
130 
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
131 
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
132 
+   </wvobject>
133 
+   <wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
134 
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
135 
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
136 
+   </wvobject>
137 
+   <wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
138 
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
139 
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
140 
+   </wvobject>
141 
+   <wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
142 
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
143 
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
144 
+   </wvobject>
145 
+   <wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
146 
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
147 
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
148 
+   </wvobject>
149 
+   <wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
150 
+      <obj_property name="ElementShortName">registres[0:15]</obj_property>
151 
+      <obj_property name="ObjectShortName">registres[0:15]</obj_property>
152 
+   </wvobject>
153 
+   <wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
154 
+      <obj_property name="ElementShortName">w_addr[3:0]</obj_property>
155 
+      <obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
156 
+   </wvobject>
157 
+   <wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
158 
+      <obj_property name="ElementShortName">w</obj_property>
159 
+      <obj_property name="ObjectShortName">w</obj_property>
160 
+   </wvobject>
161 
+   <wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
162 
+      <obj_property name="ElementShortName">data[7:0]</obj_property>
163 
+      <obj_property name="ObjectShortName">data[7:0]</obj_property>
164 
+   </wvobject>
165 
+</wave_config>

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