Browse Source

Ready for demo

Foussats Morgane 2 months ago
parent
commit
63b6b29d6c
48 changed files with 1012 additions and 508 deletions
  1. 1
    1
      compiler/Makefile
  2. 10
    10
      compiler/analyse_syntaxique.y
  3. 10
    1
      compiler/code_c
  4. BIN
      compiler/compiler
  5. 21
    1
      compiler/memory_oriented_assembly.txt
  6. BIN
      interpreter/interpreter
  7. 21
    1
      interpreter/interpreter_input.txt
  8. 1
    1
      interpreter/src/instructions.c
  9. 4
    4
      xilinx/ALU/ALU.gise
  10. 13
    5
      xilinx/ALU/bm_instr.vhd
  11. 6
    6
      xilinx/ALU/fuse.log
  12. 7
    7
      xilinx/ALU/iseconfig/ALU.projectmgr
  13. 1
    1
      xilinx/ALU/iseconfig/processeur.xreport
  14. 42
    0
      xilinx/ALU/isim.log
  15. 5
    5
      xilinx/ALU/isim/isim_usage_statistics.html
  16. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat
  17. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat
  18. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat
  19. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat
  20. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
  21. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg
  22. 13
    13
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log
  23. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat
  24. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId1.dat
  25. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe
  26. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1
  27. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat
  28. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat
  29. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat
  30. 1
    1
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c
  31. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat
  32. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o
  33. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat
  34. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat
  35. 591
    443
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c
  36. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat
  37. BIN
      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o
  38. BIN
      xilinx/ALU/isim/work/alu.vdb
  39. BIN
      xilinx/ALU/isim/work/bm_data.vdb
  40. BIN
      xilinx/ALU/isim/work/bm_instr.vdb
  41. BIN
      xilinx/ALU/isim/work/br.vdb
  42. BIN
      xilinx/ALU/isim/work/pipeline.vdb
  43. BIN
      xilinx/ALU/isim/work/process_test.vdb
  44. BIN
      xilinx/ALU/isim/work/processeur.vdb
  45. BIN
      xilinx/ALU/process_test_isim_beh.wdb
  46. 8
    4
      xilinx/ALU/processeur.vhd
  47. 4
    4
      xilinx/ALU/processeur_summary.html
  48. 253
    0
      xilinx/ALU/tests/demo.wcfg

+ 1
- 1
compiler/Makefile View File

@@ -6,7 +6,7 @@ compiler: analyse_lexicale.lex analyse_syntaxique.y table_symboles.c table_fonct
6 6
 		gcc -w *.c -ly -o compiler
7 7
 
8 8
 run: compiler
9
-		./compiler < code_c
9
+		./compiler < code_c 
10 10
 
11 11
 clean:
12 12
 		rm -f lex.yy.c compiler analyse_syntaxique.output analyse_syntaxique.tab.c analyse_syntaxique.tab.h

+ 10
- 10
compiler/analyse_syntaxique.y View File

@@ -175,26 +175,26 @@ While : tWHILE tPO {
175 175
 	$1 = array.index;
176 176
 }
177 177
 tAO {table.depth++;} Instructions tAF {remove_symboles(&table); table.depth--;} {
178
+	generate_instruction_1(&array, JMP, $2);
178 179
 	int adr_jmp = array.index;
179 180
 	update_jmf(&array, $1, adr_jmp);
180
-	generate_instruction_1(&array, JMP, $2);
181 181
 };
182 182
 
183
-Cond : E tEGAL E {generate_instruction_3(&array, EQ, $1, $1, $3); free_temp(&table); $$ = $3;};
184
-Cond : E tDIFF E {generate_instruction_3(&array, NEQ, $1, $1, $3); free_temp(&table); $$ = $3;} ;
185
-Cond : E tLT E {generate_instruction_3(&array, LT, $1, $1, $3); free_temp(&table); $$ = $3;} ;
186
-Cond : E tGT E {generate_instruction_3(&array, GT, $1, $1, $3); free_temp(&table); $$ = $3;} ;
187
-Cond : E tLTE E {generate_instruction_3(&array, LTE, $1, $1, $3); free_temp(&table); $$ = $3;} ;
188
-Cond : E tGTE E {generate_instruction_3(&array, GTE, $1, $1, $3); free_temp(&table); $$ = $3;} ;
189
-Cond : E tAND E {generate_instruction_3(&array, AND, $1, $1, $3); free_temp(&table); $$ = $3;} ;
190
-Cond : E tOR E {generate_instruction_3(&array, OR, $1, $1, $3); free_temp(&table); $$ = $3;} ;
183
+Cond : E tEGAL E {generate_instruction_3(&array, EQ, $1, $1, $3); free_temp(&table); $$ = $1;};
184
+Cond : E tDIFF E {generate_instruction_3(&array, NEQ, $1, $1, $3); free_temp(&table); $$ = $1;} ;
185
+Cond : E tLT E {generate_instruction_3(&array, LT, $1, $1, $3); free_temp(&table); $$ = $1;} ;
186
+Cond : E tGT E {generate_instruction_3(&array, GT, $1, $1, $3); free_temp(&table); $$ = $1;} ;
187
+Cond : E tLTE E {generate_instruction_3(&array, LTE, $1, $1, $3); free_temp(&table); $$ = $1;} ;
188
+Cond : E tGTE E {generate_instruction_3(&array, GTE, $1, $1, $3); free_temp(&table); $$ = $1;} ;
189
+Cond : E tAND E {generate_instruction_3(&array, AND, $1, $1, $3); free_temp(&table); $$ = $1;} ;
190
+Cond : E tOR E {generate_instruction_3(&array, OR, $1, $1, $3); free_temp(&table); $$ = $1;} ;
191 191
 Cond : tNOT Cond {generate_instruction_2(&array, NOT, $2, $2); $$ = $2;} ;
192 192
 Cond : E {$$ = $1; };
193 193
 
194 194
 Invocation : tVAR tPO {table.depth++; prepare_function_call(&table); return_value = (table.indexAvailableBottom);} Args  tPF
195 195
 	{int function_index = function_exists(&table_fonctions, $1);
196 196
 	int jmp_addr = (table_fonctions.array[function_index]).start_addr;
197
-	generate_instruction_2(&array, CALL, jmp_addr, table.indexAvailableTop);
197
+	generate_instruction_2(&array, CALL, jmp_addr, table.indexAvailableTop-1);
198 198
 	$$ = return_value;
199 199
 	};
200 200
 

+ 10
- 1
compiler/code_c View File

@@ -9,8 +9,17 @@ int main(){
9 9
     int a = 7;
10 10
     int * pointeur = &a;
11 11
     int c = fonction1(pointeur);
12
+    if(c==2){ 
13
+        printf(c);
14
+        printf(*pointeur);
15
+    }
16
+    else{
17
+        c=a+2;
18
+    }
19
+    while (c!=5){
20
+        c = c+1;    
21
+    }
12 22
     printf(c);
13
-    printf(*pointeur);
14 23
     return 0;
15 24
 } 
16 25
 

BIN
compiler/compiler View File


+ 21
- 1
compiler/memory_oriented_assembly.txt View File

@@ -14,12 +14,32 @@ LEA 255 0
14 14
 COP 1 255
15 15
 COP 255 1
16 16
 COP 5 255
17
-CALL 1 6
17
+CALL 1 5
18 18
 COP 2 255
19 19
 COP 255 2
20
+AFC 254 2
21
+EQ 255 255 254
22
+JPF 255 28
23
+COP 255 2
20 24
 PRI 255
21 25
 COP 255 1
22 26
 COP_LD 255 [255]
23 27
 PRI 255
28
+JMP 32
29
+COP 255 0
30
+AFC 254 2
31
+ADD 255 255 254
32
+COP 2 255
33
+COP 255 2
34
+AFC 254 5
35
+NEQ 255 255 254
36
+JPF 255 41
37
+COP 255 2
38
+AFC 254 1
39
+ADD 255 255 254
40
+COP 2 255
41
+JMP 32
42
+COP 255 2
43
+PRI 255
24 44
 AFC 255 0
25 45
 RET 255

BIN
interpreter/interpreter View File


+ 21
- 1
interpreter/interpreter_input.txt View File

@@ -14,12 +14,32 @@ LEA 255 0
14 14
 COP 1 255
15 15
 COP 255 1
16 16
 COP 5 255
17
-CALL 1 6
17
+CALL 1 5
18 18
 COP 2 255
19 19
 COP 255 2
20
+AFC 254 2
21
+EQ 255 255 254
22
+JPF 255 28
23
+COP 255 2
20 24
 PRI 255
21 25
 COP 255 1
22 26
 COP_LD 255 [255]
23 27
 PRI 255
28
+JMP 32
29
+COP 255 0
30
+AFC 254 2
31
+ADD 255 255 254
32
+COP 2 255
33
+COP 255 2
34
+AFC 254 5
35
+NEQ 255 255 254
36
+JPF 255 41
37
+COP 255 2
38
+AFC 254 1
39
+ADD 255 255 254
40
+COP 2 255
41
+JMP 32
42
+COP 255 2
43
+PRI 255
24 44
 AFC 255 0
25 45
 RET 255

+ 1
- 1
interpreter/src/instructions.c View File

@@ -122,7 +122,7 @@ int exec(int ip) {
122 122
         next_ip = arg1; break;
123 123
     case JPF:
124 124
         printf("JPF cond@%d[%d] to %d\n", arg1, memory[arg1], arg2);
125
-        if (memory[arg1] != 0) {
125
+        if (memory[arg1] != 1) {
126 126
             next_ip = arg2;
127 127
         }
128 128
         break;

+ 4
- 4
xilinx/ALU/ALU.gise View File

@@ -73,7 +73,7 @@
73 73
       <status xil_pn:value="SuccessfullyRun"/>
74 74
       <status xil_pn:value="ReadyToRun"/>
75 75
     </transform>
76
-    <transform xil_pn:end_ts="1621346572" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1621346572">
76
+    <transform xil_pn:end_ts="1621933612" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1621933612">
77 77
       <status xil_pn:value="SuccessfullyRun"/>
78 78
       <status xil_pn:value="ReadyToRun"/>
79 79
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -104,7 +104,7 @@
104 104
       <status xil_pn:value="SuccessfullyRun"/>
105 105
       <status xil_pn:value="ReadyToRun"/>
106 106
     </transform>
107
-    <transform xil_pn:end_ts="1621346572" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1621346572">
107
+    <transform xil_pn:end_ts="1621933612" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1621933612">
108 108
       <status xil_pn:value="SuccessfullyRun"/>
109 109
       <status xil_pn:value="ReadyToRun"/>
110 110
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -124,7 +124,7 @@
124 124
       <outfile xil_pn:name="process_test.vhd"/>
125 125
       <outfile xil_pn:name="processeur.vhd"/>
126 126
     </transform>
127
-    <transform xil_pn:end_ts="1621346573" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1621346572">
127
+    <transform xil_pn:end_ts="1621933615" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1621933612">
128 128
       <status xil_pn:value="SuccessfullyRun"/>
129 129
       <status xil_pn:value="ReadyToRun"/>
130 130
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -139,7 +139,7 @@
139 139
       <outfile xil_pn:name="process_test_isim_beh.exe"/>
140 140
       <outfile xil_pn:name="xilinxsim.ini"/>
141 141
     </transform>
142
-    <transform xil_pn:end_ts="1621346668" xil_pn:in_ck="5586040975174613622" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1621346668">
142
+    <transform xil_pn:end_ts="1621933615" xil_pn:in_ck="5586040975174613622" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1621933615">
143 143
       <status xil_pn:value="SuccessfullyRun"/>
144 144
       <status xil_pn:value="ReadyToRun"/>
145 145
       <status xil_pn:value="OutOfDateForPredecessor"/>

+ 13
- 5
xilinx/ALU/bm_instr.vhd View File

@@ -34,35 +34,43 @@ architecture Behavioral of bm_instr is
34 34
 type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
35 35
 -- instruction "00000110 00000001 00000110 00000000"
36 36
 --test afc
37
-signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
37
+--signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
38 38
 
39 39
 --test afc cop
40 40
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
41
+
41 42
 --test afc cop alea
42 43
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
44
+
43 45
 --test add
44 46
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
47
+
45 48
 --test add alea
46 49
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 3 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
47
---test sub
48 50
 
51
+--test sub
49 52
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000011000000110000000100000010", others =>"00000000000000000000000000000000");
50 53
 
51 54
 --test mul
52
-
53 55
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000010000000110000000100000010", others =>"00000000000000000000000000000000");
54 56
 
55 57
 --test store
56
-
57 58
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 10 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
58 59
 
59 60
 --test store alea
60 61
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
61 62
 
62 63
 --test load
63
-
64 64
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", 15 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000");
65 65
 
66
+-- test demo
67
+--   AFC	0	6	0
68
+--   COP	1	0	0
69
+--   ADD 2	0	1
70
+-- STORE 0	2	0
71
+-- LOAD  3	0	0
72
+signal instr_memory: mem := (1 => "00000110000000000000011000000000", 2 =>"00000101000000010000000000000000", 3 => "00000001000000100000000000000001",
73
+			4 => "00001000000000000000001000000000", 5 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000");
66 74
 
67 75
 begin
68 76
 

+ 6
- 6
xilinx/ALU/fuse.log View File

@@ -1,7 +1,7 @@
1 1
 Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test" 
2 2
 ISim O.87xd (signature 0x8ddf5b5d)
3
-Number of CPUs detected in this system: 12
4
-Turning on mult-threading, number of parallel sub-compilation jobs: 24 
3
+Number of CPUs detected in this system: 8
4
+Turning on mult-threading, number of parallel sub-compilation jobs: 16 
5 5
 Determining compilation order of HDL files
6 6
 Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work
7 7
 Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work
@@ -13,7 +13,7 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU
13 13
 Starting static elaboration
14 14
 Completed static elaboration
15 15
 Fuse Memory Usage: 98520 KB
16
-Fuse CPU Usage: 840 ms
16
+Fuse CPU Usage: 870 ms
17 17
 Compiling package standard
18 18
 Compiling package std_logic_1164
19 19
 Compiling package std_logic_arith
@@ -30,6 +30,6 @@ Time Resolution for simulation is 1ps.
30 30
 Waiting for 1 sub-compilation(s) to finish...
31 31
 Compiled 18 VHDL Units
32 32
 Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe
33
-Fuse Memory Usage: 1723384 KB
34
-Fuse CPU Usage: 980 ms
35
-GCC CPU Usage: 110 ms
33
+Fuse Memory Usage: 1198968 KB
34
+Fuse CPU Usage: 1010 ms
35
+GCC CPU Usage: 250 ms

+ 7
- 7
xilinx/ALU/iseconfig/ALU.projectmgr View File

@@ -9,13 +9,13 @@
9 9
          <ClosedNodesVersion>2</ClosedNodesVersion>
10 10
       </ClosedNodes>
11 11
       <SelectedItems>
12
-         <SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
12
+         <SelectedItem>data_memory - bm_data - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd)</SelectedItem>
13 13
       </SelectedItems>
14 14
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
15 15
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
16
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
16
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001c5000000020000000000000000000000000200000064ffffffff000000810000000300000002000001c50000000100000003000000000000000100000003</ViewHeaderState>
17 17
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
18
-      <CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
18
+      <CurrentItem>data_memory - bm_data - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd)</CurrentItem>
19 19
    </ItemView>
20 20
    <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
21 21
       <ClosedNodes>
@@ -50,7 +50,7 @@
50 50
       <SelectedItems/>
51 51
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
52 52
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
53
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000148000000010001000100000000000000000000000064ffffffff000000810000000000000001000001480000000100000000</ViewHeaderState>
53
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000132000000010001000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000</ViewHeaderState>
54 54
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
55 55
       <CurrentItem>work</CurrentItem>
56 56
    </ItemView>
@@ -85,7 +85,7 @@
85 85
       </SelectedItems>
86 86
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
87 87
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
88
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001f8000000020000000000000000000000000200000064ffffffff000000810000000300000002000001f80000000100000003000000000000000100000003</ViewHeaderState>
88
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001d9000000020000000000000000000000000200000064ffffffff000000810000000300000002000001d90000000100000003000000000000000100000003</ViewHeaderState>
89 89
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
90 90
       <CurrentItem>process_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd)</CurrentItem>
91 91
    </ItemView>
@@ -94,13 +94,13 @@
94 94
          <ClosedNodesVersion>1</ClosedNodesVersion>
95 95
       </ClosedNodes>
96 96
       <SelectedItems>
97
-         <SelectedItem></SelectedItem>
97
+         <SelectedItem/>
98 98
       </SelectedItems>
99 99
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
100 100
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
101 101
       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
102 102
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
103
-      <CurrentItem></CurrentItem>
103
+      <CurrentItem/>
104 104
    </ItemView>
105 105
    <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
106 106
       <ClosedNodes>

+ 1
- 1
xilinx/ALU/iseconfig/processeur.xreport View File

@@ -1,7 +1,7 @@
1 1
 <?xml version='1.0' encoding='UTF-8'?>
2 2
 <report-views version="2.0" >
3 3
  <header>
4
-  <DateModified>2021-05-18T16:14:30</DateModified>
4
+  <DateModified>2021-05-25T10:06:35</DateModified>
5 5
   <ModuleName>processeur</ModuleName>
6 6
   <SummaryTimeStamp>Unknown</SummaryTimeStamp>
7 7
   <SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath>

+ 42
- 0
xilinx/ALU/isim.log View File

@@ -115,4 +115,46 @@ at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_IN
115 115
 at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
116 116
 at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
117 117
 at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
118
+ISim O.87xd (signature 0x8ddf5b5d)
119
+WARNING: A WEBPACK license was found.
120
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
121
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
122
+This is a Lite version of ISim.
123
+# run 1000 ns
124
+Simulator is doing circuit initialization process.
125
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
126
+Finished circuit initialization process.
127
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
128
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
129
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
130
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
131
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
132
+ISim O.87xd (signature 0x8ddf5b5d)
133
+WARNING: A WEBPACK license was found.
134
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
135
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
136
+This is a Lite version of ISim.
137
+# run 1000 ns
138
+Simulator is doing circuit initialization process.
139
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
140
+Finished circuit initialization process.
141
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
142
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
143
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
144
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
145
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
146
+ISim O.87xd (signature 0x8ddf5b5d)
147
+WARNING: A WEBPACK license was found.
148
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
149
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
150
+This is a Lite version of ISim.
151
+# run 1000 ns
152
+Simulator is doing circuit initialization process.
153
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
154
+Finished circuit initialization process.
155
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
156
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
157
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
158
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
159
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
118 160
 # exit 0

+ 5
- 5
xilinx/ALU/isim/isim_usage_statistics.html View File

@@ -2,14 +2,14 @@
2 2
 <xtag-section name="ISimStatistics">
3 3
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
4 4
 <TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
5
-<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>980 ms, 1723384 KB</xtag-isim-property-value></TD></TR>
5
+<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1010 ms, 1198968 KB</xtag-isim-property-value></TD></TR>
6 6
 
7
-<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>121</xtag-isim-property-value></TD></TR>
8
-<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10703</xtag-isim-property-value></TD></TR>
7
+<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>122</xtag-isim-property-value></TD></TR>
8
+<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10704</xtag-isim-property-value></TD></TR>
9 9
 <TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>14</xtag-isim-property-value></TD></TR>
10
-<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>36</xtag-isim-property-value></TD></TR>
10
+<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>37</xtag-isim-property-value></TD></TR>
11 11
 <TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
12
-<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 264171 KB</xtag-isim-property-value></TD></TR>
12
+<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.08 sec, 264175 KB</xtag-isim-property-value></TD></TR>
13 13
 <TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
14 14
 <TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
15 15
 </xtag-section>

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+ 13
- 13
xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log View File

@@ -2,28 +2,28 @@ Command line:
2 2
    process_test_isim_beh.exe
3 3
      -simmode  gui
4 4
      -simrunnum  0
5
-     -socket  37953
5
+     -socket  42185
6 6
 
7
-Tue May 18 16:16:44 2021
7
+Tue May 25 12:30:38 2021
8 8
 
9 9
 
10
- Elaboration Time: 0.01 sec
10
+ Elaboration Time: 0.03 sec
11 11
 
12
- Current Memory Usage: 189.723 Meg
12
+ Current Memory Usage: 189.727 Meg
13 13
 
14
- Total Signals          : 121
15
- Total Nets             : 10703
16
- Total Signal Drivers   : 49
14
+ Total Signals          : 122
15
+ Total Nets             : 10704
16
+ Total Signal Drivers   : 50
17 17
  Total Blocks           : 14
18 18
  Total Primitive Blocks : 12
19
- Total Processes        : 36
19
+ Total Processes        : 37
20 20
  Total Traceable Variables  : 16
21
- Total Scalar Nets and Variables : 11205
22
-Total Line Count : 92
21
+ Total Scalar Nets and Variables : 11206
22
+Total Line Count : 93
23 23
 
24
- Total Simulation Time: 0.03 sec
24
+ Total Simulation Time: 0.08 sec
25 25
 
26
- Current Memory Usage: 265.224 Meg
26
+ Current Memory Usage: 265.228 Meg
27 27
 
28
-Tue May 18 16:20:51 2021
28
+Tue May 25 12:52:51 2021
29 29
 

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+ 1
- 1
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c View File

@@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0)
45 45
     char *t14;
46 46
     char *t15;
47 47
 
48
-LAB0:    xsi_set_current_line(67, ng0);
48
+LAB0:    xsi_set_current_line(72, ng0);
49 49
 
50 50
 LAB3:    t1 = (t0 + 1512U);
51 51
     t2 = *((char **)t1);

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+ 591
- 443
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+ 8
- 4
xilinx/ALU/processeur.vhd View File

@@ -148,6 +148,7 @@
148 148
 		signal li_di_r_c : std_logic;
149 149
 		signal di_ex_w_a : std_logic;
150 150
 		signal ex_mem_w_a : std_logic;
151
+		signal store_load : std_logic;
151 152
 		signal alea : std_logic;
152 153
 		
153 154
     begin
@@ -180,6 +181,8 @@
180 181
 						else '0';
181 182
 		li_di_r_c <= '1' when OUT_data(31 downto 24) = x"01" or OUT_data(31 downto 24) = x"02" or OUT_data(31 downto 24) = x"03" or OUT_data(31 downto 24) = x"04"
182 183
 						else '0';
184
+		store_load <= '1' when OUT_data(31 downto 24) = x"07" and OP_LIDI_OUT = x"08"
185
+						else '0';
183 186
     	-- Instanciate banc de registre
184 187
        banc_registres : br PORT MAP (
185 188
               A_addr => B_LIDI_OUT(3 downto 0),
@@ -194,7 +197,7 @@
194 197
             );
195 198
     			
196 199
     	B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" or OP_LIDI_OUT = x"08" else B_LIDI_OUT ;
197
-    			
200
+    	--B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ;		
198 201
     			
199 202
     	-- Instantiate pipeline DI_EX
200 203
     	DI_EX : pipeline PORT MAP (
@@ -252,7 +255,7 @@
252 255
     	addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
253 256
     						A_EXMem_OUT;
254 257
     	in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08"; 
255
-    	B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" or OP_EXMem_OUT = x"07" else
258
+    	B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"07" else
256 259
     						B_EXMem_OUT;
257 260
 							
258 261
 		-- alea ex_mem
@@ -261,7 +264,7 @@
261 264
     	-- Instantiate banc de données
262 265
        data_memory: bm_data PORT MAP (
263 266
               IN_addr => addr_dm_MUX,
264
-              IN_data => in_dm_MUX,
267
+              IN_data => B_EXMem_OUT,
265 268
               RW => RW_LC,
266 269
               RST => RST,
267 270
               CLK => CLK,
@@ -285,7 +288,8 @@
285 288
 		alea <= '0' when (li_di_r_b = '1' and di_ex_w_a = '1' and OUT_data(15 downto 8) = A_LIDI_OUT) or
286 289
 						  (li_di_r_c = '1' and di_ex_w_a = '1' and OUT_data(7 downto 0) = A_LIDI_OUT) or
287 290
 						  (li_di_r_b = '1' and ex_mem_w_a = '1' and OUT_data(15 downto 8) = A_DIEX_OUT) or
288
-						  (li_di_r_c = '1' and ex_mem_w_a = '1' and OUT_data(7 downto 0) = A_DIEX_OUT) else
291
+						  (li_di_r_c = '1' and ex_mem_w_a = '1' and OUT_data(7 downto 0) = A_DIEX_OUT) or
292
+						   (store_load = '1' and  OUT_data(15 downto 8) = A_LIDI_OUT) else
289 293
 						  '1';
290 294
 	
291 295
     	process

+ 4
- 4
xilinx/ALU/processeur_summary.html View File

@@ -2,7 +2,7 @@
2 2
 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3 3
 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
4 4
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
5
-<TD ALIGN=CENTER COLSPAN='4'><B>processeur Project Status (05/18/2021 - 16:15:09)</B></TD></TR>
5
+<TD ALIGN=CENTER COLSPAN='4'><B>processeur Project Status</B></TD></TR>
6 6
 <TR ALIGN=LEFT>
7 7
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
8 8
 <TD>ALU.xise</TD>
@@ -13,7 +13,7 @@
13 13
 <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
14 14
 <TD>processeur</TD>
15 15
 <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
16
-<TD>Mapped (Failed)</TD>
16
+<TD>Mapped</TD>
17 17
 </TR>
18 18
 <TR ALIGN=LEFT>
19 19
 <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
@@ -79,9 +79,9 @@ System Settings</A>
79 79
 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
80 80
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
81 81
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
82
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>mar. mai 18 16:15:36 2021</TD></TR>
82
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>mar. mai 18 16:20:52 2021</TD></TR>
83 83
 </TABLE>
84 84
 
85 85
 
86
-<br><center><b>Date Generated:</b> 05/18/2021 - 16:16:17</center>
86
+<br><center><b>Date Generated:</b> 05/25/2021 - 10:06:35</center>
87 87
 </BODY></HTML>

+ 253
- 0
xilinx/ALU/tests/demo.wcfg View File

@@ -0,0 +1,253 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<wave_config>
3
+   <wave_state>
4
+   </wave_state>
5
+   <db_ref_list>
6
+      <db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
7
+         <top_modules>
8
+            <top_module name="numeric_std" />
9
+            <top_module name="process_test" />
10
+            <top_module name="std_logic_1164" />
11
+            <top_module name="std_logic_arith" />
12
+            <top_module name="std_logic_unsigned" />
13
+         </top_modules>
14
+      </db_ref>
15
+   </db_ref_list>
16
+   <WVObjectSize size="59" />
17
+   <wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
18
+      <obj_property name="ElementShortName">clk</obj_property>
19
+      <obj_property name="ObjectShortName">clk</obj_property>
20
+   </wvobject>
21
+   <wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
22
+      <obj_property name="ElementShortName">rst</obj_property>
23
+      <obj_property name="ObjectShortName">rst</obj_property>
24
+   </wvobject>
25
+   <wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
26
+      <obj_property name="ElementShortName">clk_period</obj_property>
27
+      <obj_property name="ObjectShortName">clk_period</obj_property>
28
+   </wvobject>
29
+   <wvobject fp_name="/process_test/uut/addr_instructions/in_addr" type="array" db_ref_id="1">
30
+      <obj_property name="ElementShortName">in_addr[7:0]</obj_property>
31
+      <obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
32
+   </wvobject>
33
+   <wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
34
+      <obj_property name="ElementShortName">out_data[31:0]</obj_property>
35
+      <obj_property name="ObjectShortName">out_data[31:0]</obj_property>
36
+   </wvobject>
37
+   <wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
38
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
39
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
40
+   </wvobject>
41
+   <wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
42
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
43
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
44
+   </wvobject>
45
+   <wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
46
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
47
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
48
+   </wvobject>
49
+   <wvobject fp_name="/process_test/uut/LI_LD/c_in" type="array" db_ref_id="1">
50
+      <obj_property name="ElementShortName">c_in[7:0]</obj_property>
51
+      <obj_property name="ObjectShortName">c_in[7:0]</obj_property>
52
+   </wvobject>
53
+   <wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
54
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
55
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
56
+   </wvobject>
57
+   <wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
58
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
59
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
60
+   </wvobject>
61
+   <wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
62
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
63
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
64
+   </wvobject>
65
+   <wvobject fp_name="/process_test/uut/LI_LD/c_out" type="array" db_ref_id="1">
66
+      <obj_property name="ElementShortName">c_out[7:0]</obj_property>
67
+      <obj_property name="ObjectShortName">c_out[7:0]</obj_property>
68
+   </wvobject>
69
+   <wvobject fp_name="/process_test/uut/banc_registres/qa" type="array" db_ref_id="1">
70
+      <obj_property name="ElementShortName">qa[7:0]</obj_property>
71
+      <obj_property name="ObjectShortName">qa[7:0]</obj_property>
72
+   </wvobject>
73
+   <wvobject fp_name="/process_test/uut/banc_registres/qb" type="array" db_ref_id="1">
74
+      <obj_property name="ElementShortName">qb[7:0]</obj_property>
75
+      <obj_property name="ObjectShortName">qb[7:0]</obj_property>
76
+   </wvobject>
77
+   <wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
78
+      <obj_property name="ElementShortName">registres[0:15]</obj_property>
79
+      <obj_property name="ObjectShortName">registres[0:15]</obj_property>
80
+   </wvobject>
81
+   <wvobject fp_name="/process_test/uut/banc_registres/a_addr" type="array" db_ref_id="1">
82
+      <obj_property name="ElementShortName">a_addr[3:0]</obj_property>
83
+      <obj_property name="ObjectShortName">a_addr[3:0]</obj_property>
84
+   </wvobject>
85
+   <wvobject fp_name="/process_test/uut/banc_registres/b_addr" type="array" db_ref_id="1">
86
+      <obj_property name="ElementShortName">b_addr[3:0]</obj_property>
87
+      <obj_property name="ObjectShortName">b_addr[3:0]</obj_property>
88
+   </wvobject>
89
+   <wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
90
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
91
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
92
+   </wvobject>
93
+   <wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
94
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
95
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
96
+   </wvobject>
97
+   <wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
98
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
99
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
100
+   </wvobject>
101
+   <wvobject fp_name="/process_test/uut/DI_EX/c_in" type="array" db_ref_id="1">
102
+      <obj_property name="ElementShortName">c_in[7:0]</obj_property>
103
+      <obj_property name="ObjectShortName">c_in[7:0]</obj_property>
104
+   </wvobject>
105
+   <wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
106
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
107
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
108
+   </wvobject>
109
+   <wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
110
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
111
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
112
+   </wvobject>
113
+   <wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
114
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
115
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
116
+   </wvobject>
117
+   <wvobject fp_name="/process_test/uut/DI_EX/c_out" type="array" db_ref_id="1">
118
+      <obj_property name="ElementShortName">c_out[7:0]</obj_property>
119
+      <obj_property name="ObjectShortName">c_out[7:0]</obj_property>
120
+   </wvobject>
121
+   <wvobject fp_name="/process_test/uut/UAL/a" type="array" db_ref_id="1">
122
+      <obj_property name="ElementShortName">a[7:0]</obj_property>
123
+      <obj_property name="ObjectShortName">a[7:0]</obj_property>
124
+   </wvobject>
125
+   <wvobject fp_name="/process_test/uut/UAL/b" type="array" db_ref_id="1">
126
+      <obj_property name="ElementShortName">b[7:0]</obj_property>
127
+      <obj_property name="ObjectShortName">b[7:0]</obj_property>
128
+   </wvobject>
129
+   <wvobject fp_name="/process_test/uut/UAL/ctrl_alu" type="array" db_ref_id="1">
130
+      <obj_property name="ElementShortName">ctrl_alu[2:0]</obj_property>
131
+      <obj_property name="ObjectShortName">ctrl_alu[2:0]</obj_property>
132
+   </wvobject>
133
+   <wvobject fp_name="/process_test/uut/UAL/s" type="array" db_ref_id="1">
134
+      <obj_property name="ElementShortName">s[7:0]</obj_property>
135
+      <obj_property name="ObjectShortName">s[7:0]</obj_property>
136
+   </wvobject>
137
+   <wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
138
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
139
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
140
+   </wvobject>
141
+   <wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
142
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
143
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
144
+   </wvobject>
145
+   <wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
146
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
147
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
148
+   </wvobject>
149
+   <wvobject fp_name="/process_test/uut/EX_Mem/c_in" type="array" db_ref_id="1">
150
+      <obj_property name="ElementShortName">c_in[7:0]</obj_property>
151
+      <obj_property name="ObjectShortName">c_in[7:0]</obj_property>
152
+   </wvobject>
153
+   <wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
154
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
155
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
156
+   </wvobject>
157
+   <wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
158
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
159
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
160
+   </wvobject>
161
+   <wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
162
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
163
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
164
+   </wvobject>
165
+   <wvobject fp_name="/process_test/uut/EX_Mem/c_out" type="array" db_ref_id="1">
166
+      <obj_property name="ElementShortName">c_out[7:0]</obj_property>
167
+      <obj_property name="ObjectShortName">c_out[7:0]</obj_property>
168
+   </wvobject>
169
+   <wvobject fp_name="/process_test/uut/data_memory/in_addr" type="array" db_ref_id="1">
170
+      <obj_property name="ElementShortName">in_addr[7:0]</obj_property>
171
+      <obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
172
+   </wvobject>
173
+   <wvobject fp_name="/process_test/uut/data_memory/in_data" type="array" db_ref_id="1">
174
+      <obj_property name="ElementShortName">in_data[7:0]</obj_property>
175
+      <obj_property name="ObjectShortName">in_data[7:0]</obj_property>
176
+   </wvobject>
177
+   <wvobject fp_name="/process_test/uut/data_memory/rw" type="logic" db_ref_id="1">
178
+      <obj_property name="ElementShortName">rw</obj_property>
179
+      <obj_property name="ObjectShortName">rw</obj_property>
180
+   </wvobject>
181
+   <wvobject fp_name="/process_test/uut/data_memory/out_data" type="array" db_ref_id="1">
182
+      <obj_property name="ElementShortName">out_data[7:0]</obj_property>
183
+      <obj_property name="ObjectShortName">out_data[7:0]</obj_property>
184
+   </wvobject>
185
+   <wvobject fp_name="/process_test/uut/data_memory/data_memory" type="array" db_ref_id="1">
186
+      <obj_property name="ElementShortName">data_memory[0:255]</obj_property>
187
+      <obj_property name="ObjectShortName">data_memory[0:255]</obj_property>
188
+   </wvobject>
189
+   <wvobject fp_name="/process_test/uut/out_dm_mux" type="array" db_ref_id="1">
190
+      <obj_property name="ElementShortName">out_dm_mux[7:0]</obj_property>
191
+      <obj_property name="ObjectShortName">out_dm_mux[7:0]</obj_property>
192
+   </wvobject>
193
+   <wvobject fp_name="/process_test/uut/op_exmem_out" type="array" db_ref_id="1">
194
+      <obj_property name="ElementShortName">op_exmem_out[7:0]</obj_property>
195
+      <obj_property name="ObjectShortName">op_exmem_out[7:0]</obj_property>
196
+   </wvobject>
197
+   <wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
198
+      <obj_property name="ElementShortName">op_in[7:0]</obj_property>
199
+      <obj_property name="ObjectShortName">op_in[7:0]</obj_property>
200
+   </wvobject>
201
+   <wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
202
+      <obj_property name="ElementShortName">a_in[7:0]</obj_property>
203
+      <obj_property name="ObjectShortName">a_in[7:0]</obj_property>
204
+   </wvobject>
205
+   <wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
206
+      <obj_property name="ElementShortName">b_in[7:0]</obj_property>
207
+      <obj_property name="ObjectShortName">b_in[7:0]</obj_property>
208
+   </wvobject>
209
+   <wvobject fp_name="/process_test/uut/Mem_RE/c_in" type="array" db_ref_id="1">
210
+      <obj_property name="ElementShortName">c_in[7:0]</obj_property>
211
+      <obj_property name="ObjectShortName">c_in[7:0]</obj_property>
212
+   </wvobject>
213
+   <wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
214
+      <obj_property name="ElementShortName">op_out[7:0]</obj_property>
215
+      <obj_property name="ObjectShortName">op_out[7:0]</obj_property>
216
+   </wvobject>
217
+   <wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
218
+      <obj_property name="ElementShortName">a_out[7:0]</obj_property>
219
+      <obj_property name="ObjectShortName">a_out[7:0]</obj_property>
220
+   </wvobject>
221
+   <wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
222
+      <obj_property name="ElementShortName">b_out[7:0]</obj_property>
223
+      <obj_property name="ObjectShortName">b_out[7:0]</obj_property>
224
+   </wvobject>
225
+   <wvobject fp_name="/process_test/uut/Mem_RE/c_out" type="array" db_ref_id="1">
226
+      <obj_property name="ElementShortName">c_out[7:0]</obj_property>
227
+      <obj_property name="ObjectShortName">c_out[7:0]</obj_property>
228
+   </wvobject>
229
+   <wvobject fp_name="/process_test/uut/banc_registres/a_addr" type="array" db_ref_id="1">
230
+      <obj_property name="ElementShortName">a_addr[3:0]</obj_property>
231
+      <obj_property name="ObjectShortName">a_addr[3:0]</obj_property>
232
+   </wvobject>
233
+   <wvobject fp_name="/process_test/uut/banc_registres/b_addr" type="array" db_ref_id="1">
234
+      <obj_property name="ElementShortName">b_addr[3:0]</obj_property>
235
+      <obj_property name="ObjectShortName">b_addr[3:0]</obj_property>
236
+   </wvobject>
237
+   <wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
238
+      <obj_property name="ElementShortName">w_addr[3:0]</obj_property>
239
+      <obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
240
+   </wvobject>
241
+   <wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
242
+      <obj_property name="ElementShortName">w</obj_property>
243
+      <obj_property name="ObjectShortName">w</obj_property>
244
+   </wvobject>
245
+   <wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
246
+      <obj_property name="ElementShortName">data[7:0]</obj_property>
247
+      <obj_property name="ObjectShortName">data[7:0]</obj_property>
248
+   </wvobject>
249
+   <wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
250
+      <obj_property name="ElementShortName">registres[0:15]</obj_property>
251
+      <obj_property name="ObjectShortName">registres[0:15]</obj_property>
252
+   </wvobject>
253
+</wave_config>

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