Ready for demo
Este commit está contenido en:
Foussats Morgane
padre
7d8e760392
commit
63b6b29d6c
Se han modificado 48 ficheros con 1088 adiciones y 584 borrados
|
|
@ -6,7 +6,7 @@ compiler: analyse_lexicale.lex analyse_syntaxique.y table_symboles.c table_fonct
|
|||
gcc -w *.c -ly -o compiler
|
||||
|
||||
run: compiler
|
||||
./compiler < code_c
|
||||
./compiler < code_c
|
||||
|
||||
clean:
|
||||
rm -f lex.yy.c compiler analyse_syntaxique.output analyse_syntaxique.tab.c analyse_syntaxique.tab.h
|
||||
|
|
@ -175,26 +175,26 @@ While : tWHILE tPO {
|
|||
$1 = array.index;
|
||||
}
|
||||
tAO {table.depth++;} Instructions tAF {remove_symboles(&table); table.depth--;} {
|
||||
generate_instruction_1(&array, JMP, $2);
|
||||
int adr_jmp = array.index;
|
||||
update_jmf(&array, $1, adr_jmp);
|
||||
generate_instruction_1(&array, JMP, $2);
|
||||
};
|
||||
|
||||
Cond : E tEGAL E {generate_instruction_3(&array, EQ, $1, $1, $3); free_temp(&table); $$ = $3;};
|
||||
Cond : E tDIFF E {generate_instruction_3(&array, NEQ, $1, $1, $3); free_temp(&table); $$ = $3;} ;
|
||||
Cond : E tLT E {generate_instruction_3(&array, LT, $1, $1, $3); free_temp(&table); $$ = $3;} ;
|
||||
Cond : E tGT E {generate_instruction_3(&array, GT, $1, $1, $3); free_temp(&table); $$ = $3;} ;
|
||||
Cond : E tLTE E {generate_instruction_3(&array, LTE, $1, $1, $3); free_temp(&table); $$ = $3;} ;
|
||||
Cond : E tGTE E {generate_instruction_3(&array, GTE, $1, $1, $3); free_temp(&table); $$ = $3;} ;
|
||||
Cond : E tAND E {generate_instruction_3(&array, AND, $1, $1, $3); free_temp(&table); $$ = $3;} ;
|
||||
Cond : E tOR E {generate_instruction_3(&array, OR, $1, $1, $3); free_temp(&table); $$ = $3;} ;
|
||||
Cond : E tEGAL E {generate_instruction_3(&array, EQ, $1, $1, $3); free_temp(&table); $$ = $1;};
|
||||
Cond : E tDIFF E {generate_instruction_3(&array, NEQ, $1, $1, $3); free_temp(&table); $$ = $1;} ;
|
||||
Cond : E tLT E {generate_instruction_3(&array, LT, $1, $1, $3); free_temp(&table); $$ = $1;} ;
|
||||
Cond : E tGT E {generate_instruction_3(&array, GT, $1, $1, $3); free_temp(&table); $$ = $1;} ;
|
||||
Cond : E tLTE E {generate_instruction_3(&array, LTE, $1, $1, $3); free_temp(&table); $$ = $1;} ;
|
||||
Cond : E tGTE E {generate_instruction_3(&array, GTE, $1, $1, $3); free_temp(&table); $$ = $1;} ;
|
||||
Cond : E tAND E {generate_instruction_3(&array, AND, $1, $1, $3); free_temp(&table); $$ = $1;} ;
|
||||
Cond : E tOR E {generate_instruction_3(&array, OR, $1, $1, $3); free_temp(&table); $$ = $1;} ;
|
||||
Cond : tNOT Cond {generate_instruction_2(&array, NOT, $2, $2); $$ = $2;} ;
|
||||
Cond : E {$$ = $1; };
|
||||
|
||||
Invocation : tVAR tPO {table.depth++; prepare_function_call(&table); return_value = (table.indexAvailableBottom);} Args tPF
|
||||
{int function_index = function_exists(&table_fonctions, $1);
|
||||
int jmp_addr = (table_fonctions.array[function_index]).start_addr;
|
||||
generate_instruction_2(&array, CALL, jmp_addr, table.indexAvailableTop);
|
||||
generate_instruction_2(&array, CALL, jmp_addr, table.indexAvailableTop-1);
|
||||
$$ = return_value;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -9,8 +9,17 @@ int main(){
|
|||
int a = 7;
|
||||
int * pointeur = &a;
|
||||
int c = fonction1(pointeur);
|
||||
if(c==2){
|
||||
printf(c);
|
||||
printf(*pointeur);
|
||||
}
|
||||
else{
|
||||
c=a+2;
|
||||
}
|
||||
while (c!=5){
|
||||
c = c+1;
|
||||
}
|
||||
printf(c);
|
||||
printf(*pointeur);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Archivo binario no mostrado.
|
|
@ -14,12 +14,32 @@ LEA 255 0
|
|||
COP 1 255
|
||||
COP 255 1
|
||||
COP 5 255
|
||||
CALL 1 6
|
||||
CALL 1 5
|
||||
COP 2 255
|
||||
COP 255 2
|
||||
AFC 254 2
|
||||
EQ 255 255 254
|
||||
JPF 255 28
|
||||
COP 255 2
|
||||
PRI 255
|
||||
COP 255 1
|
||||
COP_LD 255 [255]
|
||||
PRI 255
|
||||
JMP 32
|
||||
COP 255 0
|
||||
AFC 254 2
|
||||
ADD 255 255 254
|
||||
COP 2 255
|
||||
COP 255 2
|
||||
AFC 254 5
|
||||
NEQ 255 255 254
|
||||
JPF 255 41
|
||||
COP 255 2
|
||||
AFC 254 1
|
||||
ADD 255 255 254
|
||||
COP 2 255
|
||||
JMP 32
|
||||
COP 255 2
|
||||
PRI 255
|
||||
AFC 255 0
|
||||
RET 255
|
||||
|
|
|
|||
Archivo binario no mostrado.
|
|
@ -14,12 +14,32 @@ LEA 255 0
|
|||
COP 1 255
|
||||
COP 255 1
|
||||
COP 5 255
|
||||
CALL 1 6
|
||||
CALL 1 5
|
||||
COP 2 255
|
||||
COP 255 2
|
||||
AFC 254 2
|
||||
EQ 255 255 254
|
||||
JPF 255 28
|
||||
COP 255 2
|
||||
PRI 255
|
||||
COP 255 1
|
||||
COP_LD 255 [255]
|
||||
PRI 255
|
||||
JMP 32
|
||||
COP 255 0
|
||||
AFC 254 2
|
||||
ADD 255 255 254
|
||||
COP 2 255
|
||||
COP 255 2
|
||||
AFC 254 5
|
||||
NEQ 255 255 254
|
||||
JPF 255 41
|
||||
COP 255 2
|
||||
AFC 254 1
|
||||
ADD 255 255 254
|
||||
COP 2 255
|
||||
JMP 32
|
||||
COP 255 2
|
||||
PRI 255
|
||||
AFC 255 0
|
||||
RET 255
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ int exec(int ip) {
|
|||
next_ip = arg1; break;
|
||||
case JPF:
|
||||
printf("JPF cond@%d[%d] to %d\n", arg1, memory[arg1], arg2);
|
||||
if (memory[arg1] != 0) {
|
||||
if (memory[arg1] != 1) {
|
||||
next_ip = arg2;
|
||||
}
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1621346572" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1621346572">
|
||||
<transform xil_pn:end_ts="1621933612" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1621933612">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
|
|
@ -104,7 +104,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1621346572" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1621346572">
|
||||
<transform xil_pn:end_ts="1621933612" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1621933612">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
|
|
@ -124,7 +124,7 @@
|
|||
<outfile xil_pn:name="process_test.vhd"/>
|
||||
<outfile xil_pn:name="processeur.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1621346573" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1621346572">
|
||||
<transform xil_pn:end_ts="1621933615" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1621933612">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
|
|
@ -139,7 +139,7 @@
|
|||
<outfile xil_pn:name="process_test_isim_beh.exe"/>
|
||||
<outfile xil_pn:name="xilinxsim.ini"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1621346668" xil_pn:in_ck="5586040975174613622" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1621346668">
|
||||
<transform xil_pn:end_ts="1621933615" xil_pn:in_ck="5586040975174613622" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1621933615">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
|
|
|
|||
|
|
@ -34,35 +34,43 @@ architecture Behavioral of bm_instr is
|
|||
type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
|
||||
-- instruction "00000110 00000001 00000110 00000000"
|
||||
--test afc
|
||||
signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
|
||||
--signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
|
||||
|
||||
--test afc cop
|
||||
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
|
||||
|
||||
--test afc cop alea
|
||||
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
|
||||
|
||||
--test add
|
||||
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
|
||||
|
||||
--test add alea
|
||||
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 3 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
|
||||
--test sub
|
||||
|
||||
--test sub
|
||||
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000011000000110000000100000010", others =>"00000000000000000000000000000000");
|
||||
|
||||
--test mul
|
||||
|
||||
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000010000000110000000100000010", others =>"00000000000000000000000000000000");
|
||||
|
||||
--test store
|
||||
|
||||
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 10 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
|
||||
|
||||
--test store alea
|
||||
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
|
||||
|
||||
--test load
|
||||
|
||||
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", 15 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000");
|
||||
|
||||
-- test demo
|
||||
-- AFC 0 6 0
|
||||
-- COP 1 0 0
|
||||
-- ADD 2 0 1
|
||||
-- STORE 0 2 0
|
||||
-- LOAD 3 0 0
|
||||
signal instr_memory: mem := (1 => "00000110000000000000011000000000", 2 =>"00000101000000010000000000000000", 3 => "00000001000000100000000000000001",
|
||||
4 => "00001000000000000000001000000000", 5 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000");
|
||||
|
||||
begin
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test"
|
||||
ISim O.87xd (signature 0x8ddf5b5d)
|
||||
Number of CPUs detected in this system: 12
|
||||
Turning on mult-threading, number of parallel sub-compilation jobs: 24
|
||||
Number of CPUs detected in this system: 8
|
||||
Turning on mult-threading, number of parallel sub-compilation jobs: 16
|
||||
Determining compilation order of HDL files
|
||||
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work
|
||||
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work
|
||||
|
|
@ -13,7 +13,7 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU
|
|||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
Fuse Memory Usage: 98520 KB
|
||||
Fuse CPU Usage: 840 ms
|
||||
Fuse CPU Usage: 870 ms
|
||||
Compiling package standard
|
||||
Compiling package std_logic_1164
|
||||
Compiling package std_logic_arith
|
||||
|
|
@ -30,6 +30,6 @@ Time Resolution for simulation is 1ps.
|
|||
Waiting for 1 sub-compilation(s) to finish...
|
||||
Compiled 18 VHDL Units
|
||||
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe
|
||||
Fuse Memory Usage: 1723384 KB
|
||||
Fuse CPU Usage: 980 ms
|
||||
GCC CPU Usage: 110 ms
|
||||
Fuse Memory Usage: 1198968 KB
|
||||
Fuse CPU Usage: 1010 ms
|
||||
GCC CPU Usage: 250 ms
|
||||
|
|
|
|||
|
|
@ -9,13 +9,13 @@
|
|||
<ClosedNodesVersion>2</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
|
||||
<SelectedItem>data_memory - bm_data - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd)</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001c5000000020000000000000000000000000200000064ffffffff000000810000000300000002000001c50000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
|
||||
<CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
|
||||
<CurrentItem>data_memory - bm_data - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd)</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
|
|
@ -50,7 +50,7 @@
|
|||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000148000000010001000100000000000000000000000064ffffffff000000810000000000000001000001480000000100000000</ViewHeaderState>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000132000000010001000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>work</CurrentItem>
|
||||
</ItemView>
|
||||
|
|
@ -85,7 +85,7 @@
|
|||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001f8000000020000000000000000000000000200000064ffffffff000000810000000300000002000001f80000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001d9000000020000000000000000000000000200000064ffffffff000000810000000300000002000001d90000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
|
||||
<CurrentItem>process_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd)</CurrentItem>
|
||||
</ItemView>
|
||||
|
|
@ -94,13 +94,13 @@
|
|||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
<SelectedItem/>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
<CurrentItem/>
|
||||
</ItemView>
|
||||
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2021-05-18T16:14:30</DateModified>
|
||||
<DateModified>2021-05-25T10:06:35</DateModified>
|
||||
<ModuleName>processeur</ModuleName>
|
||||
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
|
||||
<SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath>
|
||||
|
|
|
|||
|
|
@ -115,4 +115,46 @@ at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_IN
|
|||
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
ISim O.87xd (signature 0x8ddf5b5d)
|
||||
WARNING: A WEBPACK license was found.
|
||||
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
||||
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
||||
This is a Lite version of ISim.
|
||||
# run 1000 ns
|
||||
Simulator is doing circuit initialization process.
|
||||
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
||||
Finished circuit initialization process.
|
||||
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
ISim O.87xd (signature 0x8ddf5b5d)
|
||||
WARNING: A WEBPACK license was found.
|
||||
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
||||
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
||||
This is a Lite version of ISim.
|
||||
# run 1000 ns
|
||||
Simulator is doing circuit initialization process.
|
||||
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
||||
Finished circuit initialization process.
|
||||
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
ISim O.87xd (signature 0x8ddf5b5d)
|
||||
WARNING: A WEBPACK license was found.
|
||||
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
||||
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
||||
This is a Lite version of ISim.
|
||||
# run 1000 ns
|
||||
Simulator is doing circuit initialization process.
|
||||
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
||||
Finished circuit initialization process.
|
||||
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
|
||||
# exit 0
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
<xtag-section name="ISimStatistics">
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>980 ms, 1723384 KB</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1010 ms, 1198968 KB</xtag-isim-property-value></TD></TR>
|
||||
|
||||
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>121</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10703</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>122</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10704</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>14</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>36</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>37</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 264171 KB</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.08 sec, 264175 KB</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
|
||||
</xtag-section>
|
||||
|
|
|
|||
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
|
|
@ -2,28 +2,28 @@ Command line:
|
|||
process_test_isim_beh.exe
|
||||
-simmode gui
|
||||
-simrunnum 0
|
||||
-socket 37953
|
||||
-socket 42185
|
||||
|
||||
Tue May 18 16:16:44 2021
|
||||
Tue May 25 12:30:38 2021
|
||||
|
||||
|
||||
Elaboration Time: 0.01 sec
|
||||
Elaboration Time: 0.03 sec
|
||||
|
||||
Current Memory Usage: 189.723 Meg
|
||||
Current Memory Usage: 189.727 Meg
|
||||
|
||||
Total Signals : 121
|
||||
Total Nets : 10703
|
||||
Total Signal Drivers : 49
|
||||
Total Signals : 122
|
||||
Total Nets : 10704
|
||||
Total Signal Drivers : 50
|
||||
Total Blocks : 14
|
||||
Total Primitive Blocks : 12
|
||||
Total Processes : 36
|
||||
Total Processes : 37
|
||||
Total Traceable Variables : 16
|
||||
Total Scalar Nets and Variables : 11205
|
||||
Total Line Count : 92
|
||||
Total Scalar Nets and Variables : 11206
|
||||
Total Line Count : 93
|
||||
|
||||
Total Simulation Time: 0.03 sec
|
||||
Total Simulation Time: 0.08 sec
|
||||
|
||||
Current Memory Usage: 265.224 Meg
|
||||
Current Memory Usage: 265.228 Meg
|
||||
|
||||
Tue May 18 16:20:51 2021
|
||||
Tue May 25 12:52:51 2021
|
||||
|
||||
|
|
|
|||
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
|
|
@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0)
|
|||
char *t14;
|
||||
char *t15;
|
||||
|
||||
LAB0: xsi_set_current_line(67, ng0);
|
||||
LAB0: xsi_set_current_line(72, ng0);
|
||||
|
||||
LAB3: t1 = (t0 + 1512U);
|
||||
t2 = *((char **)t1);
|
||||
|
|
|
|||
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
Archivo binario no mostrado.
|
|
@ -148,6 +148,7 @@
|
|||
signal li_di_r_c : std_logic;
|
||||
signal di_ex_w_a : std_logic;
|
||||
signal ex_mem_w_a : std_logic;
|
||||
signal store_load : std_logic;
|
||||
signal alea : std_logic;
|
||||
|
||||
begin
|
||||
|
|
@ -180,6 +181,8 @@
|
|||
else '0';
|
||||
li_di_r_c <= '1' when OUT_data(31 downto 24) = x"01" or OUT_data(31 downto 24) = x"02" or OUT_data(31 downto 24) = x"03" or OUT_data(31 downto 24) = x"04"
|
||||
else '0';
|
||||
store_load <= '1' when OUT_data(31 downto 24) = x"07" and OP_LIDI_OUT = x"08"
|
||||
else '0';
|
||||
-- Instanciate banc de registre
|
||||
banc_registres : br PORT MAP (
|
||||
A_addr => B_LIDI_OUT(3 downto 0),
|
||||
|
|
@ -194,7 +197,7 @@
|
|||
);
|
||||
|
||||
B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" or OP_LIDI_OUT = x"08" else B_LIDI_OUT ;
|
||||
|
||||
--B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ;
|
||||
|
||||
-- Instantiate pipeline DI_EX
|
||||
DI_EX : pipeline PORT MAP (
|
||||
|
|
@ -252,7 +255,7 @@
|
|||
addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
|
||||
A_EXMem_OUT;
|
||||
in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08";
|
||||
B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" or OP_EXMem_OUT = x"07" else
|
||||
B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"07" else
|
||||
B_EXMem_OUT;
|
||||
|
||||
-- alea ex_mem
|
||||
|
|
@ -261,7 +264,7 @@
|
|||
-- Instantiate banc de données
|
||||
data_memory: bm_data PORT MAP (
|
||||
IN_addr => addr_dm_MUX,
|
||||
IN_data => in_dm_MUX,
|
||||
IN_data => B_EXMem_OUT,
|
||||
RW => RW_LC,
|
||||
RST => RST,
|
||||
CLK => CLK,
|
||||
|
|
@ -285,7 +288,8 @@
|
|||
alea <= '0' when (li_di_r_b = '1' and di_ex_w_a = '1' and OUT_data(15 downto 8) = A_LIDI_OUT) or
|
||||
(li_di_r_c = '1' and di_ex_w_a = '1' and OUT_data(7 downto 0) = A_LIDI_OUT) or
|
||||
(li_di_r_b = '1' and ex_mem_w_a = '1' and OUT_data(15 downto 8) = A_DIEX_OUT) or
|
||||
(li_di_r_c = '1' and ex_mem_w_a = '1' and OUT_data(7 downto 0) = A_DIEX_OUT) else
|
||||
(li_di_r_c = '1' and ex_mem_w_a = '1' and OUT_data(7 downto 0) = A_DIEX_OUT) or
|
||||
(store_load = '1' and OUT_data(15 downto 8) = A_LIDI_OUT) else
|
||||
'1';
|
||||
|
||||
process
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>processeur Project Status (05/18/2021 - 16:15:09)</B></TD></TR>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>processeur Project Status</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>ALU.xise</TD>
|
||||
|
|
@ -13,7 +13,7 @@
|
|||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>processeur</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>Mapped (Failed)</TD>
|
||||
<TD>Mapped</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
|
|
@ -79,9 +79,9 @@ System Settings</A>
|
|||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>mar. mai 18 16:15:36 2021</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>mar. mai 18 16:20:52 2021</TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 05/18/2021 - 16:16:17</center>
|
||||
<br><center><b>Date Generated:</b> 05/25/2021 - 10:06:35</center>
|
||||
</BODY></HTML>
|
||||
253
xilinx/ALU/tests/demo.wcfg
Archivo normal
253
xilinx/ALU/tests/demo.wcfg
Archivo normal
|
|
@ -0,0 +1,253 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
|
||||
<top_modules>
|
||||
<top_module name="numeric_std" />
|
||||
<top_module name="process_test" />
|
||||
<top_module name="std_logic_1164" />
|
||||
<top_module name="std_logic_arith" />
|
||||
<top_module name="std_logic_unsigned" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<WVObjectSize size="59" />
|
||||
<wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">rst</obj_property>
|
||||
<obj_property name="ObjectShortName">rst</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">clk_period</obj_property>
|
||||
<obj_property name="ObjectShortName">clk_period</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/addr_instructions/in_addr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">in_addr[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">out_data[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">out_data[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/LI_LD/c_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">c_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">c_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/LI_LD/c_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">c_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">c_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/qa" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">qa[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">qa[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/qb" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">qb[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">qb[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">registres[0:15]</obj_property>
|
||||
<obj_property name="ObjectShortName">registres[0:15]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/a_addr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a_addr[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a_addr[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/b_addr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b_addr[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b_addr[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/DI_EX/c_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">c_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">c_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/DI_EX/c_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">c_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">c_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/UAL/a" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/UAL/b" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/UAL/ctrl_alu" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">ctrl_alu[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">ctrl_alu[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/UAL/s" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">s[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">s[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/EX_Mem/c_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">c_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">c_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/EX_Mem/c_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">c_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">c_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/data_memory/in_addr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">in_addr[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/data_memory/in_data" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">in_data[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">in_data[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/data_memory/rw" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">rw</obj_property>
|
||||
<obj_property name="ObjectShortName">rw</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/data_memory/out_data" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">out_data[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">out_data[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/data_memory/data_memory" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">data_memory[0:255]</obj_property>
|
||||
<obj_property name="ObjectShortName">data_memory[0:255]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/out_dm_mux" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">out_dm_mux[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">out_dm_mux[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/op_exmem_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">op_exmem_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">op_exmem_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/Mem_RE/c_in" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">c_in[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">c_in[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/Mem_RE/c_out" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">c_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">c_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/a_addr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">a_addr[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">a_addr[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/b_addr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">b_addr[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">b_addr[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">w_addr[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">w</obj_property>
|
||||
<obj_property name="ObjectShortName">w</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">data[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">data[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">registres[0:15]</obj_property>
|
||||
<obj_property name="ObjectShortName">registres[0:15]</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
Cargando…
Referenciar en una nueva incidencia