21 lines
621 B
VHDL
21 lines
621 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity instruction_memory is
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Port ( addr : in STD_LOGIC_VECTOR (7 downto 0);
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q : out STD_LOGIC_VECTOR (31 downto 0);
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clk : in STD_LOGIC);
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end instruction_memory;
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architecture Behavioral of instruction_memory is
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type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(31 downto 0);
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signal memory: MEMORY_TYPE := (0 => "00000110000000010000001000000000", others => (others => '0'));
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begin
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process
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begin
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wait until CLK'event and CLK='1';
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q <= memory(to_integer(unsigned(addr)));
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end process;
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end Behavioral;
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