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This commit is contained in:
Simard Yohan 2021-04-16 15:29:35 +02:00
commit 267630c1b1
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# Ignore everything
*
# ...even if they are in subdirectories
!*/
# Except vhdl files
!.gitignore
!*.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
S : out STD_LOGIC_VECTOR (7 downto 0);
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC;
Ctrl : in STD_LOGIC_VECTOR (1 downto 0));
end ALU;
architecture Behavioral of ALU is
SIGNAL aux : STD_LOGIC_VECTOR (7 downto 0);
SIGNAL A9 : STD_LOGIC_VECTOR (8 downto 0);
SIGNAL B9 : STD_LOGIC_VECTOR (8 downto 0);
SIGNAL ADD : STD_LOGIC_VECTOR (8 downto 0);
SIGNAL SUB : STD_LOGIC_VECTOR (8 downto 0);
SIGNAL MUL : STD_LOGIC_VECTOR (15 downto 0);
begin
A9 <= '0' & A;
B9 <= '0' & B;
ADD <= A9 + B9;
SUB <= A9 - B9;
MUL <= A * B;
aux <= ADD(7 downto 0) when Ctrl = "01" else
SUB(7 downto 0) when Ctrl = "10" else
MUL(7 downto 0) when Ctrl = "11" else
(others => '0');
O <= ADD(8) when Ctrl = "01" else
'0' when Ctrl = "11" and MUL(15 downto 8) = "00000000" else
'1' when Ctrl = "11" else
'0';
C <= ADD(8) when Ctrl = "01" else '0';
Z <= '1' when aux = "00000000" else '0';
S <= aux;
end Behavioral;

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ALU_test IS
END ALU_test;
ARCHITECTURE behavior OF ALU_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
S : OUT std_logic_vector(7 downto 0);
O : OUT std_logic;
Z : OUT std_logic;
C : OUT std_logic;
Ctrl : IN std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal Ctrl : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal S : std_logic_vector(7 downto 0);
signal O : std_logic;
signal Z : std_logic;
signal C : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
A => A,
B => B,
S => S,
O => O,
Z => Z,
C => C,
Ctrl => Ctrl
);
-- Stimulus process
stim_proc: process
begin
A <=
"00000001",
"11111000" after 1 ms,
"00000010" after 2 ms,
"11001100" after 3 ms,
"00000011" after 4 ms,
"00000001" after 5 ms;
B <=
"00000011",
"10000000" after 1 ms,
"00000011" after 2 ms,
"01100101" after 3 ms,
"00000001" after 4 ms,
"00000011" after 5 ms;
Ctrl <=
"01",
"11" after 2 ms,
"10" after 4 ms,
"00" after 6 ms,
"00" after 7 ms;
wait;
end process;
END;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CPU is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
end CPU;
architecture Behavioral of CPU is
constant AFC : std_logic_vector(7 downto 0) := "00000110";
constant HALT : std_logic_vector(7 downto 0) := "00000000";
COMPONENT ALU
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
S : OUT std_logic_vector(7 downto 0);
O : OUT std_logic;
Z : OUT std_logic;
C : OUT std_logic;
Ctrl : IN std_logic_vector(1 downto 0)
);
END COMPONENT;
COMPONENT registers
PORT(
addr_A : IN std_logic_vector(0 to 3);
addr_B : IN std_logic_vector(0 to 3);
addr_W : IN std_logic_vector(0 to 3);
W : IN std_logic;
DATA : IN std_logic_vector(0 to 7);
RST : IN std_logic;
CLK : IN std_logic;
QA : OUT std_logic_vector(0 to 7);
QB : OUT std_logic_vector(0 to 7)
);
END COMPONENT;
COMPONENT instruction_memory
PORT(
addr : IN std_logic_vector(7 downto 0);
q : OUT std_logic_vector(31 downto 0);
clk : IN std_logic
);
END COMPONENT;
COMPONENT data_memory
PORT(
addr : IN std_logic_vector(7 downto 0);
data : IN std_logic_vector(7 downto 0);
rw : IN std_logic;
rst : IN std_logic;
clk : IN std_logic;
q : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal halted : std_logic := '0';
-- Interfaces composants
signal ALU_A : std_logic_vector(7 downto 0);
signal ALU_B : std_logic_vector(7 downto 0);
signal ALU_S : std_logic_vector(7 downto 0);
signal ALU_O : std_logic;
signal ALU_Z : std_logic;
signal ALU_C : std_logic;
signal ALU_Ctrl : std_logic_vector(1 downto 0);
signal registers_addr_A : std_logic_vector(3 downto 0);
signal registers_addr_B : std_logic_vector(3 downto 0);
signal registers_addr_W : std_logic_vector(3 downto 0);
signal registers_W : std_logic;
signal registers_DATA : std_logic_vector(7 downto 0);
signal registers_QA : std_logic_vector(7 downto 0);
signal registers_QB : std_logic_vector(7 downto 0);
signal data_memory_addr : std_logic_vector(7 downto 0);
signal data_memory_data : std_logic_vector(7 downto 0);
signal data_memory_rw : std_logic;
signal data_memory_q : std_logic_vector(7 downto 0);
signal instr_memory_addr : std_logic_vector(7 downto 0);
signal instr_memory_q : std_logic_vector(31 downto 0);
-- Etage 1
signal IP : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal OP1 : STD_LOGIC_VECTOR(7 downto 0);
signal A1 : STD_LOGIC_VECTOR(7 downto 0);
signal B1 : STD_LOGIC_VECTOR(7 downto 0);
signal C1 : STD_LOGIC_VECTOR(7 downto 0);
-- Etage 2
signal OP2 : STD_LOGIC_VECTOR(7 downto 0);
signal A2 : STD_LOGIC_VECTOR(7 downto 0);
signal B2 : STD_LOGIC_VECTOR(7 downto 0);
signal C2 : STD_LOGIC_VECTOR(7 downto 0);
-- Etage 3
signal OP3 : STD_LOGIC_VECTOR(7 downto 0);
signal A3 : STD_LOGIC_VECTOR(7 downto 0);
signal B3 : STD_LOGIC_VECTOR(7 downto 0);
-- Etage 4
signal OP4 : STD_LOGIC_VECTOR(7 downto 0);
signal A4 : STD_LOGIC_VECTOR(7 downto 0);
signal B4 : STD_LOGIC_VECTOR(7 downto 0);
-- Etage 5
begin
myalu: ALU PORT MAP (
A => alu_a,
B => alu_b,
S => alu_s,
O => alu_o,
Z => alu_z,
C => alu_c,
Ctrl => alu_ctrl
);
reg: registers PORT MAP (
addr_A => registers_addr_A,
addr_B => registers_addr_B,
addr_W => registers_addr_W,
W => registers_W,
DATA => registers_data,
RST => rst,
CLK => clk,
QA => registers_qa,
QB => registers_qb
);
data_mem: data_memory PORT MAP (
addr => data_memory_addr,
data => data_memory_data,
rw => data_memory_rw,
rst => rst,
clk => clk,
q => data_memory_q
);
instr_mem: instruction_memory PORT MAP (
addr => instr_memory_addr,
q => instr_memory_q,
clk => clk
);
process
begin
wait until CLK'event and CLK='1';
if (halted = '0') then
-- Etage 5
registers_addr_W <= A4(3 downto 0);
if OP4 = AFC then
registers_W <= '1';
elsif OP4 = HALT then
halted <= '1';
else
registers_W <= '0';
end if;
registers_data <= B4;
-- Etage 4
OP4 <= OP3;
A4 <= A3;
B4 <= B3;
-- Etage 3
OP3 <= OP2;
A3 <= A2;
B3 <= B2;
-- Etage 2
OP2 <= OP1;
A2 <= A1;
B2 <= B1;
C2 <= C1;
-- Etage 1
instr_memory_addr <= IP;
C1 <= instr_memory_q(7 downto 0);
B1 <= instr_memory_q(15 downto 8);
A1 <= instr_memory_q(23 downto 16);
OP1 <= instr_memory_q(31 downto 24);
-- IP <= IP + 1;
end if;
end process;
end Behavioral;

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY CPU_test IS
END CPU_test;
ARCHITECTURE behavior OF CPU_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CPU
PORT(
clk : in STD_LOGIC;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CPU PORT MAP (
clk => clk,
rst => rst
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1' after 2*clk_period;
wait for 10*clk_period;
wait;
end process;
END;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_memory is
Port ( addr : in STD_LOGIC_VECTOR (7 downto 0);
data : in STD_LOGIC_VECTOR (7 downto 0);
rw : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (7 downto 0));
end data_memory;
architecture Behavioral of data_memory is
type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(7 downto 0);
signal memory: MEMORY_TYPE;
begin
process
begin
wait until CLK'event and CLK='1';
if (rst = '0') then
memory <= (others => (others => '0'));
elsif (rw = '0') then
memory(to_integer(unsigned(addr))) <= data;
else
q <= memory(to_integer(unsigned(addr)));
end if;
end process;
end Behavioral;

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY data_memory_test IS
END data_memory_test;
ARCHITECTURE behavior OF data_memory_test IS
COMPONENT data_memory
PORT(
addr : IN std_logic_vector(7 downto 0);
data : IN std_logic_vector(7 downto 0);
rw : IN std_logic;
rst : IN std_logic;
clk : IN std_logic;
q : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal addr : std_logic_vector(7 downto 0) := (others => '0');
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal rw : std_logic := '0';
signal rst : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal q : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: data_memory PORT MAP (
addr => addr,
data => data,
rw => rw,
rst => rst,
clk => clk,
q => q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
addr <=
"00000000",
"00000010" after 1*CLK_period,
"00000110" after 2*CLK_period,
"00001000" after 3*CLK_period,
"00001100" after 4*CLK_period,
"00000000" after 5*CLK_period,
"00000001" after 6*CLK_period,
"00000010" after 8*CLK_period,
"00000000" after 9*CLK_period,
"00001111" after 11*CLK_period;
DATA <=
"01010101",
"10101010" after 6*CLK_period,
"00000000" after 7*CLK_period,
"11111111" after 8*CLK_period,
"00001111" after 10*CLK_period;
rw <=
'1',
'0' after 5*CLK_period,
'1' after 9*CLK_period,
'0' after 10*CLK_period;
RST <= '1' after clk_period, '0' after 12*CLK_period;
wait;
end process;
END;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity instruction_memory is
Port ( addr : in STD_LOGIC_VECTOR (7 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0);
clk : in STD_LOGIC);
end instruction_memory;
architecture Behavioral of instruction_memory is
type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(31 downto 0);
signal memory: MEMORY_TYPE := (0 => "00000110000000010000001000000000", others => (others => '0'));
begin
process
begin
wait until CLK'event and CLK='1';
q <= memory(to_integer(unsigned(addr)));
end process;
end Behavioral;

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY instruction_memory_test IS
END instruction_memory_test;
ARCHITECTURE behavior OF instruction_memory_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT instruction_memory
PORT(
addr : IN std_logic_vector(7 downto 0);
q : OUT std_logic_vector(31 downto 0);
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal addr : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal q : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: instruction_memory PORT MAP (
addr => addr,
q => q,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
addr <=
"00000000",
"00000010" after 1*CLK_period,
"00000110" after 2*CLK_period,
"00001000" after 3*CLK_period,
"00001100" after 4*CLK_period,
"00000000" after 5*CLK_period,
"00000001" after 6*CLK_period,
"00000010" after 8*CLK_period,
"00000000" after 9*CLK_period,
"00001111" after 11*CLK_period;
wait;
end process;
END;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity registers is
Port ( addr_A : in STD_LOGIC_VECTOR (3 downto 0);
addr_B : in STD_LOGIC_VECTOR (3 downto 0);
addr_W : in STD_LOGIC_VECTOR (3 downto 0);
W : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
QA : out STD_LOGIC_VECTOR (7 downto 0);
QB : out STD_LOGIC_VECTOR (7 downto 0));
end registers;
architecture Behavioral of registers is
type REGISTER_BANK is array (15 downto 0) of std_logic_vector(7 downto 0);
SIGNAL RB : REGISTER_BANK;
begin
process
begin
wait until CLK'event and CLK='1';
if (RST = '0') then
RB <= (others => (others => '0'));
elsif (W = '1') then
RB(to_integer(unsigned(addr_W))) <= DATA;
end if;
end process;
QA <= RB(to_integer(unsigned(addr_A))) when W = '0' or addr_W /= addr_A else DATA;
QB <= RB(to_integer(unsigned(addr_B))) when W = '0' or addr_W /= addr_B else DATA;
end Behavioral;

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY registers_test IS
END registers_test;
ARCHITECTURE behavior OF registers_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT registers
PORT(
addr_A : IN std_logic_vector(0 to 3);
addr_B : IN std_logic_vector(0 to 3);
addr_W : IN std_logic_vector(0 to 3);
W : IN std_logic;
DATA : IN std_logic_vector(0 to 7);
RST : IN std_logic;
CLK : IN std_logic;
QA : OUT std_logic_vector(0 to 7);
QB : OUT std_logic_vector(0 to 7)
);
END COMPONENT;
--Inputs
signal addr_A : std_logic_vector(0 to 3) := (others => '0');
signal addr_B : std_logic_vector(0 to 3) := (others => '0');
signal addr_W : std_logic_vector(0 to 3) := (others => '0');
signal W : std_logic := '0';
signal DATA : std_logic_vector(0 to 7) := (others => '0');
signal RST : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal QA : std_logic_vector(0 to 7);
signal QB : std_logic_vector(0 to 7);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: registers PORT MAP (
addr_A => addr_A,
addr_B => addr_B,
addr_W => addr_W,
W => W,
DATA => DATA,
RST => RST,
CLK => CLK,
QA => QA,
QB => QB
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
addr_A <=
"0000",
"0010" after 1*CLK_period,
"0110" after 2*CLK_period,
"1000" after 3*CLK_period,
"1100" after 4*CLK_period,
"0000" after 5*CLK_period,
"0001" after 6*CLK_period,
"0010" after 8*CLK_period,
"1000" after 9*CLK_period,
"1111" after 11*CLK_period;
addr_B <=
"0000",
"0001" after 1*CLK_period,
"0111" after 2*CLK_period,
"1000" after 3*CLK_period,
"1111" after 4*CLK_period,
"0001" after 5*CLK_period,
"1111" after 9*CLK_period,
"0001" after 11*CLK_period;
addr_W <=
"0000",
"0001" after 6*CLK_period,
"0010" after 7*CLK_period,
"1000" after 8*CLK_period,
"1111" after 9*CLK_period;
DATA <=
"01010101",
"10101010" after 6*CLK_period,
"00000000" after 7*CLK_period,
"11111111" after 8*CLK_period,
"00001111" after 10*CLK_period;
W <=
'0',
'1' after 5*CLK_period,
'0' after 9*CLK_period,
'1' after 10*CLK_period;
RST <= '1', '0' after 12*CLK_period;
wait;
end process;
END;