library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity instruction_memory is
    Port ( addr : in  STD_LOGIC_VECTOR (7 downto 0);
           q : out  STD_LOGIC_VECTOR (31 downto 0);
           clk : in  STD_LOGIC);
end instruction_memory;

architecture Behavioral of instruction_memory is
	type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(31 downto 0);
	signal memory: MEMORY_TYPE := (0 => "00000110000000010000001000000000", others => (others => '0'));
begin
	process
	begin
		wait until CLK'event and CLK='1';
			q <= memory(to_integer(unsigned(addr)));
	end process;
end Behavioral;