40 lines
1.2 KiB
VHDL
40 lines
1.2 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity ALU is
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Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
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B : in STD_LOGIC_VECTOR (7 downto 0);
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S : out STD_LOGIC_VECTOR (7 downto 0);
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O : out STD_LOGIC;
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Z : out STD_LOGIC;
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C : out STD_LOGIC;
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Ctrl : in STD_LOGIC_VECTOR (1 downto 0));
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end ALU;
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architecture Behavioral of ALU is
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SIGNAL aux : STD_LOGIC_VECTOR (7 downto 0);
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SIGNAL A9 : STD_LOGIC_VECTOR (8 downto 0);
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SIGNAL B9 : STD_LOGIC_VECTOR (8 downto 0);
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SIGNAL ADD : STD_LOGIC_VECTOR (8 downto 0);
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SIGNAL SUB : STD_LOGIC_VECTOR (8 downto 0);
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SIGNAL MUL : STD_LOGIC_VECTOR (15 downto 0);
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begin
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A9 <= '0' & A;
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B9 <= '0' & B;
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ADD <= A9 + B9;
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SUB <= A9 - B9;
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MUL <= A * B;
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aux <= ADD(7 downto 0) when Ctrl = "01" else
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SUB(7 downto 0) when Ctrl = "10" else
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MUL(7 downto 0) when Ctrl = "11" else
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(others => '0');
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O <= ADD(8) when Ctrl = "01" else
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'0' when Ctrl = "11" and MUL(15 downto 8) = "00000000" else
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'1' when Ctrl = "11" else
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'0';
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C <= ADD(8) when Ctrl = "01" else '0';
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Z <= '1' when aux = "00000000" else '0';
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S <= aux;
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end Behavioral;
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