library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
           B : in  STD_LOGIC_VECTOR (7 downto 0);
           S : out  STD_LOGIC_VECTOR (7 downto 0);
           O : out  STD_LOGIC;
           Z : out  STD_LOGIC;
           C : out  STD_LOGIC;
           Ctrl : in  STD_LOGIC_VECTOR (1 downto 0));
end ALU;

architecture Behavioral of ALU is
	SIGNAL aux : STD_LOGIC_VECTOR (7 downto 0);
	SIGNAL A9 : STD_LOGIC_VECTOR (8 downto 0);
	SIGNAL B9 : STD_LOGIC_VECTOR (8 downto 0);
	SIGNAL ADD : STD_LOGIC_VECTOR (8 downto 0);
	SIGNAL SUB : STD_LOGIC_VECTOR (8 downto 0);
	SIGNAL MUL : STD_LOGIC_VECTOR (15 downto 0);
begin
	A9 <= '0' & A;
	B9 <= '0' & B;
	ADD <= A9 + B9;
	SUB <= A9 - B9;
	MUL <= A * B;
	aux <= ADD(7 downto 0) when Ctrl = "01" else
		  SUB(7 downto 0) when Ctrl = "10" else
		  MUL(7 downto 0) when Ctrl = "11" else
		  (others => '0');
	O <= ADD(8) when Ctrl = "01" else 
		  '0' when Ctrl = "11" and MUL(15 downto 8) = "00000000" else
		  '1' when Ctrl = "11" else
		  '0';
   C <= ADD(8) when Ctrl = "01" else '0';
	Z <= '1' when aux = "00000000" else '0';
	S <= aux;
end Behavioral;