30 lines
790 B
VHDL
30 lines
790 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity data_memory is
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Port ( addr : in STD_LOGIC_VECTOR (7 downto 0);
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data : in STD_LOGIC_VECTOR (7 downto 0);
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rw : in STD_LOGIC;
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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q : out STD_LOGIC_VECTOR (7 downto 0));
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end data_memory;
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architecture Behavioral of data_memory is
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type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(7 downto 0);
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signal memory: MEMORY_TYPE;
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begin
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process
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begin
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wait until CLK'event and CLK='1';
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if (rst = '0') then
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memory <= (others => (others => '0'));
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elsif (rw = '0') then
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memory(to_integer(unsigned(addr))) <= data;
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end if;
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end process;
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q <= memory(to_integer(unsigned(addr)));
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end Behavioral;
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