processor-2000/data_memory.vhd

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790 B
VHDL
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2021-04-16 15:29:35 +02:00
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_memory is
Port ( addr : in STD_LOGIC_VECTOR (7 downto 0);
data : in STD_LOGIC_VECTOR (7 downto 0);
rw : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (7 downto 0));
end data_memory;
architecture Behavioral of data_memory is
type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(7 downto 0);
signal memory: MEMORY_TYPE;
begin
process
begin
wait until CLK'event and CLK='1';
if (rst = '0') then
memory <= (others => (others => '0'));
elsif (rw = '0') then
memory(to_integer(unsigned(addr))) <= data;
end if;
end process;
q <= memory(to_integer(unsigned(addr)));
end Behavioral;