Browse Source

Add all instructions support + bubbles (wip)

Simard Yohan 2 years ago
parent
commit
fd03450f1c
6 changed files with 369 additions and 45 deletions
  1. 4
    0
      .gitignore
  2. 12
    8
      ALU.vhd
  3. 69
    33
      CPU.vhd
  4. 260
    0
      config_simu.wcfg
  5. 3
    3
      data_memory.vhd
  6. 21
    1
      instruction_memory.vhd

+ 4
- 0
.gitignore View File

@@ -6,3 +6,7 @@
6 6
 # Except vhdl files
7 7
 !.gitignore
8 8
 !*.vhd
9
+
10
+# and simulation config files
11
+!*.wcfg
12
+

+ 12
- 8
ALU.vhd View File

@@ -14,6 +14,10 @@ entity ALU is
14 14
 end ALU;
15 15
 
16 16
 architecture Behavioral of ALU is
17
+	constant Ctrl_ADD : STD_LOGIC_VECTOR (1 downto 0) := "01";
18
+	constant Ctrl_MUL : STD_LOGIC_VECTOR (1 downto 0) := "10";
19
+	constant Ctrl_SOU : STD_LOGIC_VECTOR (1 downto 0) := "11";
20
+	
17 21
 	SIGNAL aux : STD_LOGIC_VECTOR (7 downto 0);
18 22
 	SIGNAL A9 : STD_LOGIC_VECTOR (8 downto 0);
19 23
 	SIGNAL B9 : STD_LOGIC_VECTOR (8 downto 0);
@@ -26,15 +30,15 @@ begin
26 30
 	ADD <= A9 + B9;
27 31
 	SUB <= A9 - B9;
28 32
 	MUL <= A * B;
29
-	aux <= ADD(7 downto 0) when Ctrl = "01" else
30
-		  SUB(7 downto 0) when Ctrl = "10" else
31
-		  MUL(7 downto 0) when Ctrl = "11" else
32
-		  (others => '0');
33
-	O <= ADD(8) when Ctrl = "01" else 
34
-		  '0' when Ctrl = "11" and MUL(15 downto 8) = "00000000" else
35
-		  '1' when Ctrl = "11" else
33
+	aux <= ADD(7 downto 0) when Ctrl = Ctrl_ADD else
34
+		    SUB(7 downto 0) when Ctrl = Ctrl_SOU else
35
+		    MUL(7 downto 0) when Ctrl = Ctrl_MUL else
36
+		    (others => '0');
37
+	O <= ADD(8) when Ctrl = Ctrl_ADD else 
38
+		  '0' when Ctrl = Ctrl_MUL and MUL(15 downto 8) = "00000000" else
39
+		  '1' when Ctrl = Ctrl_MUL else
36 40
 		  '0';
37
-   C <= ADD(8) when Ctrl = "01" else '0';
41
+   C <= ADD(8) when Ctrl = Ctrl_ADD else '0';
38 42
 	Z <= '1' when aux = "00000000" else '0';
39 43
 	S <= aux;
40 44
 end Behavioral;

+ 69
- 33
CPU.vhd View File

@@ -1,6 +1,7 @@
1 1
 library IEEE;
2 2
 use IEEE.STD_LOGIC_1164.ALL;
3 3
 use IEEE.NUMERIC_STD.ALL;
4
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
4 5
 
5 6
 entity CPU is
6 7
     Port (
@@ -10,8 +11,20 @@ entity CPU is
10 11
 end CPU;
11 12
 
12 13
 architecture Behavioral of CPU is
14
+	constant NOP  : std_logic_vector(7 downto 0) := "00000000";
15
+	constant ADD  : std_logic_vector(7 downto 0) := "00000001";
16
+	constant MUL  : std_logic_vector(7 downto 0) := "00000010";
17
+	constant SOU  : std_logic_vector(7 downto 0) := "00000011";
18
+	constant DIV  : std_logic_vector(7 downto 0) := "00000100";
19
+	constant COP  : std_logic_vector(7 downto 0) := "00000101";
13 20
 	constant AFC  : std_logic_vector(7 downto 0) := "00000110";
14
-	constant HALT : std_logic_vector(7 downto 0) := "00000000";
21
+	constant LOAD : std_logic_vector(7 downto 0) := "00000111";
22
+	constant STORE: std_logic_vector(7 downto 0) := "00001000";
23
+	-- constant HALT : std_logic_vector(7 downto 0) := "00001001";
24
+	
25
+	constant MX1: std_logic_vector(8 downto 0) := "100111110";
26
+	constant MX2: std_logic_vector(8 downto 0) := "000011110";
27
+	constant needBubbles: std_logic_vector(8 downto 0) := "111111110";
15 28
 
16 29
 	COMPONENT ALU
17 30
 	PORT(
@@ -73,7 +86,7 @@ architecture Behavioral of CPU is
73 86
 	signal registers_addr_A : std_logic_vector(3 downto 0);
74 87
 	signal registers_addr_B : std_logic_vector(3 downto 0);
75 88
 	signal registers_addr_W : std_logic_vector(3 downto 0);
76
-	signal registers_W : std_logic;
89
+	signal registers_W : std_logic := '0';
77 90
 	signal registers_DATA : std_logic_vector(7 downto 0);
78 91
 	signal registers_QA : std_logic_vector(7 downto 0);
79 92
 	signal registers_QB : std_logic_vector(7 downto 0);
@@ -109,8 +122,7 @@ architecture Behavioral of CPU is
109 122
 	signal A4 : STD_LOGIC_VECTOR(7 downto 0);
110 123
 	signal B4 : STD_LOGIC_VECTOR(7 downto 0);
111 124
 
112
-	-- Etage 5
113
-
125
+	signal bubble : integer := 2;
114 126
 
115 127
 begin
116 128
    myalu: ALU PORT MAP (
@@ -150,47 +162,71 @@ begin
150 162
 		 clk => clk
151 163
 	  );
152 164
 
165
+	instr_memory_addr <= IP;
166
+	
167
+	registers_addr_W <= A4(3 downto 0);
168
+	registers_W <= '0' when (OP4 = NOP or OP4 = STORE) else '1';
169
+	registers_data <= B4;
170
+	registers_addr_A <= B1(3 downto 0);
171
+	registers_addr_B <= C1(3 downto 0);
172
+	
173
+	ALU_A <= B2;
174
+	ALU_B <= C2;
175
+	ALU_Ctrl <= OP2(1 downto 0);
176
+	
177
+	data_memory_RW <= '0' when (OP3 = STORE) else '1';
178
+	data_memory_addr <= A3 when (OP3 = STORE) else B3;
179
+	data_memory_data <= B3;
153 180
 	
154 181
 	process
155 182
 	begin
156 183
 	wait until CLK'event and CLK='1';
157 184
 		if (halted = '0') then
158
-			-- Etage 5
159
-			registers_addr_W <= A4(3 downto 0);
160
-			if OP4 = AFC then
161
-				registers_W <= '1';
162
-			elsif OP4 = HALT then
163
-				halted <= '1';
164
-			else
165
-				registers_W <= '0';
166
-			end if;
167
-			registers_data <= B4;
168
-
169
-			-- Etage 4
185
+			-- Etage 3 -> 4
170 186
 			OP4 <= OP3;
171 187
 			A4 <= A3;
172
-			B4 <= B3;
173
-
174
-			-- Etage 3
188
+			if (OP3 = LOAD) then
189
+				B4 <= data_memory_Q;
190
+			else
191
+				B4 <= B3;
192
+			end if;
193
+			
194
+			-- Etage 2 -> 3
175 195
 			OP3 <= OP2;
176 196
 			A3 <= A2;
177
-			B3 <= B2;
178
-		
179
-			-- Etage 2
197
+			if (MX2(to_integer(unsigned(OP2))) = '1') then
198
+				B3 <= ALU_S;
199
+			else
200
+				B3 <= B2;
201
+			end if;
202
+			
203
+			-- Etage 1 -> 2
180 204
 			OP2 <= OP1;
181 205
 			A2 <= A1;
182
-			B2 <= B1;
183
-			C2 <= C1;
184
-
185
-			
186
-			-- Etage 1
187
-			instr_memory_addr <= IP;
188
-			C1 <= instr_memory_q(7 downto 0);
189
-			B1 <= instr_memory_q(15 downto 8);
190
-			A1 <= instr_memory_q(23 downto 16);
191
-			OP1 <= instr_memory_q(31 downto 24);
206
+			if (MX1(to_integer(unsigned(OP1))) = '1') then
207
+				B2 <= registers_QA;
208
+			else 
209
+				B2 <= B1;
210
+			end if;
211
+			C2 <= registers_QB;
192 212
 			
193
-			-- IP <= IP + 1;
213
+			-- Memoire -> etage 1
214
+			if (bubble = 0) then
215
+				C1 <= instr_memory_q(7 downto 0);
216
+				B1 <= instr_memory_q(15 downto 8);
217
+				A1 <= instr_memory_q(23 downto 16);
218
+				OP1 <= instr_memory_q(31 downto 24);
219
+				IP <= IP + 1;
220
+				if (needBubbles(to_integer(unsigned(instr_memory_q(31 downto 24)))) = '1') then
221
+					bubble <= 3;
222
+				end if;
223
+			else
224
+				C1 <= "00000000";
225
+				B1 <= "00000000";
226
+				A1 <= "00000000";
227
+				OP1 <= NOP;
228
+				bubble <= bubble - 1;
229
+			end if;
194 230
 	end if;
195 231
 		
196 232
 	end process;

+ 260
- 0
config_simu.wcfg View File

@@ -0,0 +1,260 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<wave_config>
3
+   <wave_state>
4
+   </wave_state>
5
+   <db_ref_list>
6
+      <db_ref path="/home/ysimard/Documents/4A/projet_compilateur/processor-2000/CPU_test_isim_beh.wdb" id="1" type="auto">
7
+         <top_modules>
8
+            <top_module name="cpu_test" />
9
+            <top_module name="numeric_std" />
10
+            <top_module name="std_logic_1164" />
11
+            <top_module name="std_logic_arith" />
12
+            <top_module name="std_logic_unsigned" />
13
+         </top_modules>
14
+      </db_ref>
15
+   </db_ref_list>
16
+   <WVObjectSize size="11" />
17
+   <wvobject fp_name="/cpu_test/clk" type="logic" db_ref_id="1">
18
+      <obj_property name="ElementShortName">clk</obj_property>
19
+      <obj_property name="ObjectShortName">clk</obj_property>
20
+   </wvobject>
21
+   <wvobject fp_name="/cpu_test/rst" type="logic" db_ref_id="1">
22
+      <obj_property name="ElementShortName">rst</obj_property>
23
+      <obj_property name="ObjectShortName">rst</obj_property>
24
+   </wvobject>
25
+   <wvobject fp_name="/cpu_test/clk_period" type="other" db_ref_id="1">
26
+      <obj_property name="ElementShortName">clk_period</obj_property>
27
+      <obj_property name="ObjectShortName">clk_period</obj_property>
28
+   </wvobject>
29
+   <wvobject fp_name="/cpu_test/uut/ip" type="array" db_ref_id="1">
30
+      <obj_property name="ElementShortName">ip[7:0]</obj_property>
31
+      <obj_property name="ObjectShortName">ip[7:0]</obj_property>
32
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
33
+   </wvobject>
34
+   <wvobject fp_name="group39" type="group">
35
+      <obj_property name="label">etage 1</obj_property>
36
+      <obj_property name="DisplayName">label</obj_property>
37
+      <wvobject fp_name="/cpu_test/uut/bubble" type="other" db_ref_id="1">
38
+         <obj_property name="DisplayName">label</obj_property>
39
+         <obj_property name="ElementShortName">bubble</obj_property>
40
+         <obj_property name="ObjectShortName">bubble</obj_property>
41
+         <obj_property name="label">bubble</obj_property>
42
+      </wvobject>
43
+      <wvobject fp_name="/cpu_test/uut/op1" type="array" db_ref_id="1">
44
+         <obj_property name="ElementShortName">op1[7:0]</obj_property>
45
+         <obj_property name="ObjectShortName">op1[7:0]</obj_property>
46
+         <obj_property name="UseCustomSignalColor">true</obj_property>
47
+         <obj_property name="CustomSignalColor">#ff00ff</obj_property>
48
+         <obj_property name="Radix">HEXRADIX</obj_property>
49
+      </wvobject>
50
+      <wvobject fp_name="/cpu_test/uut/a1" type="array" db_ref_id="1">
51
+         <obj_property name="ElementShortName">a1[7:0]</obj_property>
52
+         <obj_property name="ObjectShortName">a1[7:0]</obj_property>
53
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
54
+      </wvobject>
55
+      <wvobject fp_name="/cpu_test/uut/b1" type="array" db_ref_id="1">
56
+         <obj_property name="ElementShortName">b1[7:0]</obj_property>
57
+         <obj_property name="ObjectShortName">b1[7:0]</obj_property>
58
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
59
+      </wvobject>
60
+      <wvobject fp_name="/cpu_test/uut/c1" type="array" db_ref_id="1">
61
+         <obj_property name="ElementShortName">c1[7:0]</obj_property>
62
+         <obj_property name="ObjectShortName">c1[7:0]</obj_property>
63
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
64
+      </wvobject>
65
+   </wvobject>
66
+   <wvobject fp_name="group40" type="group">
67
+      <obj_property name="label">etage 2</obj_property>
68
+      <obj_property name="DisplayName">label</obj_property>
69
+      <wvobject fp_name="/cpu_test/uut/op2" type="array" db_ref_id="1">
70
+         <obj_property name="ElementShortName">op2[7:0]</obj_property>
71
+         <obj_property name="ObjectShortName">op2[7:0]</obj_property>
72
+         <obj_property name="UseCustomSignalColor">true</obj_property>
73
+         <obj_property name="CustomSignalColor">#ff00ff</obj_property>
74
+         <obj_property name="Radix">HEXRADIX</obj_property>
75
+      </wvobject>
76
+      <wvobject fp_name="/cpu_test/uut/a2" type="array" db_ref_id="1">
77
+         <obj_property name="ElementShortName">a2[7:0]</obj_property>
78
+         <obj_property name="ObjectShortName">a2[7:0]</obj_property>
79
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
80
+      </wvobject>
81
+      <wvobject fp_name="/cpu_test/uut/b2" type="array" db_ref_id="1">
82
+         <obj_property name="ElementShortName">b2[7:0]</obj_property>
83
+         <obj_property name="ObjectShortName">b2[7:0]</obj_property>
84
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
85
+      </wvobject>
86
+      <wvobject fp_name="/cpu_test/uut/c2" type="array" db_ref_id="1">
87
+         <obj_property name="ElementShortName">c2[7:0]</obj_property>
88
+         <obj_property name="ObjectShortName">c2[7:0]</obj_property>
89
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
90
+      </wvobject>
91
+   </wvobject>
92
+   <wvobject fp_name="group41" type="group">
93
+      <obj_property name="label">etage 3</obj_property>
94
+      <obj_property name="DisplayName">label</obj_property>
95
+      <wvobject fp_name="/cpu_test/uut/op3" type="array" db_ref_id="1">
96
+         <obj_property name="ElementShortName">op3[7:0]</obj_property>
97
+         <obj_property name="ObjectShortName">op3[7:0]</obj_property>
98
+         <obj_property name="UseCustomSignalColor">true</obj_property>
99
+         <obj_property name="CustomSignalColor">#ff00ff</obj_property>
100
+         <obj_property name="Radix">HEXRADIX</obj_property>
101
+      </wvobject>
102
+      <wvobject fp_name="/cpu_test/uut/a3" type="array" db_ref_id="1">
103
+         <obj_property name="ElementShortName">a3[7:0]</obj_property>
104
+         <obj_property name="ObjectShortName">a3[7:0]</obj_property>
105
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
106
+      </wvobject>
107
+      <wvobject fp_name="/cpu_test/uut/b3" type="array" db_ref_id="1">
108
+         <obj_property name="ElementShortName">b3[7:0]</obj_property>
109
+         <obj_property name="ObjectShortName">b3[7:0]</obj_property>
110
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
111
+      </wvobject>
112
+   </wvobject>
113
+   <wvobject fp_name="group42" type="group">
114
+      <obj_property name="label">etage 4</obj_property>
115
+      <obj_property name="DisplayName">label</obj_property>
116
+      <wvobject fp_name="/cpu_test/uut/op4" type="array" db_ref_id="1">
117
+         <obj_property name="ElementShortName">op4[7:0]</obj_property>
118
+         <obj_property name="ObjectShortName">op4[7:0]</obj_property>
119
+         <obj_property name="UseCustomSignalColor">true</obj_property>
120
+         <obj_property name="CustomSignalColor">#ff00ff</obj_property>
121
+         <obj_property name="Radix">HEXRADIX</obj_property>
122
+      </wvobject>
123
+      <wvobject fp_name="/cpu_test/uut/a4" type="array" db_ref_id="1">
124
+         <obj_property name="ElementShortName">a4[7:0]</obj_property>
125
+         <obj_property name="ObjectShortName">a4[7:0]</obj_property>
126
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
127
+      </wvobject>
128
+      <wvobject fp_name="/cpu_test/uut/b4" type="array" db_ref_id="1">
129
+         <obj_property name="ElementShortName">b4[7:0]</obj_property>
130
+         <obj_property name="ObjectShortName">b4[7:0]</obj_property>
131
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
132
+      </wvobject>
133
+   </wvobject>
134
+   <wvobject fp_name="group62" type="group">
135
+      <obj_property name="label">registres</obj_property>
136
+      <obj_property name="DisplayName">label</obj_property>
137
+      <wvobject fp_name="/cpu_test/uut/reg/rb" type="array" db_ref_id="1">
138
+         <obj_property name="ElementShortName">rb[15:0]</obj_property>
139
+         <obj_property name="ObjectShortName">rb[15:0]</obj_property>
140
+         <obj_property name="UseCustomSignalColor">true</obj_property>
141
+         <obj_property name="CustomSignalColor">#00ffff</obj_property>
142
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
143
+         <wvobject fp_name="/cpu_test/uut/reg/rb[15]" type="array" db_ref_id="1">
144
+            <obj_property name="ElementShortName">[15]</obj_property>
145
+            <obj_property name="ObjectShortName">rb[15]</obj_property>
146
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
147
+         </wvobject>
148
+         <wvobject fp_name="/cpu_test/uut/reg/rb[14]" type="array" db_ref_id="1">
149
+            <obj_property name="ElementShortName">[14]</obj_property>
150
+            <obj_property name="ObjectShortName">rb[14]</obj_property>
151
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
152
+         </wvobject>
153
+         <wvobject fp_name="/cpu_test/uut/reg/rb[13]" type="array" db_ref_id="1">
154
+            <obj_property name="ElementShortName">[13]</obj_property>
155
+            <obj_property name="ObjectShortName">rb[13]</obj_property>
156
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
157
+         </wvobject>
158
+         <wvobject fp_name="/cpu_test/uut/reg/rb[12]" type="array" db_ref_id="1">
159
+            <obj_property name="ElementShortName">[12]</obj_property>
160
+            <obj_property name="ObjectShortName">rb[12]</obj_property>
161
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
162
+         </wvobject>
163
+         <wvobject fp_name="/cpu_test/uut/reg/rb[11]" type="array" db_ref_id="1">
164
+            <obj_property name="ElementShortName">[11]</obj_property>
165
+            <obj_property name="ObjectShortName">rb[11]</obj_property>
166
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
167
+         </wvobject>
168
+         <wvobject fp_name="/cpu_test/uut/reg/rb[10]" type="array" db_ref_id="1">
169
+            <obj_property name="ElementShortName">[10]</obj_property>
170
+            <obj_property name="ObjectShortName">rb[10]</obj_property>
171
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
172
+         </wvobject>
173
+         <wvobject fp_name="/cpu_test/uut/reg/rb[9]" type="array" db_ref_id="1">
174
+            <obj_property name="ElementShortName">[9]</obj_property>
175
+            <obj_property name="ObjectShortName">rb[9]</obj_property>
176
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
177
+         </wvobject>
178
+         <wvobject fp_name="/cpu_test/uut/reg/rb[8]" type="array" db_ref_id="1">
179
+            <obj_property name="ElementShortName">[8]</obj_property>
180
+            <obj_property name="ObjectShortName">rb[8]</obj_property>
181
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
182
+         </wvobject>
183
+         <wvobject fp_name="/cpu_test/uut/reg/rb[7]" type="array" db_ref_id="1">
184
+            <obj_property name="ElementShortName">[7]</obj_property>
185
+            <obj_property name="ObjectShortName">rb[7]</obj_property>
186
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
187
+         </wvobject>
188
+         <wvobject fp_name="/cpu_test/uut/reg/rb[6]" type="array" db_ref_id="1">
189
+            <obj_property name="ElementShortName">[6]</obj_property>
190
+            <obj_property name="ObjectShortName">rb[6]</obj_property>
191
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
192
+         </wvobject>
193
+         <wvobject fp_name="/cpu_test/uut/reg/rb[5]" type="array" db_ref_id="1">
194
+            <obj_property name="ElementShortName">[5]</obj_property>
195
+            <obj_property name="ObjectShortName">rb[5]</obj_property>
196
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
197
+         </wvobject>
198
+         <wvobject fp_name="/cpu_test/uut/reg/rb[4]" type="array" db_ref_id="1">
199
+            <obj_property name="ElementShortName">[4]</obj_property>
200
+            <obj_property name="ObjectShortName">rb[4]</obj_property>
201
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
202
+         </wvobject>
203
+         <wvobject fp_name="/cpu_test/uut/reg/rb[3]" type="array" db_ref_id="1">
204
+            <obj_property name="ElementShortName">[3]</obj_property>
205
+            <obj_property name="ObjectShortName">rb[3]</obj_property>
206
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
207
+         </wvobject>
208
+         <wvobject fp_name="/cpu_test/uut/reg/rb[2]" type="array" db_ref_id="1">
209
+            <obj_property name="ElementShortName">[2]</obj_property>
210
+            <obj_property name="ObjectShortName">rb[2]</obj_property>
211
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
212
+         </wvobject>
213
+         <wvobject fp_name="/cpu_test/uut/reg/rb[1]" type="array" db_ref_id="1">
214
+            <obj_property name="ElementShortName">[1]</obj_property>
215
+            <obj_property name="ObjectShortName">rb[1]</obj_property>
216
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
217
+         </wvobject>
218
+         <wvobject fp_name="/cpu_test/uut/reg/rb[0]" type="array" db_ref_id="1">
219
+            <obj_property name="ElementShortName">[0]</obj_property>
220
+            <obj_property name="ObjectShortName">rb[0]</obj_property>
221
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
222
+         </wvobject>
223
+      </wvobject>
224
+      <wvobject fp_name="/cpu_test/uut/reg/addr_a" type="array" db_ref_id="1">
225
+         <obj_property name="ElementShortName">addr_a[3:0]</obj_property>
226
+         <obj_property name="ObjectShortName">addr_a[3:0]</obj_property>
227
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
228
+      </wvobject>
229
+      <wvobject fp_name="/cpu_test/uut/reg/addr_w" type="array" db_ref_id="1">
230
+         <obj_property name="DisplayName">label</obj_property>
231
+         <obj_property name="ElementShortName">addr_w[3:0]</obj_property>
232
+         <obj_property name="ObjectShortName">addr_w[3:0]</obj_property>
233
+         <obj_property name="label">addr_w[3:0]</obj_property>
234
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
235
+      </wvobject>
236
+      <wvobject fp_name="/cpu_test/uut/reg/w" type="logic" db_ref_id="1">
237
+         <obj_property name="ElementShortName">w</obj_property>
238
+         <obj_property name="ObjectShortName">w</obj_property>
239
+      </wvobject>
240
+      <wvobject fp_name="/cpu_test/uut/reg/data" type="array" db_ref_id="1">
241
+         <obj_property name="ElementShortName">data[7:0]</obj_property>
242
+         <obj_property name="ObjectShortName">data[7:0]</obj_property>
243
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
244
+      </wvobject>
245
+   </wvobject>
246
+   <wvobject fp_name="/cpu_test/uut/data_mem/memory[8]" type="array" db_ref_id="1">
247
+      <obj_property name="ElementShortName">[8]</obj_property>
248
+      <obj_property name="ObjectShortName">memory[8]</obj_property>
249
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
250
+      <obj_property name="UseCustomSignalColor">true</obj_property>
251
+      <obj_property name="CustomSignalColor">#008080</obj_property>
252
+   </wvobject>
253
+   <wvobject fp_name="/cpu_test/uut/data_mem/memory[20]" type="array" db_ref_id="1">
254
+      <obj_property name="ElementShortName">[20]</obj_property>
255
+      <obj_property name="ObjectShortName">memory[20]</obj_property>
256
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
257
+      <obj_property name="UseCustomSignalColor">true</obj_property>
258
+      <obj_property name="CustomSignalColor">#008080</obj_property>
259
+   </wvobject>
260
+</wave_config>

+ 3
- 3
data_memory.vhd View File

@@ -22,9 +22,9 @@ begin
22 22
 				memory <= (others => (others => '0'));
23 23
 			elsif (rw = '0') then
24 24
 				memory(to_integer(unsigned(addr))) <= data;
25
-			else
26
-				q <= memory(to_integer(unsigned(addr)));
27 25
 			end if;
28 26
 	end process;
29
-end Behavioral;
30 27
 
28
+q <= memory(to_integer(unsigned(addr)));
29
+
30
+end Behavioral;

+ 21
- 1
instruction_memory.vhd View File

@@ -9,8 +9,28 @@ entity instruction_memory is
9 9
 end instruction_memory;
10 10
 
11 11
 architecture Behavioral of instruction_memory is
12
+	constant NOP  : std_logic_vector(7 downto 0) := "00000000";
13
+	constant ADD  : std_logic_vector(7 downto 0) := "00000001";
14
+	constant MUL  : std_logic_vector(7 downto 0) := "00000010";
15
+	constant SOU  : std_logic_vector(7 downto 0) := "00000011";
16
+	constant DIV  : std_logic_vector(7 downto 0) := "00000100";
17
+	constant COP  : std_logic_vector(7 downto 0) := "00000101";
18
+	constant AFC  : std_logic_vector(7 downto 0) := "00000110";
19
+	constant LOAD : std_logic_vector(7 downto 0) := "00000111";
20
+	constant STORE: std_logic_vector(7 downto 0) := "00001000";
21
+
12 22
 	type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(31 downto 0);
13
-	signal memory: MEMORY_TYPE := (0 => "00000110000000010000001000000000", others => (others => '0'));
23
+	signal memory: MEMORY_TYPE := (
24
+		1 => AFC   & "00000001" & "00000010" & "00000000", -- r1 <= 2
25
+		2 => COP   & "00000011" & "00000001" & "00000000", -- r3 <= r1  (= 2)
26
+		3 => ADD   & "00000100" & "00000001" & "00000011", -- 2 + 2 = 4 dans R4
27
+		4 => MUL   & "00000101" & "00000100" & "00000001", -- 4 * 2 = 8 dans R5
28
+		5 => SOU   & "00000010" & "00000101" & "00000100", -- 8 - 4 = 4 dans R2
29
+		6 => STORE & "00001000" & "00000010" & "00000000", -- store R2 (4) at address 8
30
+		7 => STORE & "00010100" & "00000101" & "00000000", -- store R5 (8) at address 20
31
+		8 => LOAD  & "00000111" & "00001000" & "00000000", -- load mem@8  (4) in R7
32
+		9 => LOAD  & "00001000" & "00010100" & "00000000", -- load mem@20 (8) in R8
33
+		others => (others => '0'));
14 34
 begin
15 35
 	process
16 36
 	begin

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