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improve aleas handling

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This commit is contained in:
Simard Yohan 2021-05-10 11:52:18 +02:00
parent e8c135f1b9
commit 7409c89285
2 changed files with 162 additions and 43 deletions
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119
CPU.vhd
View file

@ -24,7 +24,6 @@ architecture Behavioral of CPU is
constant MX1: std_logic_vector(8 downto 0) := "100111110"; constant MX1: std_logic_vector(8 downto 0) := "100111110";
constant MX2: std_logic_vector(8 downto 0) := "000011110"; constant MX2: std_logic_vector(8 downto 0) := "000011110";
constant needBubbles: std_logic_vector(8 downto 0) := "111111110";
COMPONENT ALU COMPONENT ALU
PORT( PORT(
@ -100,6 +99,10 @@ architecture Behavioral of CPU is
signal instr_memory_q : std_logic_vector(31 downto 0); signal instr_memory_q : std_logic_vector(31 downto 0);
-- Etage 1 -- Etage 1
signal OP1_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal B1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal C1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal IP : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal IP : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal OP1 : STD_LOGIC_VECTOR(7 downto 0) := NOP; signal OP1 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal A1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
@ -107,12 +110,19 @@ architecture Behavioral of CPU is
signal C1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal C1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-- Etage 2 -- Etage 2
signal OP2_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal B2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal C2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal OP2 : STD_LOGIC_VECTOR(7 downto 0) := NOP; signal OP2 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal A2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal B2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal B2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal C2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal C2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-- Etage 3 -- Etage 3
signal OP3_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A3_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal B3_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal OP3 : STD_LOGIC_VECTOR(7 downto 0) := NOP; signal OP3 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal A3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal B3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal B3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
@ -121,9 +131,21 @@ architecture Behavioral of CPU is
signal OP4 : STD_LOGIC_VECTOR(7 downto 0) := NOP; signal OP4 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal A4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal B4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal B4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal OP4_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A4_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal B4_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal bubble : integer := 3; -- Aleas
signal alea_write_P3: std_logic := '0';
signal alea_write_P3_reg: std_logic_vector(3 downto 0) := "0000";
signal alea_write_P2: std_logic := '0';
signal alea_write_P2_reg: std_logic_vector(3 downto 0) := "0000";
signal alea_read_B_P1: std_logic := '0';
signal alea_read_B_P1_reg: std_logic_vector(3 downto 0) := "0000";
signal alea_read_C_P1: std_logic := '0';
signal alea_read_C_P1_reg: std_logic_vector(3 downto 0) := "0000";
signal alea: std_logic := '0';
begin begin
myalu: ALU PORT MAP ( myalu: ALU PORT MAP (
A => alu_a, A => alu_a,
@ -178,51 +200,78 @@ begin
data_memory_addr <= A3 when (OP3 = STORE) else B3; data_memory_addr <= A3 when (OP3 = STORE) else B3;
data_memory_data <= B3; data_memory_data <= B3;
C1 <= instr_memory_q(7 downto 0) when (bubble = 0) else "00000000"; -- Etage 1
B1 <= instr_memory_q(15 downto 8) when (bubble = 0) else "00000000"; OP1_in <= instr_memory_q(31 downto 24);
A1 <= instr_memory_q(23 downto 16) when (bubble = 0) else "00000000"; A1_in <= instr_memory_q(23 downto 16);
OP1 <= instr_memory_q(31 downto 24) when (bubble = 0) else NOP; B1_in <= instr_memory_q(15 downto 8);
C1_in <= instr_memory_q(7 downto 0);
OP1 <= OP1_in;
A1 <= A1_in;
B1 <= B1_in;
C1 <= C1_in;
-- Etage 2
OP2_in <= OP1;
A2_in <= A1;
B2_in <= registers_QA when (MX1(to_integer(unsigned(OP1))) = '1') else B1;
C2_in <= registers_QB;
-- Etage 3
OP3_in <= OP2;
A3_in <= A2;
B3_in <= ALU_S when (MX2(to_integer(unsigned(OP2))) = '1') else B2;
-- Etage 4
OP4_in <= OP3;
A4_in <= A3;
B4_in <= data_memory_Q when (OP3 = LOAD) else B3;
-- Aleas
alea_write_P3 <= '0' when (OP4_in = NOP or OP4_in = STORE) else '1';
alea_write_P3_reg <= A4_in(3 downto 0);
alea_write_P2 <= '0' when (OP3_in = NOP or OP3_in = STORE) else '1';
alea_write_P2_reg <= A3_in(3 downto 0);
alea_read_B_P1 <= '0' when (OP1_in = NOP or OP1_in = AFC or OP1_in = LOAD) else '1';
alea_read_B_P1_reg <= B1_in(3 downto 0);
alea_read_C_P1 <= '1' when (OP1_in = ADD or OP1_in = MUL or OP1_in = DIV or OP1_in = SOU) else '0';
alea_read_C_P1_reg <= C1_in(3 downto 0);
alea <= '1'
when (
(alea_write_P3 = '1' and alea_read_B_P1 = '1' and alea_write_P3_reg = alea_read_B_P1_reg) or
(alea_write_P3 = '1' and alea_read_C_P1 = '1' and alea_write_P3_reg = alea_read_C_P1_reg) or
(alea_write_P2 = '1' and alea_read_B_P1 = '1' and alea_write_P2_reg = alea_read_B_P1_reg) or
(alea_write_P2 = '1' and alea_read_C_P1 = '1' and alea_write_P2_reg = alea_read_C_P1_reg))
else '0';
process process
begin begin
wait until CLK'event and CLK='1'; wait until CLK'event and CLK='1';
if (halted = '0') then if (halted = '0') then
-- Etage 3 -> 4 -- Etage 3 -> 4
OP4 <= OP3; OP4 <= OP4_in;
A4 <= A3; A4 <= A4_in;
if (OP3 = LOAD) then B4 <= B4_in;
B4 <= data_memory_Q;
else
B4 <= B3;
end if;
-- Etage 2 -> 3 -- Etage 2 -> 3
OP3 <= OP2; OP3 <= OP3_in;
A3 <= A2; A3 <= A3_in;
if (MX2(to_integer(unsigned(OP2))) = '1') then B3 <= B3_in;
B3 <= ALU_S;
else
B3 <= B2;
end if;
-- Etage 1 -> 2 -- Etage 1 -> 2
OP2 <= OP1; if (alea = '0') then
A2 <= A1; OP2 <= OP2_in;
if (MX1(to_integer(unsigned(OP1))) = '1') then A2 <= A2_in;
B2 <= registers_QA; B2 <= B2_in;
else C2 <= C2_in;
B2 <= B1;
end if;
C2 <= registers_QB;
-- Memoire -> etage 1
if (bubble = 0) then
IP <= IP + 1; IP <= IP + 1;
if (needBubbles(to_integer(unsigned(instr_memory_q(31 downto 24)))) = '1') then
bubble <= 3;
end if;
else else
bubble <= bubble - 1; OP2 <= NOP;
A2 <= "00000000";
B2 <= "00000000";
C2 <= "00000000";
end if; end if;
end if; end if;

86
config_simu.wcfg
View file

@ -13,7 +13,7 @@
</top_modules> </top_modules>
</db_ref> </db_ref>
</db_ref_list> </db_ref_list>
<WVObjectSize size="12" /> <WVObjectSize size="13" />
<wvobject fp_name="/cpu_test/clk" type="logic" db_ref_id="1"> <wvobject fp_name="/cpu_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property> <obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property> <obj_property name="ObjectShortName">clk</obj_property>
@ -38,12 +38,6 @@
<wvobject fp_name="group39" type="group"> <wvobject fp_name="group39" type="group">
<obj_property name="label">etage 1</obj_property> <obj_property name="label">etage 1</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/cpu_test/uut/bubble" type="other" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">bubble</obj_property>
<obj_property name="ObjectShortName">bubble</obj_property>
<obj_property name="label">bubble</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/op1" type="array" db_ref_id="1"> <wvobject fp_name="/cpu_test/uut/op1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op1[7:0]</obj_property> <obj_property name="ElementShortName">op1[7:0]</obj_property>
<obj_property name="ObjectShortName">op1[7:0]</obj_property> <obj_property name="ObjectShortName">op1[7:0]</obj_property>
@ -70,6 +64,28 @@
<wvobject fp_name="group40" type="group"> <wvobject fp_name="group40" type="group">
<obj_property name="label">etage 2</obj_property> <obj_property name="label">etage 2</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/cpu_test/uut/op2_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op2_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op2_in[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff00ff</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/a2_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a2_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a2_in[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/b2_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b2_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b2_in[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/c2_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c2_in[7:0]</obj_property>
<obj_property name="ObjectShortName">c2_in[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/op2" type="array" db_ref_id="1"> <wvobject fp_name="/cpu_test/uut/op2" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op2[7:0]</obj_property> <obj_property name="ElementShortName">op2[7:0]</obj_property>
<obj_property name="ObjectShortName">op2[7:0]</obj_property> <obj_property name="ObjectShortName">op2[7:0]</obj_property>
@ -212,7 +228,7 @@
<wvobject fp_name="/cpu_test/uut/reg/rb[2]" type="array" db_ref_id="1"> <wvobject fp_name="/cpu_test/uut/reg/rb[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property> <obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">rb[2]</obj_property> <obj_property name="ObjectShortName">rb[2]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property> <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/cpu_test/uut/reg/rb[1]" type="array" db_ref_id="1"> <wvobject fp_name="/cpu_test/uut/reg/rb[1]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[1]</obj_property> <obj_property name="ElementShortName">[1]</obj_property>
@ -261,4 +277,58 @@
<obj_property name="UseCustomSignalColor">true</obj_property> <obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#008080</obj_property> <obj_property name="CustomSignalColor">#008080</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="group61" type="group">
<obj_property name="label">aleas</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/cpu_test/uut/alea_write_p3" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">alea_write_p3</obj_property>
<obj_property name="ObjectShortName">alea_write_p3</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/alea_write_p3_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">alea_write_p3_reg[3:0]</obj_property>
<obj_property name="ObjectShortName">alea_write_p3_reg[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/alea_write_p2" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">alea_write_p2</obj_property>
<obj_property name="ObjectShortName">alea_write_p2</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/alea_write_p2_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">alea_write_p2_reg[3:0]</obj_property>
<obj_property name="ObjectShortName">alea_write_p2_reg[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/alea_read_b_p1" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">alea_read_b_p1</obj_property>
<obj_property name="ObjectShortName">alea_read_b_p1</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/alea_read_b_p1_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">alea_read_b_p1_reg[3:0]</obj_property>
<obj_property name="ObjectShortName">alea_read_b_p1_reg[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/alea_read_c_p1" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">alea_read_c_p1</obj_property>
<obj_property name="ObjectShortName">alea_read_c_p1</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/alea_read_c_p1_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">alea_read_c_p1_reg[3:0]</obj_property>
<obj_property name="ObjectShortName">alea_read_c_p1_reg[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/alea" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">alea</obj_property>
<obj_property name="ObjectShortName">alea</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff0000</obj_property>
</wvobject>
</wvobject>
</wave_config> </wave_config>