fix instruction memory offset

CPU.vhd

@@ -83,46 +83,46 @@ architecture Behavioral of CPU is
 	signal ALU_C : std_logic;
 	signal ALU_Ctrl : std_logic_vector(1 downto 0);
 	
-	signal registers_addr_A : std_logic_vector(3 downto 0);
-	signal registers_addr_B : std_logic_vector(3 downto 0);
-	signal registers_addr_W : std_logic_vector(3 downto 0);
+	signal registers_addr_A : std_logic_vector(3 downto 0) := (others => '0');
+	signal registers_addr_B : std_logic_vector(3 downto 0) := (others => '0');
+	signal registers_addr_W : std_logic_vector(3 downto 0) := (others => '0');
 	signal registers_W : std_logic := '0';
-	signal registers_DATA : std_logic_vector(7 downto 0);
+	signal registers_DATA : std_logic_vector(7 downto 0) := (others => '0');
 	signal registers_QA : std_logic_vector(7 downto 0);
 	signal registers_QB : std_logic_vector(7 downto 0);
 	
-	signal data_memory_addr : std_logic_vector(7 downto 0);
-	signal data_memory_data : std_logic_vector(7 downto 0);
-	signal data_memory_rw : std_logic;
+	signal data_memory_addr : std_logic_vector(7 downto 0) := (others => '0');
+	signal data_memory_data : std_logic_vector(7 downto 0) := (others => '0');
+	signal data_memory_rw : std_logic := '1';
 	signal data_memory_q : std_logic_vector(7 downto 0);
 	
-	signal instr_memory_addr : std_logic_vector(7 downto 0);
+	signal instr_memory_addr : std_logic_vector(7 downto 0) := (others => '0');
 	signal instr_memory_q : std_logic_vector(31 downto 0);
 
 	-- Etage 1
 	signal IP : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-	signal OP1 : STD_LOGIC_VECTOR(7 downto 0);
-	signal A1 : STD_LOGIC_VECTOR(7 downto 0);
-	signal B1 : STD_LOGIC_VECTOR(7 downto 0);
-	signal C1 : STD_LOGIC_VECTOR(7 downto 0);
+	signal OP1 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
+	signal A1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+	signal B1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+	signal C1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
 
 	-- Etage 2
-	signal OP2 : STD_LOGIC_VECTOR(7 downto 0);
-	signal A2 : STD_LOGIC_VECTOR(7 downto 0);
-	signal B2 : STD_LOGIC_VECTOR(7 downto 0);
-	signal C2 : STD_LOGIC_VECTOR(7 downto 0);
+	signal OP2 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
+	signal A2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+	signal B2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+	signal C2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
 
 	-- Etage 3
-	signal OP3 : STD_LOGIC_VECTOR(7 downto 0);
-	signal A3 : STD_LOGIC_VECTOR(7 downto 0);
-	signal B3 : STD_LOGIC_VECTOR(7 downto 0);
+	signal OP3 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
+	signal A3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+	signal B3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
 
 	-- Etage 4
-	signal OP4 : STD_LOGIC_VECTOR(7 downto 0);
-	signal A4 : STD_LOGIC_VECTOR(7 downto 0);
-	signal B4 : STD_LOGIC_VECTOR(7 downto 0);
+	signal OP4 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
+	signal A4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+	signal B4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
 
-	signal bubble : integer := 2;
+	signal bubble : integer := 3;
 
 begin
    myalu: ALU PORT MAP (
@@ -178,6 +178,11 @@ begin
 	data_memory_addr <= A3 when (OP3 = STORE) else B3;
 	data_memory_data <= B3;
 	
+	C1 <= instr_memory_q(7 downto 0) when (bubble = 0) else "00000000";
+	B1 <= instr_memory_q(15 downto 8) when (bubble = 0) else "00000000";
+	A1 <= instr_memory_q(23 downto 16) when (bubble = 0) else "00000000";
+	OP1 <= instr_memory_q(31 downto 24) when (bubble = 0) else NOP;
+	
 	process
 	begin
 	wait until CLK'event and CLK='1';
@@ -212,19 +217,11 @@ begin
 			
 			-- Memoire -> etage 1
 			if (bubble = 0) then
-				C1 <= instr_memory_q(7 downto 0);
-				B1 <= instr_memory_q(15 downto 8);
-				A1 <= instr_memory_q(23 downto 16);
-				OP1 <= instr_memory_q(31 downto 24);
 				IP <= IP + 1;
 				if (needBubbles(to_integer(unsigned(instr_memory_q(31 downto 24)))) = '1') then
 					bubble <= 3;
 				end if;
 			else
-				C1 <= "00000000";
-				B1 <= "00000000";
-				A1 <= "00000000";
-				OP1 <= NOP;
 				bubble <= bubble - 1;
 			end if;
 	end if;

config_simu.wcfg

@@ -13,7 +13,7 @@
          </top_modules>
       </db_ref>
    </db_ref_list>
-   <WVObjectSize size="11" />
+   <WVObjectSize size="12" />
    <wvobject fp_name="/cpu_test/clk" type="logic" db_ref_id="1">
       <obj_property name="ElementShortName">clk</obj_property>
       <obj_property name="ObjectShortName">clk</obj_property>
@@ -26,6 +26,10 @@
       <obj_property name="ElementShortName">clk_period</obj_property>
       <obj_property name="ObjectShortName">clk_period</obj_property>
    </wvobject>
+   <wvobject fp_name="/cpu_test/uut/instr_mem/q" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">q[31:0]</obj_property>
+      <obj_property name="ObjectShortName">q[31:0]</obj_property>
+   </wvobject>
    <wvobject fp_name="/cpu_test/uut/ip" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">ip[7:0]</obj_property>
       <obj_property name="ObjectShortName">ip[7:0]</obj_property>

instruction_memory.vhd

@@ -32,10 +32,6 @@ architecture Behavioral of instruction_memory is
 		9 => LOAD  & "00001000" & "00010100" & "00000000", -- load mem@20 (8) in R8
 		others => (others => '0'));
 begin
-	process
-	begin
-		wait until CLK'event and CLK='1';
-			q <= memory(to_integer(unsigned(addr)));
-	end process;
+		q <= memory(to_integer(unsigned(addr)));
 end Behavioral;