diff --git a/CPU.vhd b/CPU.vhd
index c3e3b9a..dda8bdc 100644
--- a/CPU.vhd
+++ b/CPU.vhd
@@ -24,7 +24,6 @@ architecture Behavioral of CPU is
constant MX1: std_logic_vector(8 downto 0) := "100111110";
constant MX2: std_logic_vector(8 downto 0) := "000011110";
- constant needBubbles: std_logic_vector(8 downto 0) := "111111110";
COMPONENT ALU
PORT(
@@ -100,6 +99,10 @@ architecture Behavioral of CPU is
signal instr_memory_q : std_logic_vector(31 downto 0);
-- Etage 1
+ signal OP1_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
+ signal A1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+ signal B1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+ signal C1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal IP : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal OP1 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
@@ -107,12 +110,19 @@ architecture Behavioral of CPU is
signal C1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-- Etage 2
+ signal OP2_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
+ signal A2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+ signal B2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+ signal C2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal OP2 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal B2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal C2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-- Etage 3
+ signal OP3_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
+ signal A3_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+ signal B3_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal OP3 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal B3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
@@ -121,9 +131,21 @@ architecture Behavioral of CPU is
signal OP4 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
signal A4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal B4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+ signal OP4_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
+ signal A4_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+ signal B4_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal bubble : integer := 3;
-
+ -- Aleas
+ signal alea_write_P3: std_logic := '0';
+ signal alea_write_P3_reg: std_logic_vector(3 downto 0) := "0000";
+ signal alea_write_P2: std_logic := '0';
+ signal alea_write_P2_reg: std_logic_vector(3 downto 0) := "0000";
+ signal alea_read_B_P1: std_logic := '0';
+ signal alea_read_B_P1_reg: std_logic_vector(3 downto 0) := "0000";
+ signal alea_read_C_P1: std_logic := '0';
+ signal alea_read_C_P1_reg: std_logic_vector(3 downto 0) := "0000";
+ signal alea: std_logic := '0';
+
begin
myalu: ALU PORT MAP (
A => alu_a,
@@ -178,51 +200,78 @@ begin
data_memory_addr <= A3 when (OP3 = STORE) else B3;
data_memory_data <= B3;
- C1 <= instr_memory_q(7 downto 0) when (bubble = 0) else "00000000";
- B1 <= instr_memory_q(15 downto 8) when (bubble = 0) else "00000000";
- A1 <= instr_memory_q(23 downto 16) when (bubble = 0) else "00000000";
- OP1 <= instr_memory_q(31 downto 24) when (bubble = 0) else NOP;
+ -- Etage 1
+ OP1_in <= instr_memory_q(31 downto 24);
+ A1_in <= instr_memory_q(23 downto 16);
+ B1_in <= instr_memory_q(15 downto 8);
+ C1_in <= instr_memory_q(7 downto 0);
+ OP1 <= OP1_in;
+ A1 <= A1_in;
+ B1 <= B1_in;
+ C1 <= C1_in;
+
+ -- Etage 2
+ OP2_in <= OP1;
+ A2_in <= A1;
+ B2_in <= registers_QA when (MX1(to_integer(unsigned(OP1))) = '1') else B1;
+ C2_in <= registers_QB;
+
+ -- Etage 3
+ OP3_in <= OP2;
+ A3_in <= A2;
+ B3_in <= ALU_S when (MX2(to_integer(unsigned(OP2))) = '1') else B2;
+
+ -- Etage 4
+ OP4_in <= OP3;
+ A4_in <= A3;
+ B4_in <= data_memory_Q when (OP3 = LOAD) else B3;
+
+ -- Aleas
+ alea_write_P3 <= '0' when (OP4_in = NOP or OP4_in = STORE) else '1';
+ alea_write_P3_reg <= A4_in(3 downto 0);
+ alea_write_P2 <= '0' when (OP3_in = NOP or OP3_in = STORE) else '1';
+ alea_write_P2_reg <= A3_in(3 downto 0);
+ alea_read_B_P1 <= '0' when (OP1_in = NOP or OP1_in = AFC or OP1_in = LOAD) else '1';
+ alea_read_B_P1_reg <= B1_in(3 downto 0);
+ alea_read_C_P1 <= '1' when (OP1_in = ADD or OP1_in = MUL or OP1_in = DIV or OP1_in = SOU) else '0';
+ alea_read_C_P1_reg <= C1_in(3 downto 0);
+
+ alea <= '1'
+ when (
+ (alea_write_P3 = '1' and alea_read_B_P1 = '1' and alea_write_P3_reg = alea_read_B_P1_reg) or
+ (alea_write_P3 = '1' and alea_read_C_P1 = '1' and alea_write_P3_reg = alea_read_C_P1_reg) or
+ (alea_write_P2 = '1' and alea_read_B_P1 = '1' and alea_write_P2_reg = alea_read_B_P1_reg) or
+ (alea_write_P2 = '1' and alea_read_C_P1 = '1' and alea_write_P2_reg = alea_read_C_P1_reg))
+ else '0';
+
process
begin
wait until CLK'event and CLK='1';
if (halted = '0') then
-- Etage 3 -> 4
- OP4 <= OP3;
- A4 <= A3;
- if (OP3 = LOAD) then
- B4 <= data_memory_Q;
- else
- B4 <= B3;
- end if;
+ OP4 <= OP4_in;
+ A4 <= A4_in;
+ B4 <= B4_in;
-- Etage 2 -> 3
- OP3 <= OP2;
- A3 <= A2;
- if (MX2(to_integer(unsigned(OP2))) = '1') then
- B3 <= ALU_S;
- else
- B3 <= B2;
- end if;
+ OP3 <= OP3_in;
+ A3 <= A3_in;
+ B3 <= B3_in;
-- Etage 1 -> 2
- OP2 <= OP1;
- A2 <= A1;
- if (MX1(to_integer(unsigned(OP1))) = '1') then
- B2 <= registers_QA;
- else
- B2 <= B1;
- end if;
- C2 <= registers_QB;
+ if (alea = '0') then
+ OP2 <= OP2_in;
+ A2 <= A2_in;
+ B2 <= B2_in;
+ C2 <= C2_in;
- -- Memoire -> etage 1
- if (bubble = 0) then
IP <= IP + 1;
- if (needBubbles(to_integer(unsigned(instr_memory_q(31 downto 24)))) = '1') then
- bubble <= 3;
- end if;
else
- bubble <= bubble - 1;
+ OP2 <= NOP;
+ A2 <= "00000000";
+ B2 <= "00000000";
+ C2 <= "00000000";
end if;
end if;
diff --git a/config_simu.wcfg b/config_simu.wcfg
index 63f6ad1..6a2bf94 100644
--- a/config_simu.wcfg
+++ b/config_simu.wcfg
@@ -13,7 +13,7 @@
-
+
clk
clk
@@ -38,12 +38,6 @@
etage 1
label
-
- label
- bubble
- bubble
- bubble
-
op1[7:0]
op1[7:0]
@@ -70,6 +64,28 @@
etage 2
label
+
+ op2_in[7:0]
+ op2_in[7:0]
+ UNSIGNEDDECRADIX
+ true
+ #ff00ff
+
+
+ a2_in[7:0]
+ a2_in[7:0]
+ UNSIGNEDDECRADIX
+
+
+ b2_in[7:0]
+ b2_in[7:0]
+ UNSIGNEDDECRADIX
+
+
+ c2_in[7:0]
+ c2_in[7:0]
+ UNSIGNEDDECRADIX
+
op2[7:0]
op2[7:0]
@@ -212,7 +228,7 @@
[2]
rb[2]
- SIGNEDDECRADIX
+ UNSIGNEDDECRADIX
[1]
@@ -261,4 +277,58 @@
true
#008080
+
+ aleas
+ label
+
+ alea_write_p3
+ alea_write_p3
+
+
+ alea_write_p3_reg[3:0]
+ alea_write_p3_reg[3:0]
+ UNSIGNEDDECRADIX
+ true
+ #808000
+
+
+ alea_write_p2
+ alea_write_p2
+
+
+ alea_write_p2_reg[3:0]
+ alea_write_p2_reg[3:0]
+ UNSIGNEDDECRADIX
+ true
+ #808000
+
+
+ alea_read_b_p1
+ alea_read_b_p1
+
+
+ alea_read_b_p1_reg[3:0]
+ alea_read_b_p1_reg[3:0]
+ UNSIGNEDDECRADIX
+ true
+ #808000
+
+
+ alea_read_c_p1
+ alea_read_c_p1
+
+
+ alea_read_c_p1_reg[3:0]
+ alea_read_c_p1_reg[3:0]
+ UNSIGNEDDECRADIX
+ true
+ #808000
+
+
+ alea
+ alea
+ true
+ #ff0000
+
+