Browse Source

improve aleas handling

Simard Yohan 5 months ago
parent
commit
7409c89285
2 changed files with 162 additions and 43 deletions
  1. 84
    35
      CPU.vhd
  2. 78
    8
      config_simu.wcfg

+ 84
- 35
CPU.vhd View File

@@ -24,7 +24,6 @@ architecture Behavioral of CPU is
24 24
 	
25 25
 	constant MX1: std_logic_vector(8 downto 0) := "100111110";
26 26
 	constant MX2: std_logic_vector(8 downto 0) := "000011110";
27
-	constant needBubbles: std_logic_vector(8 downto 0) := "111111110";
28 27
 
29 28
 	COMPONENT ALU
30 29
 	PORT(
@@ -100,6 +99,10 @@ architecture Behavioral of CPU is
100 99
 	signal instr_memory_q : std_logic_vector(31 downto 0);
101 100
 
102 101
 	-- Etage 1
102
+	signal OP1_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
103
+	signal A1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
104
+	signal B1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
105
+	signal C1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
103 106
 	signal IP : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
104 107
 	signal OP1 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
105 108
 	signal A1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
@@ -107,12 +110,19 @@ architecture Behavioral of CPU is
107 110
 	signal C1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
108 111
 
109 112
 	-- Etage 2
113
+	signal OP2_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
114
+	signal A2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
115
+	signal B2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
116
+	signal C2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
110 117
 	signal OP2 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
111 118
 	signal A2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
112 119
 	signal B2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
113 120
 	signal C2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
114 121
 
115 122
 	-- Etage 3
123
+	signal OP3_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
124
+	signal A3_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
125
+	signal B3_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
116 126
 	signal OP3 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
117 127
 	signal A3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
118 128
 	signal B3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
@@ -121,9 +131,21 @@ architecture Behavioral of CPU is
121 131
 	signal OP4 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
122 132
 	signal A4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
123 133
 	signal B4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
134
+	signal OP4_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
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+	signal A4_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
136
+	signal B4_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
124 137
 
125
-	signal bubble : integer := 3;
126
-
138
+	-- Aleas
139
+	signal alea_write_P3: std_logic := '0';
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+	signal alea_write_P3_reg: std_logic_vector(3 downto 0) := "0000";
141
+	signal alea_write_P2: std_logic := '0';
142
+	signal alea_write_P2_reg: std_logic_vector(3 downto 0) := "0000";
143
+	signal alea_read_B_P1: std_logic := '0';
144
+	signal alea_read_B_P1_reg: std_logic_vector(3 downto 0) := "0000";
145
+	signal alea_read_C_P1: std_logic := '0';
146
+	signal alea_read_C_P1_reg: std_logic_vector(3 downto 0) := "0000";
147
+	signal alea: std_logic := '0';
148
+	
127 149
 begin
128 150
    myalu: ALU PORT MAP (
129 151
           A => alu_a,
@@ -178,51 +200,78 @@ begin
178 200
 	data_memory_addr <= A3 when (OP3 = STORE) else B3;
179 201
 	data_memory_data <= B3;
180 202
 	
181
-	C1 <= instr_memory_q(7 downto 0) when (bubble = 0) else "00000000";
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-	B1 <= instr_memory_q(15 downto 8) when (bubble = 0) else "00000000";
183
-	A1 <= instr_memory_q(23 downto 16) when (bubble = 0) else "00000000";
184
-	OP1 <= instr_memory_q(31 downto 24) when (bubble = 0) else NOP;
203
+	-- Etage 1
204
+	OP1_in <= instr_memory_q(31 downto 24);
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+	A1_in <= instr_memory_q(23 downto 16);
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+	B1_in <= instr_memory_q(15 downto 8);
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+	C1_in <= instr_memory_q(7 downto 0);
185 208
 	
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+	OP1 <= OP1_in;
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+	A1 <= A1_in;
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+	B1 <= B1_in;
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+	C1 <= C1_in;
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+
214
+	-- Etage 2
215
+	OP2_in <= OP1;
216
+	A2_in <= A1;
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+	B2_in <= registers_QA when (MX1(to_integer(unsigned(OP1))) = '1') else B1;
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+	C2_in <= registers_QB;
219
+	
220
+	-- Etage 3
221
+	OP3_in <= OP2;
222
+	A3_in <= A2;
223
+	B3_in <= ALU_S when (MX2(to_integer(unsigned(OP2))) = '1') else B2;
224
+	
225
+	-- Etage 4
226
+	OP4_in <= OP3;
227
+	A4_in <= A3;
228
+	B4_in <= data_memory_Q when (OP3 = LOAD) else B3;
229
+	
230
+	-- Aleas
231
+	alea_write_P3 <= '0' when (OP4_in = NOP or OP4_in = STORE) else '1';
232
+	alea_write_P3_reg <= A4_in(3 downto 0);
233
+	alea_write_P2 <= '0' when (OP3_in = NOP or OP3_in = STORE) else '1';
234
+	alea_write_P2_reg <= A3_in(3 downto 0);
235
+	alea_read_B_P1 <= '0' when (OP1_in = NOP or OP1_in = AFC or OP1_in = LOAD) else '1';
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+	alea_read_B_P1_reg <= B1_in(3 downto 0);
237
+	alea_read_C_P1 <= '1' when (OP1_in = ADD or OP1_in = MUL or OP1_in = DIV or OP1_in = SOU) else '0';
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+	alea_read_C_P1_reg <= C1_in(3 downto 0);
239
+	
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+	alea <= '1' 
241
+		when (
242
+			(alea_write_P3 = '1' and alea_read_B_P1 = '1' and alea_write_P3_reg = alea_read_B_P1_reg) or
243
+			(alea_write_P3 = '1' and alea_read_C_P1 = '1' and alea_write_P3_reg = alea_read_C_P1_reg) or
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+			(alea_write_P2 = '1' and alea_read_B_P1 = '1' and alea_write_P2_reg = alea_read_B_P1_reg) or
245
+			(alea_write_P2 = '1' and alea_read_C_P1 = '1' and alea_write_P2_reg = alea_read_C_P1_reg))
246
+		else '0';
247
+
186 248
 	process
187 249
 	begin
188 250
 	wait until CLK'event and CLK='1';
189 251
 		if (halted = '0') then
190 252
 			-- Etage 3 -> 4
191
-			OP4 <= OP3;
192
-			A4 <= A3;
193
-			if (OP3 = LOAD) then
194
-				B4 <= data_memory_Q;
195
-			else
196
-				B4 <= B3;
197
-			end if;
253
+			OP4 <= OP4_in;
254
+			A4 <= A4_in;
255
+			B4 <= B4_in;
198 256
 			
199 257
 			-- Etage 2 -> 3
200
-			OP3 <= OP2;
201
-			A3 <= A2;
202
-			if (MX2(to_integer(unsigned(OP2))) = '1') then
203
-				B3 <= ALU_S;
204
-			else
205
-				B3 <= B2;
206
-			end if;
258
+			OP3 <= OP3_in;
259
+			A3 <= A3_in;
260
+			B3 <= B3_in;
207 261
 			
208 262
 			-- Etage 1 -> 2
209
-			OP2 <= OP1;
210
-			A2 <= A1;
211
-			if (MX1(to_integer(unsigned(OP1))) = '1') then
212
-				B2 <= registers_QA;
213
-			else 
214
-				B2 <= B1;
215
-			end if;
216
-			C2 <= registers_QB;
263
+			if (alea = '0') then
264
+				OP2 <= OP2_in;
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+				A2 <= A2_in;
266
+				B2 <= B2_in;
267
+				C2 <= C2_in;
217 268
 			
218
-			-- Memoire -> etage 1
219
-			if (bubble = 0) then
220 269
 				IP <= IP + 1;
221
-				if (needBubbles(to_integer(unsigned(instr_memory_q(31 downto 24)))) = '1') then
222
-					bubble <= 3;
223
-				end if;
224 270
 			else
225
-				bubble <= bubble - 1;
271
+				OP2 <= NOP;
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+				A2 <= "00000000";
273
+				B2 <= "00000000";
274
+				C2 <= "00000000";
226 275
 			end if;
227 276
 	end if;
228 277
 		

+ 78
- 8
config_simu.wcfg View File

@@ -13,7 +13,7 @@
13 13
          </top_modules>
14 14
       </db_ref>
15 15
    </db_ref_list>
16
-   <WVObjectSize size="12" />
16
+   <WVObjectSize size="13" />
17 17
    <wvobject fp_name="/cpu_test/clk" type="logic" db_ref_id="1">
18 18
       <obj_property name="ElementShortName">clk</obj_property>
19 19
       <obj_property name="ObjectShortName">clk</obj_property>
@@ -38,12 +38,6 @@
38 38
    <wvobject fp_name="group39" type="group">
39 39
       <obj_property name="label">etage 1</obj_property>
40 40
       <obj_property name="DisplayName">label</obj_property>
41
-      <wvobject fp_name="/cpu_test/uut/bubble" type="other" db_ref_id="1">
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-         <obj_property name="DisplayName">label</obj_property>
43
-         <obj_property name="ElementShortName">bubble</obj_property>
44
-         <obj_property name="ObjectShortName">bubble</obj_property>
45
-         <obj_property name="label">bubble</obj_property>
46
-      </wvobject>
47 41
       <wvobject fp_name="/cpu_test/uut/op1" type="array" db_ref_id="1">
48 42
          <obj_property name="ElementShortName">op1[7:0]</obj_property>
49 43
          <obj_property name="ObjectShortName">op1[7:0]</obj_property>
@@ -70,6 +64,28 @@
70 64
    <wvobject fp_name="group40" type="group">
71 65
       <obj_property name="label">etage 2</obj_property>
72 66
       <obj_property name="DisplayName">label</obj_property>
67
+      <wvobject fp_name="/cpu_test/uut/op2_in" type="array" db_ref_id="1">
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+         <obj_property name="ElementShortName">op2_in[7:0]</obj_property>
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+         <obj_property name="ObjectShortName">op2_in[7:0]</obj_property>
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+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
71
+         <obj_property name="UseCustomSignalColor">true</obj_property>
72
+         <obj_property name="CustomSignalColor">#ff00ff</obj_property>
73
+      </wvobject>
74
+      <wvobject fp_name="/cpu_test/uut/a2_in" type="array" db_ref_id="1">
75
+         <obj_property name="ElementShortName">a2_in[7:0]</obj_property>
76
+         <obj_property name="ObjectShortName">a2_in[7:0]</obj_property>
77
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
78
+      </wvobject>
79
+      <wvobject fp_name="/cpu_test/uut/b2_in" type="array" db_ref_id="1">
80
+         <obj_property name="ElementShortName">b2_in[7:0]</obj_property>
81
+         <obj_property name="ObjectShortName">b2_in[7:0]</obj_property>
82
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
83
+      </wvobject>
84
+      <wvobject fp_name="/cpu_test/uut/c2_in" type="array" db_ref_id="1">
85
+         <obj_property name="ElementShortName">c2_in[7:0]</obj_property>
86
+         <obj_property name="ObjectShortName">c2_in[7:0]</obj_property>
87
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
88
+      </wvobject>
73 89
       <wvobject fp_name="/cpu_test/uut/op2" type="array" db_ref_id="1">
74 90
          <obj_property name="ElementShortName">op2[7:0]</obj_property>
75 91
          <obj_property name="ObjectShortName">op2[7:0]</obj_property>
@@ -212,7 +228,7 @@
212 228
          <wvobject fp_name="/cpu_test/uut/reg/rb[2]" type="array" db_ref_id="1">
213 229
             <obj_property name="ElementShortName">[2]</obj_property>
214 230
             <obj_property name="ObjectShortName">rb[2]</obj_property>
215
-            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
231
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
216 232
          </wvobject>
217 233
          <wvobject fp_name="/cpu_test/uut/reg/rb[1]" type="array" db_ref_id="1">
218 234
             <obj_property name="ElementShortName">[1]</obj_property>
@@ -261,4 +277,58 @@
261 277
       <obj_property name="UseCustomSignalColor">true</obj_property>
262 278
       <obj_property name="CustomSignalColor">#008080</obj_property>
263 279
    </wvobject>
280
+   <wvobject fp_name="group61" type="group">
281
+      <obj_property name="label">aleas</obj_property>
282
+      <obj_property name="DisplayName">label</obj_property>
283
+      <wvobject fp_name="/cpu_test/uut/alea_write_p3" type="logic" db_ref_id="1">
284
+         <obj_property name="ElementShortName">alea_write_p3</obj_property>
285
+         <obj_property name="ObjectShortName">alea_write_p3</obj_property>
286
+      </wvobject>
287
+      <wvobject fp_name="/cpu_test/uut/alea_write_p3_reg" type="array" db_ref_id="1">
288
+         <obj_property name="ElementShortName">alea_write_p3_reg[3:0]</obj_property>
289
+         <obj_property name="ObjectShortName">alea_write_p3_reg[3:0]</obj_property>
290
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
291
+         <obj_property name="UseCustomSignalColor">true</obj_property>
292
+         <obj_property name="CustomSignalColor">#808000</obj_property>
293
+      </wvobject>
294
+      <wvobject fp_name="/cpu_test/uut/alea_write_p2" type="logic" db_ref_id="1">
295
+         <obj_property name="ElementShortName">alea_write_p2</obj_property>
296
+         <obj_property name="ObjectShortName">alea_write_p2</obj_property>
297
+      </wvobject>
298
+      <wvobject fp_name="/cpu_test/uut/alea_write_p2_reg" type="array" db_ref_id="1">
299
+         <obj_property name="ElementShortName">alea_write_p2_reg[3:0]</obj_property>
300
+         <obj_property name="ObjectShortName">alea_write_p2_reg[3:0]</obj_property>
301
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
302
+         <obj_property name="UseCustomSignalColor">true</obj_property>
303
+         <obj_property name="CustomSignalColor">#808000</obj_property>
304
+      </wvobject>
305
+      <wvobject fp_name="/cpu_test/uut/alea_read_b_p1" type="logic" db_ref_id="1">
306
+         <obj_property name="ElementShortName">alea_read_b_p1</obj_property>
307
+         <obj_property name="ObjectShortName">alea_read_b_p1</obj_property>
308
+      </wvobject>
309
+      <wvobject fp_name="/cpu_test/uut/alea_read_b_p1_reg" type="array" db_ref_id="1">
310
+         <obj_property name="ElementShortName">alea_read_b_p1_reg[3:0]</obj_property>
311
+         <obj_property name="ObjectShortName">alea_read_b_p1_reg[3:0]</obj_property>
312
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
313
+         <obj_property name="UseCustomSignalColor">true</obj_property>
314
+         <obj_property name="CustomSignalColor">#808000</obj_property>
315
+      </wvobject>
316
+      <wvobject fp_name="/cpu_test/uut/alea_read_c_p1" type="logic" db_ref_id="1">
317
+         <obj_property name="ElementShortName">alea_read_c_p1</obj_property>
318
+         <obj_property name="ObjectShortName">alea_read_c_p1</obj_property>
319
+      </wvobject>
320
+      <wvobject fp_name="/cpu_test/uut/alea_read_c_p1_reg" type="array" db_ref_id="1">
321
+         <obj_property name="ElementShortName">alea_read_c_p1_reg[3:0]</obj_property>
322
+         <obj_property name="ObjectShortName">alea_read_c_p1_reg[3:0]</obj_property>
323
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
324
+         <obj_property name="UseCustomSignalColor">true</obj_property>
325
+         <obj_property name="CustomSignalColor">#808000</obj_property>
326
+      </wvobject>
327
+      <wvobject fp_name="/cpu_test/uut/alea" type="logic" db_ref_id="1">
328
+         <obj_property name="ElementShortName">alea</obj_property>
329
+         <obj_property name="ObjectShortName">alea</obj_property>
330
+         <obj_property name="UseCustomSignalColor">true</obj_property>
331
+         <obj_property name="CustomSignalColor">#ff0000</obj_property>
332
+      </wvobject>
333
+   </wvobject>
264 334
 </wave_config>

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