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Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
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Lacroix Raphael c462cd7fe7 WIP tried stuff
2023-05-29 21:57:46 +02:00
..
xsim.dir WIP tried stuff 2023-05-29 21:57:46 +02:00
compile.log WIP tried stuff 2023-05-29 21:57:46 +02:00
compile.sh WIP tried stuff 2023-05-29 21:57:46 +02:00
elaborate.log WIP tried stuff 2023-05-29 21:57:46 +02:00
elaborate.sh WIP tried stuff 2023-05-29 21:57:46 +02:00
simulate.log added test files for full CPU 2023-05-29 21:37:49 +02:00
simulate.sh WIP tried stuff 2023-05-29 21:57:46 +02:00
Test_Alu.tcl Added VHDL part of the project 2023-05-29 13:58:26 +02:00
Test_Alu_behav.wdb WIP tried stuff 2023-05-29 21:57:46 +02:00
Test_Alu_vhdl.prj WIP tried stuff 2023-05-29 21:57:46 +02:00
webtalk.jou WIP tried stuff 2023-05-29 21:57:46 +02:00
webtalk.log WIP tried stuff 2023-05-29 21:57:46 +02:00
webtalk_31637.backup.jou Added VHDL part of the project 2023-05-29 13:58:26 +02:00
webtalk_31637.backup.log Added VHDL part of the project 2023-05-29 13:58:26 +02:00
webtalk_32017.backup.jou Added VHDL part of the project 2023-05-29 13:58:26 +02:00
webtalk_32017.backup.log Added VHDL part of the project 2023-05-29 13:58:26 +02:00
webtalk_334386.backup.jou work in progress ALU 2023-05-29 20:30:32 +02:00
webtalk_334386.backup.log work in progress ALU 2023-05-29 20:30:32 +02:00
webtalk_831173.backup.jou Added VHDL part of the project 2023-05-29 13:58:26 +02:00
webtalk_831173.backup.log Added VHDL part of the project 2023-05-29 13:58:26 +02:00
xelab.pb WIP tried stuff 2023-05-29 21:57:46 +02:00
xsim.ini Added VHDL part of the project 2023-05-29 13:58:26 +02:00
xvhdl.log WIP tried stuff 2023-05-29 21:57:46 +02:00
xvhdl.pb WIP tried stuff 2023-05-29 21:57:46 +02:00