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Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new
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Lacroix Raphael 12859bebe9 Merge remote-tracking branch 'origin/master' 
# Conflicts:
#	VHDL/ALU/ALU.cache/wt/project.wpc
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.reloc
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
2023-05-29 21:42:46 +02:00
..
AleaControler.vhd added the alea handling and IP implementation 2023-05-29 19:54:40 +02:00
ALU.vhd Update ALU 2023-05-29 21:39:05 +02:00
InstructionMemory.vhd Added VHDL part of the project 2023-05-29 13:58:26 +02:00
IP.vhd added the alea handling and IP implementation 2023-05-29 19:54:40 +02:00
Memory.vhd Added VHDL part of the project 2023-05-29 13:58:26 +02:00
Pipeline.vhd added test files for full CPU 2023-05-29 21:37:49 +02:00
register.vhd Added VHDL part of the project 2023-05-29 13:58:26 +02:00
Registers.vhd Added VHDL part of the project 2023-05-29 13:58:26 +02:00
Stage_Di_Ex.vhd Added VHDL part of the project 2023-05-29 13:58:26 +02:00
Stage_Ex_Mem.vhd Added VHDL part of the project 2023-05-29 13:58:26 +02:00
Stage_Li_Di.vhd Added VHDL part of the project 2023-05-29 13:58:26 +02:00
Stage_Mem_Re.vhd Added VHDL part of the project 2023-05-29 13:58:26 +02:00