58 lines
1.8 KiB
VHDL
58 lines
1.8 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12.05.2023 16:14:24
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-- Design Name:
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-- Module Name: ALU - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ALU is
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Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
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B : in STD_LOGIC_VECTOR (7 downto 0);
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Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div
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S : out STD_LOGIC_VECTOR (7 downto 0);
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N : out STD_LOGIC;
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O : out STD_LOGIC;
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Z : out STD_LOGIC;
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C : out STD_LOGIC);
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end ALU;
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architecture Behavioral of ALU is
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signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000";
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begin
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res <= (x"00" & A) + (x"00" & B) when (Ctrl_Alu = "000") else
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(x"00" & A) - (x"00" & B) when (Ctrl_Alu = "001") else
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A * B when (Ctrl_Alu = "010"); -- else
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-- A mod B when (Ctrl_Alu = "100");
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S <= res(7 downto 0);
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N <= '1' when B > A and Ctrl_Alu="001" else '0';
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O <= '1' when res(15 downto 8) > x"01" and Ctrl_Alu="010" else '0';
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Z <= '1' when res(15 downto 0) = x"0" else '0';
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C <= '1' when res(8)='1' and (Ctrl_Alu = "000") else '0';
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end Behavioral;
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