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-- Company: 
-- Engineer: 
-- 
-- Create Date: 12.05.2023 16:14:24
-- Design Name: 
-- Module Name: ALU - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
    Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
           B : in STD_LOGIC_VECTOR (7 downto 0);
           Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div 
           S : out STD_LOGIC_VECTOR (7 downto 0);
           N : out STD_LOGIC;
           O : out STD_LOGIC;
           Z : out STD_LOGIC;
           C : out STD_LOGIC);
end ALU;

architecture Behavioral of ALU is
    signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000";     
begin
    res <= (x"00" & A) + (x"00" & B) when (Ctrl_Alu = "000") else
           (x"00" & A) - (x"00" & B) when (Ctrl_Alu = "001") else
            A * B when (Ctrl_Alu = "010"); -- else
            -- A mod B when (Ctrl_Alu = "100");
    S <= res(7 downto 0);
    N <= '1' when B > A and Ctrl_Alu="001" else '0';
    O <= '1' when res(15 downto 8) > x"01" and Ctrl_Alu="010" else '0';
    Z <= '1' when res(15 downto 0) = x"0" else '0';
    C <= '1' when res(8)='1' and (Ctrl_Alu = "000") else '0';
end Behavioral;