90 lines
No EOL
2.3 KiB
VHDL
90 lines
No EOL
2.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 29.06.2021 08:40:33
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-- Design Name:
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-- Module Name: Test_ScreenSystem - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Test_ScreenSystem is
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-- Port ( );
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end Test_ScreenSystem;
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architecture Behavioral of Test_ScreenSystem is
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component ScreenSystem is
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Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
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vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
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vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
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Hsync : out STD_LOGIC;
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Vsync : out STD_LOGIC;
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btnC : in STD_LOGIC;
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CLK : in STD_LOGIC
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);
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end component;
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signal my_vgaRed : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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signal my_vgaBlue : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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signal my_vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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signal my_Hsync : STD_LOGIC := '0';
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signal my_Vsync : STD_LOGIC := '0';
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signal my_btnC : STD_LOGIC := '0';
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signal my_CLK : STD_LOGIC := '0';
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constant CLK_period : time := 9.26 ns;
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begin
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instance : ScreenSystem
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port map (
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vgaRed => my_vgaRed,
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vgaBlue => my_vgaBlue,
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vgaGreen => my_vgaGreen,
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Hsync => my_Hsync,
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Vsync => my_Vsync,
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btnC => my_btnC,
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CLK => my_CLK
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);
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CLK_process :process
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begin
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my_CLK <= '0';
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wait for CLK_period/2;
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my_CLK <= '1';
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wait for CLK_period/2;
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end process;
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process
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begin
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wait;
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end process;
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end Behavioral; |