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-- Company: 
-- Engineer: 
-- 
-- Create Date: 29.06.2021 08:40:33
-- Design Name: 
-- Module Name: Test_ScreenSystem - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_ScreenSystem is
--  Port ( );
end Test_ScreenSystem;

architecture Behavioral of Test_ScreenSystem is

    component ScreenSystem is
      Port (  vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
              vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
              vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
              Hsync    : out STD_LOGIC;
              Vsync    : out STD_LOGIC;
              
              
              btnC : in STD_LOGIC;
              CLK  : in  STD_LOGIC
       );
     end component;
       
    signal my_vgaRed   : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal my_vgaBlue  : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal my_vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal my_Hsync    : STD_LOGIC := '0';
    signal my_Vsync    : STD_LOGIC := '0';
    
    
    signal my_btnC : STD_LOGIC := '0';
    signal my_CLK  : STD_LOGIC := '0';

    constant CLK_period : time := 9.26 ns;

begin
    instance : ScreenSystem
    port map    (
                 vgaRed => my_vgaRed,
                 vgaBlue => my_vgaBlue,
                 vgaGreen => my_vgaGreen,
                 Hsync => my_Hsync,
                 Vsync => my_Vsync,
                 btnC => my_btnC,
                 CLK => my_CLK
                );
    
    CLK_process :process
    begin
        my_CLK <= '0';
        wait for CLK_period/2;
        my_CLK <= '1';
        wait for CLK_period/2;
    end process;
    
    process 
    begin   
        wait;
    end process;  
      
end Behavioral;