160 lines
5.2 KiB
Text
160 lines
5.2 KiB
Text
#-----------------------------------------------------------
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# Vivado v2016.4 (64-bit)
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# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
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# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
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# Start of session at: Mon Apr 19 10:14:33 2021
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# Process ID: 6416
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# Current directory: C:/Users/Hp/Documents/Processeur
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16404 C:\Users\Hp\Documents\Processeur\Processeur.xpr
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# Log file: C:/Users/Hp/Documents/Processeur/vivado.log
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# Journal file: C:/Users/Hp/Documents/Processeur\vivado.jou
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#-----------------------------------------------------------
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start_gui
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open_project C:/Users/Hp/Documents/Processeur/Processeur.xpr
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launch_simulation
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source Test_LC.tcl
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close_sim
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launch_simulation
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source Test_LC.tcl
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add_bp {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} 44
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remove_bps -file {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} -line 44
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close_sim
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launch_simulation
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launch_simulation
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source Test_LC.tcl
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close_sim
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launch_simulation
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source Test_LC.tcl
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close_sim
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launch_simulation
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source Test_LC.tcl
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close_sim
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launch_simulation
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source Test_LC.tcl
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close_sim
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launch_simulation
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source Test_LC.tcl
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close_sim
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launch_simulation
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source Test_LC.tcl
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set_property SOURCE_SET sources_1 [get_filesets sim_1]
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close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd w ]
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add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd
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set_property top Test_Etage3_Calcul [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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launch_simulation
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launch_simulation
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launch_simulation
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launch_simulation
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source Test_Etage3_Calcul.tcl
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close_sim
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launch_simulation
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source Test_Etage3_Calcul.tcl
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set_property SOURCE_SET sources_1 [get_filesets sim_1]
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close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd w ]
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add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
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set_property top Test_Etage4_Memoire [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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launch_simulation
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launch_simulation
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source Test_Etage4_Memoire.tcl
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set_property top Test_Etage3_Calcul [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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current_sim simulation_10
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close_sim
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launch_simulation
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source Test_Etage3_Calcul.tcl
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set_property top Test_Etage4_Memoire [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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current_sim simulation_11
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close_sim
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launch_simulation
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source Test_Etage4_Memoire.tcl
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close_sim
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launch_simulation
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source Test_Etage4_Memoire.tcl
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close_sim
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launch_simulation
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source Test_Etage4_Memoire.tcl
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set_property SOURCE_SET sources_1 [get_filesets sim_1]
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close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd w ]
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add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd
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set_property top Test_Etage2_5_Registres [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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launch_simulation
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source Test_Etage2_5_Registres.tcl
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close_sim
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launch_simulation
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source Test_Etage2_5_Registres.tcl
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close_sim
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launch_simulation
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source Test_Etage2_5_Registres.tcl
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close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd w ]
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add_files C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd
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set_property SOURCE_SET sources_1 [get_filesets sim_1]
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close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd w ]
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add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd
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set_property top Test_Pipeline [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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launch_simulation
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launch_simulation
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launch_simulation
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launch_simulation
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source Test_Pipeline.tcl
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add_wave {{/Test_Pipeline/instance/Instruction_1_to_2}} {{/Test_Pipeline/instance/Instruction_2_to_3}} {{/Test_Pipeline/instance/Instruction_3_to_4}} {{/Test_Pipeline/instance/Instruction_4_to_5}}
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run all
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run 10 us
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run 10 us
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restart
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run 10 us
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restart
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run 10 us
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close_sim
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launch_simulation
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source Test_Pipeline.tcl
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restart
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run 10 us
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close_sim
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launch_simulation
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current_sim simulation_18
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launch_simulation
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launch_simulation
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launch_simulation
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source Test_Pipeline.tcl
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restart
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run 10 us
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close_sim
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launch_simulation
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source Test_Pipeline.tcl
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restart
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run 10 us
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save_wave_config {C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg}
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add_files -fileset sim_1 -norecurse C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
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set_property xsim.view C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg [get_filesets sim_1]
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close_sim
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launch_simulation
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source Test_Pipeline.tcl
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restart
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run 10 us
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restart
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run 10 us
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restart
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run 10 us
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close_sim
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launch_simulation
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current_sim simulation_18
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launch_simulation
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launch_simulation
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source Test_Pipeline.tcl
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restart
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run 10 us
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close_sim
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launch_simulation
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source Test_Pipeline.tcl
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restart
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run 10 us
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close_sim
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launch_simulation
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source Test_Pipeline.tcl
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restart
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run 10 us
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