#----------------------------------------------------------- # Vivado v2016.4 (64-bit) # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017 # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017 # Start of session at: Mon Apr 19 10:14:33 2021 # Process ID: 6416 # Current directory: C:/Users/Hp/Documents/Processeur # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16404 C:\Users\Hp\Documents\Processeur\Processeur.xpr # Log file: C:/Users/Hp/Documents/Processeur/vivado.log # Journal file: C:/Users/Hp/Documents/Processeur\vivado.jou #----------------------------------------------------------- start_gui open_project C:/Users/Hp/Documents/Processeur/Processeur.xpr launch_simulation source Test_LC.tcl close_sim launch_simulation source Test_LC.tcl add_bp {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} 44 remove_bps -file {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} -line 44 close_sim launch_simulation launch_simulation source Test_LC.tcl close_sim launch_simulation source Test_LC.tcl close_sim launch_simulation source Test_LC.tcl close_sim launch_simulation source Test_LC.tcl close_sim launch_simulation source Test_LC.tcl close_sim launch_simulation source Test_LC.tcl set_property SOURCE_SET sources_1 [get_filesets sim_1] close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd w ] add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd set_property top Test_Etage3_Calcul [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation launch_simulation launch_simulation launch_simulation source Test_Etage3_Calcul.tcl close_sim launch_simulation source Test_Etage3_Calcul.tcl set_property SOURCE_SET sources_1 [get_filesets sim_1] close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd w ] add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd set_property top Test_Etage4_Memoire [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation launch_simulation source Test_Etage4_Memoire.tcl set_property top Test_Etage3_Calcul [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] current_sim simulation_10 close_sim launch_simulation source Test_Etage3_Calcul.tcl set_property top Test_Etage4_Memoire [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] current_sim simulation_11 close_sim launch_simulation source Test_Etage4_Memoire.tcl close_sim launch_simulation source Test_Etage4_Memoire.tcl close_sim launch_simulation source Test_Etage4_Memoire.tcl set_property SOURCE_SET sources_1 [get_filesets sim_1] close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd w ] add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd set_property top Test_Etage2_5_Registres [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation source Test_Etage2_5_Registres.tcl close_sim launch_simulation source Test_Etage2_5_Registres.tcl close_sim launch_simulation source Test_Etage2_5_Registres.tcl close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd w ] add_files C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd set_property SOURCE_SET sources_1 [get_filesets sim_1] close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd w ] add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd set_property top Test_Pipeline [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation launch_simulation launch_simulation launch_simulation source Test_Pipeline.tcl add_wave {{/Test_Pipeline/instance/Instruction_1_to_2}} {{/Test_Pipeline/instance/Instruction_2_to_3}} {{/Test_Pipeline/instance/Instruction_3_to_4}} {{/Test_Pipeline/instance/Instruction_4_to_5}} run all run 10 us run 10 us restart run 10 us restart run 10 us close_sim launch_simulation source Test_Pipeline.tcl restart run 10 us close_sim launch_simulation current_sim simulation_18 launch_simulation launch_simulation launch_simulation source Test_Pipeline.tcl restart run 10 us close_sim launch_simulation source Test_Pipeline.tcl restart run 10 us save_wave_config {C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg} add_files -fileset sim_1 -norecurse C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg set_property xsim.view C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg [get_filesets sim_1] close_sim launch_simulation source Test_Pipeline.tcl restart run 10 us restart run 10 us restart run 10 us close_sim launch_simulation current_sim simulation_18 launch_simulation launch_simulation source Test_Pipeline.tcl restart run 10 us close_sim launch_simulation source Test_Pipeline.tcl restart run 10 us close_sim launch_simulation source Test_Pipeline.tcl restart run 10 us