67 lines
2 KiB
VHDL
67 lines
2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13.04.2021 10:19:15
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-- Design Name:
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-- Module Name: System - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity System is
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Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
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flag : out STD_LOGIC_VECTOR (3 downto 0);
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sw : in STD_LOGIC_VECTOR (15 downto 0);
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btnC : in STD_LOGIC;
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btnL : in STD_LOGIC;
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btnR : in STD_LOGIC);
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end System;
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architecture Structural of System is
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component ALU
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Generic (Nb_bits : Natural);
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Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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OP : in STD_LOGIC_VECTOR (1 downto 0);
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S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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N : out STD_LOGIC;
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O : out STD_LOGIC;
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Z : out STD_LOGIC;
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C : out STD_LOGIC);
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end component;
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signal aux: STD_LOGIC_VECTOR (1 downto 0);
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signal aux4: STD_LOGIC;
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signal aux5: STD_LOGIC;
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signal aux6: STD_LOGIC;
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signal aux7: STD_LOGIC;
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begin
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aux <= "01" when btnC = '1' else
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"10" when btnR = '1' else
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"11" when btnL = '1' else
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"00";
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flag <= aux4 & aux5 & aux6 & aux7;
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My_ALU: ALU generic map (Nb_bits => 8) port map(sw (15 downto 8), sw (7 downto 0), aux, led, aux4, aux5, aux6, aux7);
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end Structural;
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